Description
XPS_FX2 is a communication core to interface Xilinx Microblaze soft processor and a popular USB High Speed microcontroller Cypress CY7C68013A (also known as EzUSB FX2).
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Maximal supported bandwidth is normally limited by |
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title | FD[7:0] bus pins: FPGA <-> USB FX2 microcontroller connection; |
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Pin Name | FPGA Direction | FX2 direction | Description | In the reference design case (1) |
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FD[7:0] | Bidirectional | Bidirectional | FD[0:7] are used for byte data transfer between FPGA and USB FX2 μC. | If the custom IP blocks and MicroBlaze API Commands (MB Commands) are used, data bytes array could be transfered between - TE USB FX2 module's DRAM (MicroBlaze's software) and
- host computer's memory (host computer's software)
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title | Peripheral internal structure block scheme |
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XPS_FX2 Core Design Parameters
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title | XPS_FX2 Core Design Parameters |
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Feature/Description | Parameter Name | Allowable Values | Default Value | VHDL Type |
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System Parameters | Target FPGA family | C_FAMILY | spartan3, spartan3e, spartan3a, spartan3adsp, spartan3an, virtex2p, virtex4, qvirtex4, qrvirtex4, virtex5 | virtex5 | string | PLB Parameters | PLB base address | C_BASEADDR | Valid Address | None | std_logic_vector | PLB high address | C_HIGHADDR | Valid Address | None | std_logic_vector | PLB least significant address bus width | C_SPLB_AWIDTH | 32 | 32 | integer | PLB data width | C_SPLB_DWIDTH | 32, 64, 128 | 32 | integer | Shared bus topology | C_SPLB_P2P | 0 = Shared bus topology | 0 | integer | PLB master ID bus Width | C_SPLB_MID_WIDTH | log2(C_SPLB_NUM_ MASTERS) with a minimum value of 1 | 1 | integer | Number of PLB masters | C_SPLB_NUM_MASTERS | 1 - 16 | 1 | integer | Width of the slave data bus | C_SPLB_NATIVE_DWIDTH | 32 | 32 | integer | Burst support | C_SPLB_SUPPORT_BURSTS | 0 = No burst support | 0 | integer | XPS_FX2 Parameters | Size of Transmit FIFO | C_TX_FIFO_KBYTE | 2, 4, 8,16,32 | 2 | integer | Size of Receive FIFO | C_RX_FIFO_KBYTE | 0, 2 | 2 | integer | Using Address FIFO (1) | C_USE_ADDR_FIFO | 0 (not working) | 0 | integer | Shift transmit FIFO clock by 180 degrees (2) | C_TX_FIFO_CLK_180 | 0, 1 | 0 | integer |
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(1) Address FIFO was designed to avoid FIFO draining before the EP ADDRESS changing. Will be fixed in further releases. (2) Set to 1 only if the user experience 8-bit data shifting after a received packet of data. Normally set to 0. |
XPS_FX2 Core I/O Signals
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title | XPS_FX2 I/O Signal Descriptions |
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Name | Interface | I/O | Initial State | Description |
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ChipScope[0:31] | - | O | - | Debug port | USB_IFCLK | - | I | - | USB 48MHz clock | USB_SLRD | - | O | 0 | USB Data Read strobe | USB_SLWR | - | O | 0 | USB Data Write strobe | USB_FLAGA | - | I | - | USB programmable status flag (not used) | USB_FLAGB | - | I | - | USB TX FIFO full flag | USB_FLAGC | - | I | - | USB TX FIFO empty flag | USB_FLAGD | - | I | - | USB RX FIFO empty flag | USB_SLOE | - | O | 0 | Toggles FX2 IO buffer (1=read from USB) | USB_PKTEND | - | O | 0 | Commences current packet (if smaller than 512 bytes) | USB_FIFOADR[1:0] | - | O | 0 | Selects USB endpoint: - "00"=EP2,
- "01"=EP4,
- "10"=EP6,
- "11"=EP8
| USB_FD[7:0] | - | I/O | 0 | USB tristate data Bus | TX_FIFO_Clk | - | I | - | TX FIFO clock | RX_FIFO_Clk | - | I | - | RX FIFO clock | TX_FIFO_DIN[0:31] | FIFO_IN | I | - | TX FIFO input data | TX_FIFO_VLD | FIFO_IN | I | - | TX FIFO data valid strobe | TX_FIFO_RDY | FIFO_IN | O | 0 | TX FIFO is ready flag | RX_FIFO_DOUT[0:31] | FIFO_OUT | O | zeros | RX FIFO output data | RX_FIFO_VLD | FIFO_OUT | O | 0 | RX FIFO data valid strobe | RX_FIFO_RDY | FIFO_OUT | I | - | RX FIFO is ready flag | IP2INTC_Irpt | - | O | 0 | Processor interrupt | OTHERS ARE PLBv4.6 SIGNALS | PLBv4.6 | - | - | - |
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Writing and reading to/from FIFO_IN and FIFO_OUT ports
The point to point unidirectional buses use simple handshaking protocol.
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title | FIFO high speed communication ports principle of operation |
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XPS_FX2 Core Registers
XPS_FX2 has a full access of a microprocessor to the core functionality through a 5 user 32-bit and 7 IPIF Interrupt registers attached to PLBv4.6 bus.
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Note |
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The First (LSB) interrupt from user_logic is masked on the left!! |
Details of XPS_FX2 Core Registers
The parts of the registers (or the whole registers) with a non-capital designation (e.g. wr_fifo_rst) are usually the names of the HDL signals connected to the described register.
Control Register (CR)
The Control Register is used to control basic peripheral functions. All the bit flags are assembled here.
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title | Packet end timount and USB_PKTEND |
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(1) Endpoint EP8 is read only and is switched automatically when data arrives. To achieve maximal throughput use only one endpoint and prevent TX FIFO draining (TX FIFO empty should not occur). (2) Packet end timeout timer automatically asserts USB_PKTEND signal when TX_FIFO is empty for a programmed number of cycles and current USB EndPoint FIFO is not empty. Cycle timer is also reset when switched to EP8 – incoming data. The USB_PKTEND send current packet and enables the PC to receive packet smaller than 512 bytes. If user setup the timer properly then the packets are automatically send when there is no more data available in the TX_FIFO. |
FIFOs Threshold Register (FTR)
This register is used to setup thresholds for interrupt triggering when FIFO occupancy reaches set number of words. For RX FIFO the prog_full flag goes high when number of words in a FIFO is higher than threshold. For TX FIFO the prog_empty flag goes high when number of words in a FIFO is lower than threshold.
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title | FIFOs Threshold Register (FTR) bits |
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Status Register (SR)
In the status register the peripheral reports of the current status. The tx_fifo_count can have 9-13 bits according to size of the TX_FIFO. This register is usually accessed using 16-bit reads
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title | Status Register (SR) bits |
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Bits | Name | Description | Reset Value |
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19-31 | tx_fifo_count | Transmit FIFO occupancy in words | 0 | 18 | tx_fifo_overflow | Transmit FIFO overflow flag | 0 | 17 | tx_fifo_full | Transmit FIFO full flag | 0 | 16 | tx_fifo_empty | Transmit FIFO empty flag | 1 | 7-15 | rx_fifo_count | Receive FIFO occupancy in words | 0 | 3 | rx_fifo_prog_full | Receive FIFO programmable full flag | 0 | 2 | rx_fifo_underflow | Receive FIFO underflow flag | 0 | 1 | rx_fifo_full | Receive FIFO full flag | 0 | 0 | rx_fifo_empty | Receive FIFO empty flag | 1 |
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FIFO Write Register (FWR)
Single beat write to this register puts a single word (4 bytes) to TX FIFO. For proper operation PLB clock frequency should be less or equal to TX_FIFO_Clk.
FIFO Read Register (FRR)
Single beat read from this register pops one word (4 bytes) from RX FIFO. For proper operation PLB clock frequency should be less or equal to RX_FIFO_Clk.
Interrupt enable/pending registers
With INTR_IPIER register the user can enable/disable peripheral interrupt sources. With INTR_IPISR the user can identify interrupt source. Writing a value to INTR_IPISR also clears interrupt.
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title | Interrupt enable/pending registers |
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Programming model
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By setting control register (CR) make sure that user not override the previously set bits. |
Example 1
Resetting the TX_FIFO:
1. Write 0x00000001 to CR
2. Write 0x00000000 to CR
Example 2
Resetting the RX_FIFO:
1. Write 0x00000002 to CR
2. Write 0x00000000 to CR
Example 3
Setting the endpoint address to EP4
1. Write 0x00000010 to CR
Example 4 (if Reference Design is used): test XPS_NPI_DMA and XPS_FX2 using MB Commands
XPS_NPI_DMA and XPS_FX2 custom IP blocks are both necessary to connect (throgh USB connection) host computer's software and TE USB FX2 module's DRAM.
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