Page History
| Company | Trenz Electronic Gmbh |
|---|---|
| PCN Number | PCN-20160211 |
| Title | TE0712-01 to TE0712-02 revision change |
| Subject | Change of hardware revision |
| Issue Date | 2014073020160211 |
Products Affected
This change affects all Trenz Electronic TE0712 SoMs of the first revision: TE0712-01-*.
TE0712-01-* | TE0712-02-* |
Changes
#1 added pullup on SPI "hold"
Type: Enhancement
Reason: Makes SPI accessible in case Quad bit is cleared and HOLD pin is pulled low by on chip pulldown
Impact: None
#2 added Testpoints
Type: Improvement
Reason: Improvement of production tests
Impact: None
#3 Routed MII clock pin additionally to FPGA
Type: Enhancement
Reason: Allows DDR clock to be different from PHY clock
Impact: None
#4 Added Testpoints
Type: Layout change
Reason: Improve production testing
Impact: None
#5 routed one more PLL clock output to FPGA
Type: Enhancement
Reason: One more clock is available from PLL
Impact: None
#6 Added I2C SCL Pullup
Type: Enhancement
Reason: It allows AXI_I2C to be used without defining on-chip pullup on SCL line
Impact: None
Method of Identification
The model code and revision number (e.g. TE0712-01 or TE0720-02) are printed on the top side of the PCB.
Production Shipment Schedule
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Overview
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