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Table of Contents

Table of Contents
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Overview

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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/TE0600

Trenz Electronic GigaBee XC6SLX series are industrial-grade FPGA micromodules integrating a leading-edge Xilinx Spartan-6 LX FPGA, Gigabit Ethernet transceiver (physical layer), two independent banks of 16-bit-wide 128/512 MBytes DDR3 SDRAM, 16 MBytes SPI Flash memory for configuration and operation, and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via robust board-to-board (B2B) connectors.

...

All this on a tiny footprint, smaller than half a credit card, at the most competitive price.

Block diagram

Image RemovedImage Added

Block diagram of the GigaBee XC6SLX board

Main components

Pictures were photographed from revision 3 and serve for informational purposes only.

Top side:

  • Xilinx Spartan-6 LX FPGA
  • clock generator
  • 10/100/1000 Mbps Ethernet PHY
  • protected 1-Wire EEPROM
  • DDR3-SDRAM
  • DC-DC converters

...

  • B2B connector J1
  • B2B connector J2
  • Flash memory

Key features

  • Industrial-grade Xilinx Spartan-6 LX FPGA micromodule (LX45 / LX100 / LX150)

  • 10/100/1000 tri-speed Gigabit Ethernet transceiver (PHY)

  • 2 x 16-bit-wide 1 Gb (128 MB) or 4 Gb (512 MB) DDR3 SDRAM

  • 128 Mb (16 MB) SPI Flash memory (for configuration and operation) accessible through:

  • 1 kb protected 1-Wire EEPROM with SHA-1 Engine

  • JTAG port (SPI indirect)

  • FPGA configuration through:

    • B2B connector

    • JTAG port

    • SPI Flash memory

  • Plug-on module with 2 × 100-pin high-speed hermaphroditic strips

  • Up to 52 differential, up to 109 single-ended (+ 1 dual-purpose) FPGA I/O pins available on B2B strips

  • 46.0 A 0 A x 1.2 V 2 V power rail

  • 3.0 A x 1.5 A x 1.5 V 5 V power rail

  • 2x 1A x 2.5V power rail

  • 125 MHz reference clock signal

  • Single-ended custom oscillator (option)

  • eFUSE bit-stream encryption (LX100 or larger)

  • 1 user LED

  • Evenly-spread supply pins for good signal integrity

Additional assembly options are available for cost or performance optimization upon request.

Initial Delivery State

Storage device name

Content

Notes

SPI Flash memory

Blinky Demo

 

protected 1-Wire EEPROM

not programmed 


Power Consumption

Power consumption of GigaBee XC6SLX modules highly depend on the FPGA design implemented. Some typical power consumptions are provided below for the following reference systems:

  • Boards – GigaBee XC6SLX 45/100/150

  • Base board – TE0603-02

  • Power supply – 5 V from 5 V for baseboard

  • Connected Gigabit Ethernet cable

FPGA typeUnconfiguredConfigured with Web-server reference design
LX450.15 A0.6 A
LX1000.17 A0.5 A
LX1500.2 A0.5 A

Detailed Description

Power Supply

The nominal supply voltage of the GigaBee XC6SLX is 3.3 volt. The minimum supply voltage is 3.0 volt. The maximum supply voltage is 3.45 volt.

Warning
titleWarning

Supply voltages beyond the range might affect to device reliability, or even cause permanent damage of the device!

Board power supply diagram

Image RemovedImage Added

Power Supply Sources

GigaBee XC6SLX board must be powered at least in one of the following two ways:

...

Please make sure that your logic design does not draw more RMS current per pin than specified in section Board-to-board Connectors.

FPGA banks VCCIO power supply

FPGA VCCIO power options are shown below. Default values for configurable voltages are shown in braces.

BankSupply voltage
B0VCCIO 0

VCCIO0 (3.

3 V

3V)

B1VCCIO 1 VCCIO1 (1.5 V5V)
B2VCCIO2 (3.3 V3V)
B3VCCIO3 (1.5 V5V)

Bank 0 power supply VCCIO 0 VCCIO0 can be configured by user to 3.3 V3 V, 2.5 V 5 V or 1.5 V5 V, see Chapter VCCIO0 Power Rail. Bank Banks 1 and 3 VCCIO supply voltage is configured to 1.5 V 5 V to communicate with DDR3 SDRAM memory chip.

By special request, modules can be supplied without DDR3 SDRAM chips. Contact Trenz Electronic support for details.

On-board Power Rails

GigaBee XC6SLX has the following power rails on-board.

3.3V Power Rail

It is the main internal power rail and must be supplied from an external power source.

It supplies the other following power rails:

  • 1.2V / 4 A 6A on-board high-efficiency switching voltage regulator;
  • 1.5V / 1.5 A 3A on-board high-efficiency switching voltage regulator;
  • 2.5V 0.8 A 1A linear voltage regulator;
  • VCCIO0 power rail (option) (: if zero-resistor R80 is not populated and zero-resistor R79 is populated).
1.2V Power Rail

It is converted from the 3.3V rail by a switching voltage regulator and can provide up to 4.0 A 6A to:

  • FPGA VCCINT power supply pins;
  • Ethernet PHY;
  • J1 connector.
1.5V Power Rail

It is converted from the 3.3V rail by a switching voltage regulator and can provide up to 1.5 A 3A to:

  • DDR3 SDRAM;
  • Vref1 / Vref2 DDR3 SDRAM reference voltages;
  • FPGA bank banks 1 and 3 VCCO;
  • J1 J2 connector.
2.5V Power Rail

It is converted from the 3.3V rail by a linear voltage regulator and can provide up to 0.8 A 1A to:

  • VCCAUX power rail;
  • Ethernet physical layer;
  • J1 connector;
  • J2 connector VCCIO0 power rail (option: if zero-resistor R80 is populated and zero-resistor R79 is not populated).
VCCAUX Power Rail

It is converted from the 3.3V rail by a linear voltage regulator and can provide up to 0.8 A 1A to:

  • FPGA auxiliary circuits;
  • J2 connector.
VCCIO0 Power Rail

There are 4 options to supply this rail:

  1. from 3.3 V power rail (if zero-resistor R79 is populated1 and R80 is not);
  2. from 2.5 V power rail (if zero-resistor R80 is populated and R79 is not);
  3. from 1.5 V power rail (if zero-resistors R79 and R80 are not populated and VCCIO0 connected to 1.5 V power rail);
  4. from an external power source through J2 B2B connector (pins 1, 3, 5, 7, 9) (if R79 and R80 are not populated)

It supplies:

  • FPGA bank 0 VCCO.

Figure below show simplified schematic of power options. Dashed resistors are not populated by default.

...

power-rail
name

nominal
voltage(V)

maximum
current (A)

power
source

system
supply

user
supply

3.3V3.3

2.4
(3.3 option)

J1, J2module

J1 (≤1.2 A)
J2 (≤1.2 A,
≤2.1 option)

2.5V2.51.0.83.3V ? linearEthernet

J1 (≤0.3 A)
J2 (option)

1.5V1.513.503.3V ? switch

DDR3 SDRAM
VCCO (1+3)

J1 (≤0.3 A)
1.2V1.246.03.3V ? switch

VCCINT
Ethernet

J1 (≤0.6 A)
VCCAUX2.51.0.83.3V ? linearFPGAJ2 (≤0.3 A)
VCCCIO01.2, 1.5, 1.8, 2.5, 3.30.9J2 or 2.5V or 3.3VVCCO (0)J2 (≤0.9 A)

Power Supervision

Power-on Reset

During power-on, the /RESET line is first asserted. Thereafter, the supply voltage supervisor monitors the power supply rail 3.3V and keeps the /RESET line active (low) as long as the supply rail remains below the threshold voltage (2.93 volt). An internal timer delays the return of the /RESET line to the inactive state (high) to ensure proper system reset prior to a regular system start-up. The typical delay time td of 200 ms starts after the supply rail has risen above the threshold voltage.

...

After this delay, the /RESET line is reset (high) and the FPGA configuration can start. When the supply rail voltage drops below the threshold voltage, the /RESET line becomes active (low) again and stays active (low) as long as the rail voltage remains below the threshold voltage (2.93 volt). Once the rail voltage raises again and remains over the threshold voltage for more than the typical delay time td of 200 ms, the /RESET line returns to the inactive state (high) to allow a new system start-up.

Power Fail

GigaBee XC6SLX integrates a power-fail comparator which can be used for low-battery detection, power-fail warning, or for monitoring a power supply other than the main supply 3.3 V. When the voltage of the PFI (power-fail comparator input, input pin 16 of connector J2) line drops below 1.25 volt, the /PFO (power-fail comparator output, FPGA pin A2, label IO_L83P_3) line becomes active (low). The user application can sense this line to take action. To set a power fail threshold higher than 1.25 volt, the user can implement a simple resistive voltage divider on the carrier board.

Board-to-board Connectors

Include Page
4 x 5 SoM LSHM B2B Connectors
4 x 5 SoM LSHM B2B ConnectorsIN:Samtec LSHMIN:Samtec LSHM

EPROM

GigaBee XC6SLX board contains a Maxim DS2502-E48 node address chip with factory-programmed valid MAC-48 address and 768 bits of OTP-EPROM memory for user data.

...

More information can be found at the Maxim DS2432 product page.

DDR3 SDRAM Memory

The board contains two 1 Gb (128 MB) or 4 Gb (512 MB) DDR3 SDRAM chips. Data width of each chip is 16 bit. DDR3 memory connected to FPGA bank 1 and FPGA bank 3. Spartan-6 Memory controller Blocks operations can be merged to implement effective 32-bit memory interface. Refer Xilinx XAPP496 for detailed information.

Flash Memory

GigaBee XC6SLX board contains 128 Mb (16 MB) serial flash memory chip Winbond W25Q128FV (W25Q128BV till REV 02) (U11). This serial flash chip can operate as general SPI memory mode and in double or quad modes. Usage of dual and quad modes increase bandwidth up to 40 MB/s.

For more information see Winbond W25Q128FV W25Q128JVEIQ (W25Q128BV till REV 02or W25Q128FV in old revisions) product overview.

Flash can be programmed in several ways:

...

Serial flash signals connection

Ethernet

The board contains a Marvell Alaska Ethernet PHY chip (88E1111) operating at 10/100/1000 Mb/s. The board supports GMII interface mode with the FPGA. Configuration details:

...

Note
titleCaution

For correct operation of the Marvell PHY it is required that PHY Reset pin sees valid low level each time power is applied and also during any brownout situations where system Power is removed for short time, but some pins are not at valid logic levels.

Solutions:

  1. if GbE PHY is not used PHY reset pin can be tied off to GND
  2. if PLL is used from PHY clock, then PLL "locked" output can be used to reset PHY - as long PLL is not locked, it will keep PHY in reset
  3. Reset pulse generation circuit clocked from FPGA internal configuration clock, this circuit can force PHY reset pin to low when external clock from PHY is not available
  4. any custom Reset circuit that is guaranteed to drive PHY reset to low level at least once after FPGA configuration when PHY clock is not running.
  5. any user logic that is guaranteed to drive PHY reset low after FPGA configuration (without using PHY clock).

Explanation: Marvell PHY samples the MODE pins ONLY when it sees low level on PHY reset input, it does not sample those pins during short power off situations (if the reset pin holds high level because of pin capacitance and high impedance of the pins)! So it is possible that the PHY mode is reset, but the mode pins are not sampled again - this yields in mode setting where 125MHz reference clock from PHY is not available.

Oscillators

The module has one 25 MHz oscillator for Ethernet PHY (U9). Ethernet PHY provides clock multiplication and resulting 125 MHz clock acts as a system and user clock for the FPGA (FPGA input pin AA12).

Note
titleCaution

Note: For correct generation start, PHY should receive reset pulse. Recommended way to do it it's to connect PHY reset signal  (ETHERNET_PHY_RST_N) to LOCKED output of corresponding DCM (DCM which use 125 MHz from PHY).

The module also provides the footprint for custom additional 3.3 V 3 V single-ended oscillator (U12) which can be installed as an option used as a system and user clock for the FPGA (FPGA input pin Y13).

User LED

The module contains one user active-low LED connected to FPGA output pin T20. To access more LEDs, use a carrier board and drive FPGA signals connected to B2B connectors. As LED connected to FPGA bank with configurable VCCIO to light LED FPGA pin should in '0' (low) state. To disable LED FPGA pin should be in 'Z' (High impedance).

Watchdog

GigaBee XS6LX has a watchdog timer that is periodically triggered by a positive or negative transition of the WDI (watchdog input) line (FPGA pin V9). When the supervising system fails to re-trigger the watchdog circuit within the time-out interval (min 1.1 s, typ 1.6 s, max 2.3 s), the /WDO (watchdog output) line becomes active (low). This event also re-initializes the watchdog timer.

...

Unused IOB Pins option selection.

 


In the standard assembly, the /WDO (watchdog output) line is left unconnected1 and the only possibility to reset the module is by driving the /MR (master reset) line active (low) through pin 18 of connector J2.

...

Note
titleCaution

If alternate assembly is used, pin 18 of connector J2 must be left unconnected.

Configuration Options

The FPGA on GigaBee XC6SLX board can be configured by means of the following devices:

  • Xilinx download cable (JTAG)
  • SPI Flash memory

JTAG Configuration

The FPGA can be configured through the JTAG interface. JTAG signals are connected to B2B connector J2. When GigaBee XC6SLX board is used with the TE0603 carrier board, the JTAG interface can be accessed via connectors J5 and J6 on the carrier board.

Flash Configuration

Default configuration option for FPGA is “Master Serial/SPI”. The bit-stream for the FPGA is stored in a serial Flash chip (U11). See chapter 2.7 Flash Memory for additional information.

eFUSE Programming

eFUSE programming feature is not directly supported by GigaBee XC6SLX modules, but it is possible to use it. To program eFUSE, please follow the steps below:
  • Connect VCCAUX to 3.3V power rail.
    On TE0603 it can be done by connecting J5 pin 2 or J6 “VREF” (VCCAUX) to J1 any pin from 1,2,3,4 (3.3V). See Figure below.
  • Program eFUSE using JTAG cable and iMPACT software.
  • Remove power supply connections to VCCAUX

B2B Connectors Pin Descriptions

This section describes how the various pins on B2B connectors J1 and J2 connects to TE0600 on-board components. There are five main signal types connected to B2B connectors:

...

FPGA BankSingle-endedDifferentialTotalVCCIO
Bank 012245VCCIO 0 VCCIO0 (3.3 V3V)
Bank 11613VCCIO 1 VCCIO1 (1.5 V5V)
Bank 232145VCCIO2 (3.3 V3V)
Bank 3036VCCIO3 (1.5 V5V)

 552109 

B2B signals count

Pin Labeling

FPGA user signals connected to B2B connectors are characterized by the "B2B_Bx_Lyy_p" naming convention, where:

...

Remaining signals use custom names.

Pin Numbering

Note that GigaBee XC6SLX have hermaphroditic B2B connectors. A feature of  hermaphroditic connector numbering is that connected signal numbers don't match. Odd signals on module connect to even signals on baseboard. For example module signal 1 to baseboard signal 2, module signal 2 to baseboard signal 1, module signal 3 to baseboard signal 4 and so on.

Pin Types

Most pins of B2B connectors J1 and J2 are general-purpose, user-defined I/O pins (GPIOs). There are, however, up to 8 different functional types of pins on the TE0600, as outlined in Table below. In pin-out tables Table 11 and Table 12, the individual pins are colour-coded according to pin type as in Table below. 


TE0600 pin types

type
colour code		description
DIOUnrestricted, general-purpose differential user-I/O pin.
SIOUnrestricted, general-purpose user-I/O pin.
CONFIGDedicated configuration signals.
PWRMGMTControl and status signals for the power-saving Suspend mode.
JTAGDedicated JTAG signals.
GNDDedicated ground pin. All must be connected.
TETrenz Electronic specific pin type.
See the description of each pin in the user manual for additional information on the corresponding signals.
POWPower signals.
SPISPI signals.
PHYEthernet PHY signals.

...

See “Spartan-6 FPGA SelectIO Resources” page 38 for detailed information.

External Bank 2 differential clock connection

TE0600 -02 module have optional connection to FPGA bank 2 differential clock input pins. To provide connection from B2B_B2_L41_P signal to Y13 FPGA pin, zero-resistor R69 should be soldered. To provide connection B2B_B2_L41_N signal to AB13 FPGA pin, zero-resistor R81 should be soldered. Note that in this case optional user oscillator U13 can't be used.

J1 Pin-out

J1 pin-out

J1 pinNetType

FPGA pin

Net LengthJ1 pinNetTypeFPGA pinNet Length
13.3VPOW--2GNDGND--
33.3VPOW--4PHY_MDI0_PPHY--
53.3VPOW--6PHY_MDI0_NPHY--
73.3VPOW--8GNDGND--
93.3VPOW--10PHY_MDI1_PPHY--
113.3VPOW--12PHY_MDI1_NPHY--
133.3VPOW--14PHY_AVDDPHY--
153.3VPOW--16PHY_MDI2_PPHY--
17PHY_L10PHY--18PHY_MDI2_NPHY--
19PHY_L100PHY--20GNDGND--
21PHY_L1000PHY--22PHY_MDI3_PPHY--
23PHY_DUPPHY--24PHY_MDI3_NPHY--
25PHY_LED_TXPHY--26GNDGND--
27PHY_LED_RXPHY--28ENTE--
29GNDGND--30INITCONFIGT6-
31B2B_B2_L57_NDIOAB4812.66mm3056mm32B2B_B2_L32_NSIOAB1189.12mm2307mm
33B2B_B2_L57_PDIOAA4912.84mm3446mm34GNDGND--
35B2B_B2_L49_NDIOAB6810.66mm9076mm36B2B_B2_L60_PDIOT7912.96mm8674mm
37B2B_B2_L49_PDIOAA6911.58mm4038mm38B2B_B2_L60_NDIOR71113.16mm3583mm
392.5VPOW--40B2B_B2_L59_NDIOR81113.42mm4941mm
411.2VPOW--42B2B_B2_L59_PDIOR91113.36mm4584mm
431.2VPOW--44GNDGND--
45B2B_B2_L48_NDIOAB7914.98mm447mm46B2B_B2_L44_NDIOY101113.34mm4331mm
47B2B_B2_L48_PDIOY71014.98mm6069mm48B2B_B2_L44_PDIOW101013.21mm0478mm
49B2B_B2_L45_NDIOAB81011.60mm3986mm50B2B_B2_L42_NDIOW1179.52mm889mm
51B2B_B2_L45_PDIOAA811.053mm642mm52B2B_B2_L42_PDIOV11810.36mm2701mm
53GNDGND--54GNDGND--
55B2B_B2_L43_NDIOAB913.75mm1392mm56B2B_B2_L18_PDIOV13710.94mm5384mm
57B2B_B2_L43_PDIOY91213.97mm5123mm58B2B_B2_L18_NDIOW13610.96mm0455mm
59B2B_B2_L41_NDIOAB10, AB131015.33mm7999mm60B2B_B2_L8_NDIOU16912.92mm2993mm
61B2B_B2_L41_PDIOAA10, Y131116.01mm1771mm62B2B_B2_L8_PDIOU17912.94mm2993mm
63GNDGND--64GNDGND--
65B2B_B2_L21_PDIOY151314.12mm8399mm66B2B_B2_L11_PDIOV17810.31mm5343mm
67B2B_B2_L21_NDIOAB151214.37mm6254mm68B2B_B2_L11_NDIOW17710.29mm1532mm
69B2B_B2_L15_PDIOY171413.20mm2958mm70B2B_B2_L6_PDIOW1879.40mm5851mm
71B2B_B2_L15_NDIOAB1713.77mm1454mm72B2B_B2_L6_NDIOY1869.94mm1811mm
73GNDGND--74GNDGND--
75B2B_B2_L31_NSIOAB121214.30mm3436mm76B2B_B2_L5_PDIOY1968.18mm398mm
77SUSPENDSYSN151921.23mm1709mm78B2B_B2_L5_NDIOAB1968.12mm3535mm
79VBATTCONFIGR17-80B2B_B2_L9_NDIOV18810.43mm2621mm
81VFSCONFIGP16-82B2B_B2_L9_PDIOV19810.36mm1752mm
83RFUSECONFIGP15-84GNDGND--
85AWAKESYST191416.15mm1634mm86B2B_B2_L4_NDIOT171113.88mm4321mm
87CSO_BSPIT5-88B2B_B2_L4_PDIOT181113.96mm8014mm
89GNDGND--90GNDGND--
91CCLKSPIY21-92B2B_B2_L29_NSIOY121315.58mm9734mm
93MISOSPIAA20-94B2B_B2_L10_NDIOR151718.01mm4735mm
95MOSISPIAB20-96B2B_B2_L10_PDIOR161618.97mm3045mm
97MISO3SPIU13-98B2B_B2_L2_NDIOAB2158.06mm425mm
99MISO2SPIU14-100B2B_B2_L2_PDIOAA2168.19mm4085mm

J2 Pin-out

J2 Pin-out

J2 pinNetTypeFPGA pinNet LengthJ2 pinNetTypeFPGA pinNet Length
1VCCIO0POW--23.3VPOW--
3VCCIO0POW--43.3VPOW--
5VCCIO0POW--63.3VPOW--
7VCCIO0POW--83.3VPOW--
9VCCIO0POW--103.3VPOW--
11B2B_PROGBCONFIG--123.3VPOW--
13HSWAPENCONFIGA3-14B2B_B0_L1SIOA49.017mm4715mm
15B2B_B3_L60_NDIOB157.44mm5418mm16PFITE--
17B2B_B3_L60_PDIOB256.27mm7655mm18/MRTE--
191.5VPOW--20GNDGND--
21B2B_B3_L9_NDIOT31921.36mm4246mm22B2B_B0_L2_PDIOC51012.17mm0314mm
23B2B_B3_L9_PDIOT41821.76mm2943mm24B2B_B0_L2_NDIOA5911.60mm8853mm
25B2B_B0_L3_PDIOD669.76mm0158mm26B2B_B0_L4_NDIOA6710.65mm8292mm
27B2B_B0_L3_NDIOC658.66mm4466mm28B2B_B0_L4_PDIOB6811.71mm2228mm
29GNDGND--30GNDGND--
31B2B_B3_L59_PDIOJ71114.90mm0801mm32B2B_B0_L5_NDIOA7811.59mm7078mm
33B2B_B3_L59_NDIOH81113.71mm8896mm34B2B_B0_L5_PDIOC7911.54mm9983mm
35B2B_B0_L32_PDIOD769.93mm1276mm36B2B_B0_L6_NDIOA8710.42mm6094mm
37B2B_B0_L32_NDIOD869.87mm1646mm38B2B_B0_L6_PDIOB8810.43mm9961mm
39GNDGND--40GNDGND--
41B2B_B0_L7_NDIOC869.62mm1167mm42B2B_B0_L8_NDIOA9912.28mm2657mm
43B2B_B0_L7_PDIOD969.71mm3073mm44B2B_B0_L8_PDIOC9912.92mm5699mm
45B2B_B0_L33_NDIOC1058.66mm889mm46B2B_B0_L34_NDIOA10711.58mm7216mm
47B2B_B0_L33_PDIOD1069.76mm1201mm48B2B_B0_L34_PDIOB10811.60mm6163mm
49GNDGND--50GNDGND--
51B2B_B0_L36_PDIOD1168.76mm6976mm52B2B_B0_L35_NDIOA11812.89mm4283mm
53B2B_B0_L36_NDIOC1258.87mm3601mm54B2B_B0_L35_PDIOC11912.92mm6535mm
55B2B_B0_L49_PDIOD1469.96mm136mm56B2B_B0_L37_NDIOA12710.52mm7513mm
57B2B_B0_L49_NDIOC1458.96mm7449mm58B2B_B0_L37_PDIOB12811.74mm0849mm
59GNDGND--60GNDGND--
61B2B_B0_L62_PDIOD1579.44mm687mm62B2B_B0_L38_NDIOA13812.38mm5431mm
63B2B_B0_L62_NDIOC1669.95mm5212mm64B2B_B0_L38_PDIOC13912.87mm8448mm
65B2B_B0_L66_PDIOE16810.07mm0885mm66B2B_B0_L50_NDIOA14711.66mm3259mm
67B2B_B0_L66_NDIOD1769.96mm9228mm68B2B_B0_L50_PDIOB14811.87mm4909mm
69GNDGND--70GNDGND--
71B2B_B1_L10_PDIOF16911.56mm3734mm72B2B_B0_L51_NDIOA151012.22mm0938mm
73B2B_B1_L10_NDIOF17811.85mm466mm74B2B_B0_L51_PDIOC151012.67mm5055mm
75B2B_B1_L9_PDIOG161012.59mm5086mm76B2B_B0_L63_NDIOA16711.95mm3551mm
77B2B_B1_L9_NDIOG171012.23mm6008mm78B2B_B0_L63_PDIOB16911.12mm772mm
79GNDGND--80GNDGND--
81B2B_B1_L21_NDIOJ161315.22mm7408mm82B2B_B0_L64_NDIOA17913.55mm5157mm
83B2B_B1_L21_PDIOK161415.41mm9404mm84B2B_B0_L64_PDIOC171013.25mm4806mm
85B2B_B1_L61_PDIOL171417.89mm852mm86B2B_B0_L65_NDIOA18812.51mm4997mm
87B2B_B1_L61_NDIOK181317.59mm4155mm88B2B_B0_L65_PDIOB18912.29mm3889mm
89GNDGND--90GNDGND--
91VCCAUXPOW--92B2B_B1_L20_PDIOA20811.02mm0846mm
93TMSJTAGC18-94B2B_B1_L20_NDIOA21710.82mm7172mm
95TDIJTAGE18-96B2B_B1_L19_PDIOB21912.63mm0803mm
97TDOJTAGA19-98B2B_B1_L19_NDIOB22911.06mm8608mm
99TCKJTAGG15-100B2B_B1_L59SIOP192730.19mm179mm

Signal Integrity Considerations

Traces of differential signals pairs are routed symmetrically (as symmetric pairs).

Traces of differential signals pairs are NOT routed with equal length, although difference in signal lines length is negligible for actual signal frequencies. For applications where traces length has to be matched or timing differences have to be compensated, Tables below abowe list the trace length of I/O signal lines measured from FPGA balls to B2B connector pins.

...

An electronic version of these pin-out tables are available for download from the Trenz Electronic support area of the web site.

Module revisions and assembly variants

Module revision coded by 4 FPGA BR[3:0] pins, which can be read by FPGA firmware. All these pins should be configured to have internal PULLUP.

Signal
FPGA pin		BR3
R19		BR2
P18		BR1
N16		BR0
P17
Revision 011111
Revision 021110
Revision 031101
Revision 041100

Board revisions pin coding 


Main differences between 01 and 02 revisions:

...

  • Optimized placement and routing for DC/DC converters
  • Added thermal vias to mounting holes
  • Added Testpoints
  • Changed Board revision identification to REV03
  • Changed U9 from SIT1602AI-83-33E-25.0000 to SiT8008AI-73-XXS-25.000000E
  • Added Track-it™ Traceability Pad
  • Change SPI Flash from W25Q128BVEIG to W25Q128FVEIG
  • DDR3 changed from IM4G16D3EABG-125I to IM4G16D3FABG-125I for the 4 GBit variants
  • U13 (DS2432P+) is no longer populated by default

...

Main differences between 03 and 04 revisions:

  • Optimized placement and routing
  • More powerful regulators
  • Removed stucked vias
  • Added Testpoints
  • Changed Board revision identification to REV04
  • U12 was fitted for all module assembly variants as default

Module assembly variants coded by 4 zero ohm resistors, connected to FPGA AV[3:0] pins. All these pins should be configures configured to have internal PULLUP.

Signal
FPGA pin		AV3
M18		AV2
M17		AV1
V20		AV0
U19		Speed
grade		SDRAMTemp
grade		Status
TE0600-02[V|B]000022x128MBitCobsolete
TE0600-02[V|B]I000122x128MBitIobsolete
TE0600-02[V|B]F001032x128MBitCobsolete
TE0600-02[V|B]IF001132x128MBitIobsolete
TE0600-02[V|B]MF010032x512MBitC

Assembly variants pin coding

Related Materials and References

obsolete
 TE0600-03[V|B]000022x128MBitCobsolete
TE0600-03[V|B]I000122x128MBitIobsolete
TE0600-03[V|B]F001032x128MBitCobsolete
TE0600-03[V|B]IF001132x128MBitIobsolete
TE0600-03[V|B]MF010032x512MBitCobsolete
TE0600-04-52I11000122x128MBitIfull production
TE0600-04-72C11000022x128MBitCfull production
TE0600-04-72C21010022x512MBitCfull production
TE0600-04-83C21011032x512MBitCfull production
TE0600-04-83I11001132x128MBitIfull production
TE0600-04-83I21011132x512MBitIfull production

Assembly variants pin coding

Related Materials and References

The following documents The following documents provide supplementary information useful with this user manual.

Data Sheets

Documentation Archives

User Guides

Design and Development Tools

Design Resources

Tutorials

Glossary of Abbreviations and Acronyms

(error)A WARNING notice denotes a hazard. It calls attention to an operating procedure, practice, or the like that, if not correctly performed or adhered to, could result in damage to the product or loss of important data. Do not proceed beyond a WARNING notice until the indicated conditions are fully understood and met.
(warning)A CAUTION notice denotes a risk. It calls attention to an operating procedure, practice, or the like that, if not correctly performed or adhered to, could result in a fault. (undesired condition that can lead to an error) Do not proceed beyond a CAUTION notice until the indicated conditions are fully understood and met.

API

application programming interface

B2B

board-to-board

DSP

digital signal processing; digital signal processor

EDK

Embedded Development Kit

IOB

input / output blocks; I/O blocks

IP

intellectual property

ISP

In-System Programmability

OTP

one-time programmable

PB

push button

SDK

Software Development Kit

TE

Trenz Electronic

XPS

Xilinx Platform Studio

Mechanical Dimensions

GigaBee XC6SLX can reach a minimum vertical height of about 8 mm, if B2B connectors are not assembled. The maximum component height on the module board on the top side is about 3.5 mm. The maximum component height on the module board on the bottom side is about 3.0 mm.

...

GigaBee XC6SLX has 4 mounting holes, one in each corner. The module can be fixed by screwing M3 screws (ISO 262) onto a carrier board through those mounting holes.

 


Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

...

The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Weight

GigaBee XC6SLX weighs between 17.1 and 17.3 g with standard connectors.

Document Change History

Document ported to wiki and adapted to web presentation.

Date

Revision

Contributors

Description

2011-10-010.01AIKRelease.
2011-10-050.02AIKAdded B2B pin-out section.
2011-10-060.03AIKReformatted pin-out tables. Added eFUSE programming section.
2011-10-060.04AIKAdded board photos. Additions to eFUSE section.
2011-10-060.05AIKRemoved net length information for nets which can't be measured right.
2011-10-060.06AIKAdded power consumption section.
2011-10-080.07AIKLittle fixes after FDR audit.
2011-10-120.08AIKFix in eFUSE section.
2011-11-110.09AIKAdded pin numbering description for B2B connectors
2012-01-200.10AIKAdded pin compatibility note and manual reference.
2012-04-120.11AIKAdded FPGA banks VCCIO voltages table.
2012-04-171.00FDRUpdated documentation link.
Replaced obsolete ElDesI and RedMine links with current GitHub links.
Updated dating convention.
2012-05-181.01AIKCorrected cross-reference in section 3.2. Corrected LED description.
2012-06-181.02FDRRemoved junction temperature limits under connector current ratings.
2012-07-181.03AIKAdded table with B2B signals summary per FPGA bank
2012-10-302.01AIKFork to 01 and 02 board revisions
2012-11-062.01AIKFixed bank 1 power options
2012-11-212.02AIKUpdated module diagram
2012-11-302.03AIKAdded Ethernet disable note
2012-12-192.04AIKFixed SPI Flash size on block diagram
2013-01-212.05AIKAdded PHY reset note
2013-03-132.06AIKConnectors current chapter moved to separate document
2013-03-132.07AIKChanged Bank 1 power supply description and VCCIO0 sources description
2016-01-29

2.08

AIK

Pause advertise correction
-212.02AIKUpdated module diagram
2012-11-302.03AIKAdded Ethernet disable note
2012-12-192.04AIKFixed SPI Flash size on block diagram
2013-01-212.05AIKAdded PHY reset note
2013-03-132.06AIKConnectors current chapter moved to separate document
2013-03-132.07AIKChanged Bank 1 power supply description and VCCIO0 sources description
2016-01-29

2.08

AIK

Pause advertise correction
2016-11-05
3.00


FDR


Document ported to wiki and adapted to web presentation.
2017-04-03
TTAdded REV03 to assembly Variant Table
2024-03-11
4.00
MT

Added REV04 to assembly variant coding table
Added REV04 to revision coding table
Added main differences between 03 and 04 revisions
Updated nets lengths table
Added info about additional 3.3V single-ended oscillator (U12)
Updated supply diagram
Updated block diagram

2024-03-21
4.01
VY

Updated SoM statuses in Assembly variants pin coding Table 

2016-11-05

Disclaimer

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