Page History

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Overview

Refer to https://shopwiki.trenz-electronic.de/de/Download/?path=Trenz_Electronic/XMODdisplay/PD/TE0790+TRM for the current downloadableonline version of this manual and additionalother technicalavailable documentation of the product.

The Trenz Electronic TE0790 is an universal USB2.0 to JTAG, UART and GPIO adapter based on the FTDI FT2232H USB2 IC. The adapter board converts signals from USB2.0 to standard serial or parallel interfaces of Embedded Systems like JTAG, SPI, I²C and UART.
The board is equipped with a programmable System Controller CPLD provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family) to control the signals of the configured interfaces. The data stream of the USB2.0 port can be also converted to 8 independent GPIO's or used as FIFO.

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• Xmod form-factor
  • size: 20 x 25 mm
  • M3 mounting hole
• FT2232H
  • USB2.0 port High Speed (480 Mbps) and Full Speed (12 Mbps) compatible
  • Entire USB protocol handled on the chip
  • USB2.0 to JTAG, SPI and I²C conversion provided by the IC's Multi-Protocol Synchronous Serial Engine (MPSSE)
  • USB2.0 to UART conversion
  • Channel B UART RX/TX LED's
  • Mini-USB B connector (more rigid then micro-USB)
  • 93C56 EEPROM
• Lattice XO2-256 CPLD
  • on board programmable using Lattice tools
  • 8 universal I/O pins
  • VCCIO either 3.3V or user supplied (1.8 to 3.3V)
  • RED user LED
  • 12 MHz clock from on-board Oscillator
• LDO DCDC for optional USB power
• Variable power supply of the XMOD adapter board
  
  • by Mini USB2.0 connector
  • by base-board through pin header J2
• GREEN GREEN Power-on LED
• User button
• 4 position DIP switch
  • Choose CPLD program mode
  • FTDI EEPROM disable (not implemented in PCB REV 1)
  • Use VIO same as VCC
  • Use VCC from USB

Block Diagram

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Figure 1: TE0790-02 block diagram.

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Table 3: Pin header J2 signal assignment. *pin 1 on header J2
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Figure 3: J2 pin header signal assignment

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Table 4: Pin header J2 signal assignment with standard configuration firmware. *pin 1 on header J2

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Table 5: Pin header J2 signal assignment with standard, but RXD-TXD swapped configuration firmware. *pin 1 on header J2

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Table 6: Pin header J2 signal assignment with DIPFORTy firmware.

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The System Controller CPLD (U1) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The  The SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces.

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The internal routing of the signals on the System Controller CPLD between the USB2.0 interface and pin header J2  J2 depends on its configured firmware. Refer to the Resources Site of the TE0790 CPLD can be set into JTAG chain via  S2-1 DIP Switch. Refer to the TE0790 CPLD Firmware for more information about the currently available System Controller CPLD firmware and for download.

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The DIP-switch S2 is to set different modes of powering the on-board peripherals and their components, the I/O supply voltages .Further functionalities are to secure the EEPROM content and to enable configuring programming the SC adapter board CPLD by JTAG interface:

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Table 8: DIP-switch S2 power setting description.   *Attention: don't supply voltage from base if pin sourced from USB!

User Push Button

• *max. 100mA for external components (It's not recommended to supply FPGA Module)
    Attention: Do not use this setting, if base power supply is connected to this pins!  For more details see Power supply of the adapter board  section.
• **view of XMOD

Table 8: DIP-switch S2 power setting description.

User Push Button

The user push button S1 directly connected to the SC CPLD manipulates pin G of the pin header The user push button S1 directly connected to the SC CPLD manipulates pin G of the pin header J2 by driving it to GND.

On-board LEDs

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Power supply of the adapter board

The adapter on-board's peripherals are powered XMOD can be powered via USB or with 3.3V as supply voltage. If 3.3V and VIO is supplied only by the LDO DCDC U3 (on J2 pins, depending on DIP-switch settings. Max. ~100mA for external components are available on J2 3.3V Pin, if the power supply via USB is used.

Following diagram shows how the settings of the DIP-switches S2-3 and S2-4 ON), the I/O-pins of header J2 deliver max. ~100mA.
If module is powered from base then S2-4 (and most likely S2-3 (VIO) too) must be OFF.

Following diagram shows how the settings of the DIP-switches S2-3 and S2-4 determines the configuration of the on-board voltages:

determines the configuration of the on-board voltages:

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Figure 4: TE0790 on-board voltages configuration

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 Table 10: power rails.

Variants Currently In Production

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• Module size: 24,65mm × 20,02mm.  Please download the assembly diagram for exact numbers.

• Mating height with standard pin headers: 89.5 mm.

• PCB thickness: 1.75 6 mm.

• Highest part on PCB: approx. 8.75 7 mm. Please download the step model for exact numbers.

All dimensions are given in millimeters and mil.

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Figure 5: Module physical dimensions drawing.

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Table 15: Document change history.

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