Page History
USB FX2 microcontroller Configuration (RAM Firmware)
You can use CyConsole ("Options" > "EZ-USB Interface" > "Download" and a .hex or .bix file) or CyControl ("Program FX2 > RAM" and a .hex or .iic file) to directly program the firmware file (.hex, .bix or .iic Firmware file) into the USB FX2 microcontroller's RAM.
Add 2 images.
You can also use OpenFutNet: if used for Firwmare Recovery Boot or Firmware Upgade both EEPROM and RAM are programmed.
| Notewarning |
|---|
| If you don't also write the IIC EEPROM ("Options" > "EZ-USB Interface" > "Lg EEPROM" for CyConsole and xxx "Program>FX2 64KB EEPROM" for CyControl), the new firmware is lost if the TE USB FX2 module goes under reset or power off/on cycle. |
IIC EEPROM Configuration (EEPROM Firmware)
| Tip |
|---|
if If the TE USB FX2 module exit from reset or is powered on, the IIC EEPROM content programs/configures the USB FX2 microcontroller RAM |
| Scroll pdf title | ||
|---|---|---|
| ||
|
You can use CyConsole and CyControl ("Lg EEPROM") and CyControl ("Program>FX2 64KB EEPROM") to directly program the .iic Firmware file into the IIC EEPROM connected to USB FX2 microcontroller.
Add 2 images.
You can also use OpenFutNet: if used for Firwmare Recovery Boot or Firmware Upgade both EEPROM and RAM are programmed.
| Notewarning |
|---|
The firmware actually changes (it runs on USB FX2 microcontroller's RAM) only when
|
FPGA Configuration (bitstream, RAM-like image)
| Warningnote |
|---|
| If you don't also write the SPI Flash memory, the new bitstream image is lost if the TE USB FX2 module goes under reset or power off/on cycle. |
...
- B2B connector
- JTAG
- Slave Parallel (SelectMAP)
- Slave Parallel
- 6-pin JTAG header connector
- 6-pin SPI header connector (TE0300 only)
- USB connector (in fact, SPI Flash memory is used: OpenFutNet or another softwares writes the bitstream image in the SPI Flash and, after SPI Flash writing is complete, the FPGA read the SPI Flash content to configure itself)
SPI Flash memory (see the next section)
| Note |
|---|
| Programming using JTAG interface provide convenient and fast way to test FPGA project. FPGA configuration programmed this way is volatile and lost after reset or power cycle. |
For further information on
- Xilinx Spartan-3E FPGA
- Xilinx Spartan-3A DSP configuration modes, please consult the documentation listed in chapter 17 Related Materials and References.
- Xilinx Spartan-6
...
...
SPI Flash Configuration (bitstream, PROM image)
| Tip |
|---|
| If the TE USB FX2 module exit from reset state or is powered on (in the default state of switches), the SPI Flash content programs/configures the FPGA. |
| Scroll pdf title | |||||||||
|---|---|---|---|---|---|---|---|---|---|
| |||||||||
 |
The bit-stream for the FPGA is stored in the SPI Flash. To use this bit-stream source FPGA configuration option is set to “Master Serial/SPI”. See 2.8 SPI Flash Bus links for additional information for every case.
SPI Flash can be programmed in several ways:
Direct programming by via USB controller (; it is usually done by Firmware Upgrade Tools like Python OpenFut and C# OpenFutNet).
Indirect SPI programming via FPGA pins, controlled by JTAG (can be done using Xilinx iMPACT); it is done by Xilinx iMPACT via JTAG. See Appendix A. Indirect SPI Programming using iMPACT.
Direct SPI programming by FPGA, using an SPI core (via FPGA pins; the FPGA project should contain SPI interface core and the software to work with it : only if iMPACT GUI (SPI interface and SW required are automatically created by Xilinx iMPACT tool). Only if Xilinx iMPACT tool is version 11.x or below, see Xilinx AR#36156)).
SPI Flash can be programmed using the following connection:
- USB connector
- B2B connector
- JTAG
- Slave Parallel (SelectMAP)
- Slave Serial
- 6-pin JTAG header connector
...
- 6-pin SPI header connector (TE0300 only)
| Scroll pdf title | |||||||||
|---|---|---|---|---|---|---|---|---|---|
| |||||||||
|
Overview
Content Tools