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JTAG Interface

Ethernet PHY

Ethernet pins connections to Board to Board (B2B). Ethernet components ETH1 and ETH2 are connected to B2B connector J3JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.

MIO Pins

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UART

There is no fixed mapping for PS7 UART, if needed it can be mapped to free pins from MIO1 Bank or via EMIO to PL pins.

Recommended mapping for primary (console, debug) UART are MIO52, MIO53.

On-board Peripherals

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Notes :

CAN PHY

CAN pins connections to Board to Board (B2B).

JTAG Interface

JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.

MIO Pins

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Scroll Title
anchor Table_OBP_MIOs title On board peripheralsMIOs pins
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default stylesortByColumn widths sortByColumn 1 sortEnabled false cellHighlighting true
Chip/Interface	Product	Notes
SPI Flash	U13	16 MByte Flash
EEPROM	U11	64 Kbit EEPROM
RTC	U7	Real Time Clock
DDR3 SDRAM	U1	Volatile Memory
Ethernet	U3, U10	CAN Transceiver	U16
User LED	D4	Green LED

Quad SPI Flash Memory

On-board QSPI flash memory is used to store initial FPGA configuration. Datasheet is provided in Texas Instruments. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

Quad SPI Flash (U7) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500.

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On-board Peripherals

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RTC 

The RTC has an I²C Bus (2-wire SerialInterface) and offers temperature compensated time. The STC-Smart Temperature Compensation is calibrated in the factory and leads to a very high time-accuracy.

RTC intruppt is connected to MIO0 connected to Bank 500, pin G6.

EEPROM

Quad SPI Flash Memory

On-board QSPI flash memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency.

Quad SPI Flash (U7) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500The Microchip Technology Inc. 24xx64 is a 64 Kbit Electrically Erasable PROM. The device is organized as a single block of 8K x 8-bit memory with a 2-wire serial interface. Lowvoltage design permits operation down to 1.7V, with standby and active currents of only 1 μA and 3 mA, respectively. It has been developed for advanced, lowpower applications such as personal communications or data acquisition. The 24xx64 also has a page write capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for up to 512 Kbits address space.

LEDs

RTC 

The RTC has an I²C Bus (2-wire SerialInterface) and offers temperature compensated time. The STC-Smart Temperature Compensation is calibrated in the factory and leads to a very high time-accuracy.

RTC interrupt is connected to MIO0 connected to Bank 500 through pin G6.

DDR3 SDRAM

The TE0728 SoM has two 512 MByte volatile DDR3 SDRAM IC for storing user application code and data.

 Configuration of the DDR3 memory controller in the FPGA should be done using the MIG tool in the Xilinx Vivado Design Suite IP catalog.

Ethernet

There are two 100 MBit Extreme Temperature Ethernet provided by Texas Instrument on the board. Datasheet is provided TI website. Both PHY's are connected with all I/O Pins to FPGA Bank 34 (VCCIO = 3.3V). PHY Clock 25 MHz source is provided from MEMS Oscillator. There is no sharing of signals for the two PHY's.

PUDC pin is connected with pull-up to 3.3V those pre-configuration pull-ups are disabled by default. Strapping resistor exist to change the PUDC mode.

EEPROM

The Microchip Technology Inc. 24xx64 is a 64 Kbit Electrically Erasable PROM. The device is organized as a single block of 8K x 8-bit memory with a 2-wire serial interface. The 24xx64 also has a page write capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for up to 512 Kbits address space.

LEDs

CAN Transceiver

DDR3 SDRAM

The TE0728 SoM has a volatile DDR3 SDRAM, 256Mx16bit (512MB), IC for storing user application code and data. Size of DDR3 can be varied in different assembly versions.

• Part number: NT5CB256M16CP-DIH
• Supply voltage: 1.5V
• Organization: 256M x 16 bits

DDR3 SDRAM can be varied on demand for other assembly options. DDR3 can have density of maximum 512MB due to available addressing. The maximum possible speed for DDR3 SDRAM is 1066 Mb/s.

Ethernet

There are two 100 MBit Extreme Temperature Ethernet provided by Texas Instrumen on the board. Datasheet is provided at TI website. Both PHY's are connected with all I/O Pins to FPGA Bank 34 (VCCIO = 3.3V). PHY Clock 25 MHz sources is provided from MEMS Oscillator. There is no sharing of signals for the two PHY's.

PUDC pin is connected with pull-up to 3.3V those pre-configuration pull-ups are disabled by default. Strapping resistor exist to change the PUDC mode.Controller Area Network (CAN) transceivers are designed for use with the Texas Instruments TMS320Lx240x 3.3-V DSPs with CAN controllers. The datasheet is available in TI website. Each CAN transceiver is designed to provide differential transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1 Mbps. 

Low Dropout Linear Regulator

The low-dropout (LDO)  provides an easy-to-use robust power management  solution for a wide variety of applications. User programmable soft-start minimizes stress on the input power source by reducing capacitive inrush current on start-up. The soft-start is monotonic and well- suited for powering many different types of Monitoring or Provides a Sequencing Signal processors and ASICs. The enable input and power for Other Supplies good output allow easy sequencing with external regulators. This complete flexibility permits the user to configure a solution that meets the sequencing Voltage Startup requirements of FPGAs, DSPs, and other applications with special start-up requirements.

Clock Sources

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CAN Transceiver

Controller Area Network (CAN) transceivers are designed for use with the Texas Instruments TMS320Lx240x 3.3-V DSPs with CAN controllers. The datasheet is available in TI website. Each CAN transceiver is designed to provide differential transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1 Mbps. 

Oscillators

Power and Power-On Sequence

Power Supply

Power supply with minimum current capability of 2.5A for system startup is recommended.

Power Consumption

* TBD - To Be Determined

Power Distribution Dependencies

Power on Sequence

The TE07028 SoM meets the recommended criteria to power up the Xilinx Zynq properly by keeping a specific sequence of enabling the on-board DC-DC converters and regulators dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages. When

Power and Power-On Sequence

Power Supply

Power supply with minimum current capability of 3.5 A for system startup is recommended.

Power Consumption

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* TBD - To Be Determined

Power on Sequence

The PS and PL power supplies are fully independent. PS power supplies (VCCPINT, VCCPAUX, VCCPLL, VCCO_DDR, VCCO_MIO0, and VCCO_MIO1) can be powered before or after any PL power supplies. The PS and PL power regions are isolated to prevent damage. The recommended power-on sequence is VCCPINT, then VCCPAUX and VCCPLL together, then the PS VCCO supplies (VCCO_MIO0, VCCO_MIO1, and VCCO_DDR) to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The PS_POR_B input is required to be asserted to GND during the power-on sequence until VCCPINT, VCCPAUX and VCCO_MIO0 have reached minimum operating levels to ensure PS eFUSE integrity. 

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Power Distribution Dependencies

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The PS and PL power supplies are fully independent. PS power supplies (VCCPINT, VCCPAUX, VCCPLL, VCCO_DDR, VCCO_MIO0, and VCCO_MIO1) can be powered before or after any PL power supplies. The PS and PL power regions are isolated to prevent damage. The recommended power-on sequence is VCCPINT, then VCCPAUX and VCCPLL together, then the PS VCCO supplies (VCCO_MIO0, VCCO_MIO1, and VCCO_DDR) to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The PS_POR_B input is required to be asserted to GND during the power-on sequence until VCCPINT, VCCPAUX and VCCO_MIO0 have reached minimum operating levels to ensure PS eFUSE integrity.

Voltage Monitor Circuit

The microprocessor supervisory circuits monitor system voltages from 0.4 V to 5 V, asserting an open-drain RESET signal when the SENSE voltage drops below a preset threshold or when the manual reset (MR) pin drops to a logic low. The RESET output remains low for the user adjustable delay time after the SENSE voltage and MR return above their thresholds. Datasheet is available in Texas Instruments website.

When the U8 and U9 generates PWRGD signal, it turns on the U4 which generates PWRGD_3.3V, it turns on the U6 and it generates PWROK signal which is connected to MR. Whenever the supply voltage for U12 drops down below the threshold it resets the system. Actually it resets the system when all regulators are working.

Power Rails

Bank Voltages

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Bank          

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Voltage

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VCCO_MIO1_500

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Supplied by the carrier board. JM2,JM3

Board to Board Connectors

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Voltage Monitor Circuit

The microprocessor supervisory circuits monitor system voltages asserting an open-drain RESET signal when the SENSE voltage drops below a preset threshold or when the manual reset (MR) pin drops to a logic low. The RESET output remains low for the user adjustable delay time after the SENSE voltage and MR return above their thresholds. Datasheet is available in Texas Instruments website.

Power Rails

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6 x 6 modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.

• 3 x REF-189018-01 (compatible to SEM-140-02-03.0-H-D-A), (80 pins, "40" per row)

  Operating Temperature:-55°C ~ 125°C
  Current Rating: 2.6A per ContactNumber of Positions: 80
  Number of Rows: 2

Technical Specifications

Absolute Maximum Ratings

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Scroll Title
anchor Table_TSPWR_AMR_PSPR title PS absolute maximum ratingsModule power rails.
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true
Symbols	Description	Min	Max	Unit
VCCPINT	PS internal logic supply voltage	-0.5	1.1	V
VCCPAUX	PS auxiliary supply voltage	-0.5	2.0	V
VCCPLL	PS PLL supply	-0.5	2.0	V
VCCO_DDR	PS DDR I/O supply voltage	-0.5	2.0	V
VPREF	PS input reference voltage	-0.5	2.0	V
VCCO_MIO0	PS MIO I/O supply voltage for HR I/O banks	-0.5	3.6	V
VCCO_MIO1	PS MIO I/O supply voltage for HR I/O banks	1.71	3.45	V

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Power Signal B2B JM1 Pin B2B JM2 Pin B2B JM3 Pin Direction Notes VIN 1,3 - - Input Supply voltage from carrier board. VCCO_13 39 - - Input VBATT - 1 - Output RTC Supply voltage 3.3V 19 4 25,57 Output Internal 3.3V voltage level. VMIO - 2 Input Variable and supplied by carrier 1.8V - 5 - Output Internal 1.8V voltage level.

Bank Voltages

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Board to Board Connectors

Technical Specifications

Absolute Maximum Ratings

Temprature range: -40°C to +85°C.

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Recommended Operating Conditionse

Physical Dimensions

• Module size: 60 mm × 60 mm.  Please download the assembly diagram for exact numbers.

• Mating height with standard connectors: 7 mm.

• PCB thickness: 1.6 mm.

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Currently

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Offered Variants 

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Revision History

Hardware Revision History

Product changes can be seen in PCN page.

Hardware revision number is printed on the PCB board next to the module model number separated by the dash.

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