Page History
Template Revision 2.7 - on construction
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Important General Note:
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Export PDF to download, if vivado revision is changed!
Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
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Figure template (note: inner scroll ignore/only only with drawIO object):
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Create DrawIO object here: Attention if you copy from other page, use |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Table template:
- Layout macro can be use for landscape of large tables
- Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)
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Table of contents
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Overview
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Notes :
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Design Example with minimum PS Setup (DDR, QSPI, UART0) only for custom boards or easier debug via SDK.
Refer to http://trenz.org/te0803-info for the current online version of this manual and other available documentation.
Key Features
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Revision History
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| title | Design Revision History |
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- new assembly variants
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- script update
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- 2019.2 update
- Vitis support
- FSBL SI programming procedure update
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- custom FSBL
- new assembly variants
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- new assembly variant
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- new assembly variant
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- additional notes for FSBL generated with Win SDK
- changed *.bif
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- new assembly variant
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- bugfix TE0803-01-04EG boart part file
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- new assembly variant
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- new assembly variant
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- rework Board Part Files
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- Update Board Part CSV File with new Flash assembly variants
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2017-11-14
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- Initial release
Release Notes and Know Issues
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Requirements
Software
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Hardware
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
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Note: Design contains also Board Part Files for TE0803+TEBF0808 configuration, this boart part files are not used for this reference design.
Design supports following carriers:
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| title | Hardware Carrier |
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Additional HW Requirements:
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| title | Additional Hardware |
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Content
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Notes :
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For general structure and of the reference design, see Project Delivery - Xilinx devices
Design Sources
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| title | Design sources |
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Additional Sources
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| title | Additional design sources |
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Prebuilt
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Notes :
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| title | Prebuilt files |
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File
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File-Extension
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Description
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Debian SD-Image
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*.img
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Debian Image for SD-Card
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MCS-File
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*.mcs
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Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
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MMI-File
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*.mmi
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File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
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SREC-File
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*.srec
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Converted Software Application for MicroBlaze Processor Systems
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File
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File-Extension
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Description
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Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
Design Flow
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
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Note:
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Block Design
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PS Interfaces
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Design specific constrain
Not needed.
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Application
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FPGA Example
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zynq_fsbl_flash
TE modified 2019.2 FSBL
General:
- Modified Files: main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
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- Si5338 Configuration
- ETH+OTG Reset over MIO
zynqmp_fsbl_flash
TE modified 2019.2 FSBL
General:
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TE modified 2019.2 FSBL
General:
- Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
hello_te0803
Hello TE0803 is a Xilinx Hello World example as endless loop instead of one console output.
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Authors
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Overview
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