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Trenz Electronic TE0728 is an automotive-grade FPGA module integrating a Xilinx Automotive an Automotive Xilinx  Zynq-7020 7 FPGA, two 100 Mbit Ethernet transceivers (PHY) , 512 MByte DDR3L SDRAM, 16 MByte DDR3 SDRAM, QSPI Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. 

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• Xilinx
XA7Z020
• XC7Z020-1CLG484Q (Automotive)
• Rugged for shock and high vibration
• Dimensions: 6 x 6 cm
Temperature range: Automotive
• [XA7Z014S is available on other assembly options]
  • Package: CL/CLG484
  • Speed Grade: -1
  • Temperature Grade: Expanded (-40 to +128 °C)
• • 
    
• Dual-Core ARM Cortex-A9 MPCore
  
• 2 x 100 MBit Ethernet transceiver (PHY)
• 512 MByte DDR3L SDRAM, 16-bit-wide 
• DDR3 SDRAM, up to 512MB, up to 1066 Mb/s, connected to PS  [different size is available on other assembly options]
16 MByte
• QSPI Flash memory (with XiP support)
• Plug-on module with 3 x 80-pin Samtec Micro Tiger Eye(TM) high-speed connectors
76 single ended I/O, 24 LVDS pairs (48 I/O) and 42 MIO available on board-to-board connectors
• [different size is available on other assembly options]
• Programmable SIT8918A , PS clock generator
• 2 Kbit serial EEPROM
• Three user LEDs
• CAN transceiver (PHY)
12 V power supply with watchdog
• On-board high-efficiency DC-DC converters
• System management and power sequencing
• eFUSE bit-stream encryption
• AES bit-stream encryption
• Temperature compensated RTC (real-time clock)
• Three user LEDs
• Evenly-spread supply pins for good signal integrity

Depending on the customer design, additional cooling might be required.

Block Diagram

• 2 x 100 MBit Ethernet transceiver (PHY)
• Board to Board (B2B)
  • Plug-on module with 3 x 80-pin Samtec Micro Tiger Eye(TM) high-speed connectors
• I/O Interface
  • 42x MIO
  • 200x HR
  • 128x PS IO
  • 0x GTP Transceiver
  • 0x GTX Transceiver

• Power Supply
  • 12 V power supply with watchdog
• Others:
  • Dimensions: 6 x 6 cm
  • Rugged for shock and high vibration
  • On-board high-efficiency DC-DC converters
  • System management and power sequencing
  • eFUSE bit-stream encryption
  • AES bit-stream encryption
  • Evenly-spread supply pins for good signal integrity
    
    

Block Diagram

Main Components

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1. 512 MByte DDR3 SDRAM, U1
2. Xilinx Automotive XA7Z020-1CLG484Q ,U2
3. 100 MBit Ethernet transceiver, U3
4. Standard Clock Oscillators @ 25MHz, U5
5. 1.5 A Low Dropout Linear Regulator, U6
6. Real Time Clock, Micro Crystal @32.768 MHz, U7
8. 100 MBit Ethernet transceiver, U10
9. User LED Green, D4
10. Real Time Clock, U7
11. Standard Clock Oscillators, U5100 MBit Ethernet transceiver, U10
12. 64 Kbit I2C EEPROM, U11
13. Low-Quiescent-Current Proggrammable Delay Supervisory Circuit, U12
14. CAN Tranceiver, U16
15. QSPI NOR 16 MByte QSPI Nor Flash memory, U13
16. Standard Clock Oscillators @ 50MHzOscillators, U14
17. Low-Quiescent-Current Priggrammable Programmable Delay Supervisory Circuit, U15
18. CAN Tranceiver, U16Low-Quiescent-Current Programmable Delay Supervisory Circuit, U12
19. B2B connector , JM2
20. B2B connector , JM3
21. B2B connector  Samtec Micro Tiger Eye Connector  SEM-140-02-03, JM1
    User LED Greenconnector , JM1

FPGA (U2), DDR3 SDRAM (U1) and QSPI (U13) can be  varied on other assembly option, for more information contact us. 

Initial Delivery State

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Configuration Signals

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Zynq-7020SoC  includes a reset that is driven by the reset system. Hardware resets are driven by the power-on reset signal (Reset) connected to carrier and the system reset signal (PS_SRST_B)  connected to VMIO, it means after power on the PS will be reset.