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Table of Contents
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Overview
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Refer to https://wiki.trenz-electronic.de/display/
...
PD/TE0723+TRM for downloadable version of this manual and additional technical documentation of the product.
...


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The Trenz Electronic TE0723 is a Arduino compatible FPGA module Zynq board with numerous on-board peripherals based on the Xilinx Zynq XC7Z010 SoC.
...
Figure 1: TE0723 block diagram.
Main Components
      
Figure 2: Main components of the TE0723 module.
  1. Xilinx Zynq XC7Z010 SoC, U1
  2. 4 Gbit DDR3L 256M x 16 SDRAM, U2
  3. 16 MByte QSPI quad SPI Flash memory, U5
  4. High-speed CMOS logic analog multiplexer/demultiplexer, U10
  5. 1 MHz low-power operational amplifier, U11
  6. Dual high-speed USB to multipurpose UART/FIFO, U3
  7. 0.5A dual-channel current-limited power switch, U21
  8. Low-power programmable oscillator @ 12.000000 MHz, U7
  9. 2-Kbit Microwire compatible serial EEPROM, U6
  10. 10-pin header, J1
  11. 8-pin header, J2
  12. 10-pin header, J3
  13. Analog input header, J4
  14. 2 x 4-pin header, J5
  15. PMod 2x6 interface header, J6
  16. USB host mode jumper, J7
  17. Micro USB 2.0 Type-B receptacle, J8
  18. Micro USB 2.0 Type-B receptacle, J9
  19. Micro SD card connector with detect signal, J10
  20. Analog input select jumper, J11
  21. 5V supply power input, J12
  22. Reset switch, S1
  23. Red LED, D2
  24. Green LED, D6
  25. Green LED, D7
  26. Ultra-low supply-current voltage monitor, U23
  27. 1A PowerSoC DC-DC converter (3.3 V), U20
  28. 1A PowerSoC DC-DC converter (1.8 V, U19
  29. 1A PowerSoC DC-DC converter (1.35 V), U16
  30. Hi-speed USB 2.0 ULPI transceiver, U18
  31. Low-power programmable oscillator @ 52.000000 MHz, U14
  32. 1A PowerSoC DC-DC converter (1.0 V), U17
  33. JTAG interface testpoints, TP1-TP4
Initial Delivery State
Storage device name
IC
Content
Notes
Quad SPI Flash
U5
Empty
 -
Configuration EEPROMU6Pre-ProgrammedXilinx License
Table 1: Initial delivery state of programmable devices on the module.
Boot Process
The 7 boot mode strapping pins on the TE0723 module are set to boot the system from quad SPI Flash only. For additional information refer to the TE0723 schematic and Xilinx UG585 Zynq-7000 All Programmable SoC Technical Reference Manual (MIO2 ... MIO8) of the Xiliny Zynq Z-7010 device are hardware programmed on the board. They are evaluated by the Zynq device soon after the 'POR_B'.signal is deasserted to begin the boot process (see section "Boot Mode Pin Settings" of Xilinx manual UG585).
The TE0723 Zynq board is hardware programmed to boot initially from the on-board QSPI Flash memory U5. The JTAG interface of the module is provided for storing the data to the QSPI Flash memory through the Zynq device.
Signals, Interfaces and Pins
I/O Signals on Connectors
List of Overview of the Zynq SoC PS/PL banks I/O signals between PS/PL banks and connected to the external connectors:
BankTypeConnectorI/O Signal CountVoltageNotes
34HRJ1683.33VSignal Schematic names: 'SCL', 'SDA', 'D8' ... 'D13'.D8 .. 13, SDA, SCL
34HRJ283.33VSignal Schematic names: 'RXD', 'TXD', 'D2' ... 'D7'.D2 .. 7, RXD, TXD
34HRJ683.33VSignal Schematic names: 'PIO01' ... 'PIO08'.
34HRJ1113.3VSignal Schematic name: 'AIN_FPGA'.
35HRJ4763.33V
Signal Schematic names: 'AIN0' ... 5'AIN5', usable as differential analog inputs or regular digital I/O's.
35HRJ513.33VConnector dedicated to ESP8266 module.ESP_GPIO2
500MIOJ10673.3SDCARD3VSDIO interface to SD Card socket.
 501501MIOJ543.3ESP_RXD, ESP_TXD, ESP_GPIO0, MOD_RST
Table x: .
JTAG Interface
JTAG access to the Xilinx Zynq XC7Z010 SoC is provided through FTDI USB/UART FIFO bridge connected to the J9 Micro USB connector.
Default PS MIO Mapping
...
I2C Interface
I2C interface pins from the Zynq SoC PL bank 34 are connected to the connector J1. There are no on-board I2C slave devices.
...
Table x: .
On-board Peripherals
DDR Memory
TE0723 module has up to 512-MBytes of DDR3L SDRAM arranged into 32-bit wide memory bus providing total of 1 GBytes of on-board RAM. Different memory sizes are available optionally.
Quad SPI Flash Memory
On-board quad SPI Flash memory S25FL127S (U5) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application storage. All four SPI data lines are connected to the Zynq SoC's PS, allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the bus width and clock frequency used.
Dual High-speed USB to Multipurpose UART/FIFO
FT2232H...
High-speed USB ULPI PHY
Hi-speed USB ULPI PHY (U18) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq SoC's PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 3.3V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U14).
High-Speed Analog Multiplexer
Digitally controlled analog switch TI CD74HC4051...
Low-power Operational Amplifier
The Microchip Technology Inc. MCP6001...
Oscillators
The module has following reference clock signals provided by on-board oscillators:
...
PS_CLK
...
52.000000 MHz
...
U1
...
PS_CLK_500
...
Zynq SoC PS subsystem main clock.
...
OTG-RCLK
...
52.000000 MHz
...
REFCLK
...
USB3320C PHY reference clock.
...
FT2232H oscillator input.
Table x: Reference clock signals.
On-board LEDs
There are three LEDs on-board TE0723:
...
Green
...
Green
...
3.3V
...
3VConnector dedicated to ESP8266 module.
Table 2: Overview of the Zynq SoC's PS/PL banks I/O signals
Zynq SoC I/O Banks
BankTypeVCCIOI/O Signal CountAvailable on ConnectorsNotes
34HR3.3V44258 user I/O's on Pmod connector J6, female pin header J1 and J2 each. 1 I/O on pin header J11.
35HR3.3V876 user I/O's on female pin header J4, 1 user I/O on female pin header J5.
500PS MIO3.3V15-6 MIO pins used for QSPI flash memory interface, 7 MIO pins used for SD Card interface, 1 MIO pin connected to red LED D2,
1 MIO pin as reset pin routed to USB PHY U18, 'POR_B'-signal is connected to voltage monitor circuit 23.
501PS MIO3.3V16412 MIO pins used for USB ULPI interface, 4 MIO pins used for ESP8266 interface header J5.
0Config3.3V4-4 I/O's are dedicated to JTAG interface.
Table 3: General overview of Zynq SoC PL/PS I/O bank
USB2 to JTAG/UART Adapter
The TE0723 board is equipped with the FTDI FT2232H USB2 to JTAG/UART adapter controller connected to micro-USB2 connector J9 to provide JTAG and UART access to the Xilinx Zynq XC7Z010 SoC. There is also a 256-byte configuration EEPROM U6 wired to the FT2232H chip via Microwire bus which holds pre-programmed license code to support Xilinx programming tools.

 Warning
Do not access the FT2232H EEPROM using FTDI programming tools, doing so will erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license the on-board JTAG will not be accessible any more with any Xilinx tools. Software tools from FTDI website do not warn or ask for confirmation before erasing user EEPROM content.

Channel A of the FTDI IC is configured as JTAG interface (MPSSE) connected to the JTAG interface of the Zynq SoC on configuration bank 0:
Zynq SoC U1
Signal Schematic Name
FT2232H IC U3 Pin
Pin G9TCK12
Pin L7TDI13
Pin L8TDO14
Pin L9TMS15
Table 4: JTAG interface signals

14 additional bus lines of Channel B of the FTDI IC are routed to Zynq SoC PL bank 34 and are available to the user. The FTDI chip which converts signals from USB2 to a variety of standard serial and parallel interfaces like UART and user GPIO's in FIFO mode. Refer to the FTDI data sheet to get information about the capacity of the FT2232H IC.
Zynq SoC U1
Signal Schematic Name
FT2232H IC U3 Pin
Bank 34, pin H13BDBUS032
Bank 34, pin H14BDBUS133
Bank 34, pin J15BDBUS234
Bank 34, pin J14BDBUS335
Bank 34, pin K15BDBUS437
Bank 34, pin L15BDBUS538
Bank 34, pin L14BDBUS639
Bank 34, pin M15BDBUS740
Bank 34, pin M14BCBUS042
Bank 34, pin N14BCBUS146
Bank 34, pin P15BCBUS247
Bank 34, pin N13BCBUS348
Bank 34, pin R15BCBUS449
Bank 34, pin P14BCBUS753
Table 5: FTDI FT2232H bus line signals
Quad SPI Interface
Quad SPI Flash memory (U5) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6.
Zynq SoC U1 PinSignal Schematic NameFlash memory U5 Pin
Bank 500, pin MIO1SPI0_CS1
Bank 500, pin MIO2SPI0_DQ0/MIO25
Bank 500, pin MIO3SPI0_DQ1/MIO32
Bank 500, pin MIO4SPI0_DQ2/MIO43
Bank 500, pin MIO5SPI0_DQ3/MIO57
Bank 500, pin MIO6SPI0_SCK6
Table 6: Quad SPI interface signals
SD Card Interface
TE0723 module has on-board 3.3V SD Card socket (J10) with card detect switch wired to the SoC PS MIO bank 500.
Zynq SoC U1 PinSignal Schematic NameConnected to
Bank 500, pin MIO0Card detect switchJ10-9
Bank 500, pin MIO10DAT0J10-7
Bank 500, pin MIO11CMDJ10-3
Bank 500, pin MIO12CLKJ10-5
Bank 500, pin MIO13DAT1J10-8
Bank 500, pin MIO14DAT3J10-1
Bank 500, pin MIO15CD/DAT3J10-2
Table 7: SD Card socket signals
USB2 Interface
High-speed USB2 interface is provided by USB3320 from Microchip (U18). The USB2 PHY is connected via ULPI interface to the Zynq SoC PS USB0, bank 501 and pins MIO28 ... MIO39.
The USB2 interface is accessible through the micro-USB2 B connector J8 and enables device, host or OTG modes. For host mode, the on-board USB2 interface provides the USB-VBUS supply voltage with nominal 4.75V to 5.25V on micro-USB2 connector pin J8-1. To configure host mode on this interface, the board has to be supplied with 5V through pin header J12 or with the USB-VBUS supply voltage of micro-USB2 connector J9, which is connected to the FTDI FT2232H chip.
The USB-VBUS supply voltage enabling the host mode on USB2 interface J8 is switched by the on-board power distribution switch AP2152SG-13 from Diodes Incorporated. The voltage is switched on with the signal 'VBUS_V_EN' which is controlled by the USB2 PHY U18. If the output load exceeds the current-limit threshold, the AP2152SG-13 limits the output current and pulls the over-current low-active logic output signal 'USB_OC' low, which is routed to the Zynq PL bank 35, pin F15.
 An extra 100µF decoupling capacitor (in addition to 4.7µF) can be activated on-board to stabilize the USB-VBUS host supply voltage furthermore. This can be done by fitting and closing jumper J7, fitting 0-Ohm-resistor R53 or MOSFET transistor Q1. The transistor Q1 allows to enable and disable this 100µF extra capacitor  by the signal 'HOST_MODE_EN' routed to the Zynq PL bank 34, pin L13.
Following table shows the signal assignment of the USB PHY U18 with the Zynq PS MIO bank 501:
Zynq SoC U1 PinSignal Schematic NameUSB2 PHY U18 Pin
Bank 501, pin MIO28OTG-DATA47
Bank 501, pin MIO29OTG-DIR31
Bank 501, pin MIO30OTG-STP29
Bank 501, pin MIO31OTG-NXT2
Bank 501, pin MIO32OTG-DATA03
Bank 501, pin MIO33OTG-DATA14
Bank 501, pin MIO34OTG-DATA25
Bank 501, pin MIO35OTG-DATA36
Bank 501, pin MIO36OTG-CLK1
Bank 501, pin MIO37OTG-DATA59
Bank 501, pin MIO38OTG-DATA610
Bank 501, pin MIO39OTG-DATA713
Table 8: USB interface signals
ESP8266 Wi-Fi Interface
Interface for the ESP8266 Wi-Fi module is provided through connector J5.
Zynq SoC U1 PinSignal Schematic NameConnected to
Bank 501, pin MIO48ESP_TXDJ5-2
Bank 501, pin MIO49ESP_RXDJ5-7
Bank 501, pin MIO52MOD_RSTJ5-6
Bank 501, pin MIO53ESP_GPIO0J5-3
Bank 35, pin G15ESP_GPIO2J5-5
Table 9: ESP8266 Wi-Fi module interface
I²C Interface
I2C interface pins SCL and SDA from the Zynq SoC PL bank 34 are connected to the connector J1. There are no on-board I²C slave devices. The two I²C bus lines 'SDA' and 'SCL' can be optionally pulled up to 3.3V on-board by fitting the 0-Ohm-resistors R35 ('SDA') and R42 ('SCL').
Zynq SoC U1 PinSignal Schematic NameConnected to
R13SDAJ1-9
P13SCLJ1-10
Table 10: Zynq SoC I2C interface
Analog Input Interface
The TE0723 board provides up to 7 muxed analog input pins to the XADC unit of the Zynq device. 6 pins are exposed to female pin header J4, 1 to male pin header J11. The pins are muxed by the TI High Speed CMOS 8-Channel Analog Multiplexer CD74HC4051 (U10). There is between the analog output of the multiplexer IC and the differential analog input of the Zynq device an operational amplifier (U11) configured in voltage-follower circuit transforming the single analog output signal of the multiplexer IC to the differential analog signal, which is connected to the differential XADC input pins of the Zynq device, pin G7, H7.
The analog input channels can be selected by the pins 'AMUX_SO', 'AMUX_S1' and 'AMUX_S2', which are connected to the Zynq PL bank 34, pin G12, H12, G11: 
Analog Input Channel
[AMUX_S2:AMUX_S1:AMUX_S0]
Connector pinNote
AIN0000J4-1-
AIN1001J4-2-
AIN2010J4-3-
AIN3011J4-4-
AIN4100J4-5-
AIN5101J4-6-
AIN6110J11-1-
VIN_SENSE111-half divided 5V input supply voltage
Table 11: Selecting multiplexer analog input channels

Another feature of the analog interface capacities of the XADC units of the Zynq device are the Auxiliary Analog Inputs of the Zynq device's PL bank 35 (see Xilinx document UG480, section 'Auxiliary Analog Inputs'). With 6 pins of female pin header J4 3 analog differential pairs can be created:
Analog differential Input Pin Pair
Connector pin
Signal Schematic NameNote
IO_L1P_T0_AD0P_35, pin F12 
IO_L1N_T0_AD0N_35, pin E13		J4-3
J4-1		AIN2
AIN0		I/O's also usable in digital mode
IO_L2P_T0_AD8P_35, pin F11
IO_L2N_T0_AD8N_35, pin E12
J4-4
J4-2		AIN3
AIN1		I/O's also usable in digital mode
IO_L3P_T0_DQS_AD1P_35, pin F13
IO_L3N_T0_DQS_AD1N_35, pin F14
J4-6
J4-5		AIN5
AIN4		I/O's also usable in digital mode
Table 12: Auxiliary Analog Inputs of the Zynq device
Note: These 6 auxiliary analog inputs pins are analog inputs are shared with PL bank pins and can be used as regular digital I/O's.
On-board Peripherals
DDR Memory
TE0723 module has up to 512-MBytes of DDR3L SDRAM arranged into 32-bit wide memory bus providing total of 1 GBytes of on-board RAM. Different memory sizes are available optionally.
Quad SPI Flash Memory
On-board quad SPI Flash memory S25FL127S (U5) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application storage. All four SPI data lines are connected to the Zynq SoC's PS, allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the bus width and clock frequency used.
FTDI FT2232H IC
The FTDI chip U3 converts signals from USB2.0 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip.
FTDI FT2232H chip is used in MPPSE mode for JTAG, 14 I/O's of Channel B are routed to PL bank 34 of the Zynq SoC and are usable for example as UART interface.
The configuration of FTDI FT2232H chip is stored with Xllinx License on EEPROM U6. Please note the warning in section "USB2 to JTAG/UART Adapter" to not overwrite or delete the Xilinx License on the EEPROM U6.
Microwire Serial EEPROM
There is a 2-Kbit (128 x 16-bit organization) Microwire compatible serial EEPROM 93AA56B (U6) connected to the FTDI FT2232H dual high-speed USB2 to multipurpose UART/FIFO (U3). This external EEPROM allows each of the FTDI FT2232H chip’s channels to be independently configured as a serial UART (RS232 mode), parallel FIFO (245) mode or fast serial (optical isolation). The external EEPROM can also be used to customize the USB VID, PID, serial number, product description strings and power descriptor value of the FT2232H for OEM applications. Other parameters controlled by the EEPROM include remote wake up, soft pull down on power-off and I/O pin drive strength.
High-speed USB2 ULPI PHY
Hi-speed USB2 ULPI PHY (U18) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq SoC's PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 3.3V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U14).
Oscillators
The module has following reference clock signals provided by on-board oscillators:
SourceSignalFrequencyDestinationPin NameNotes
U14
PS_CLK
52.000000 MHz
U1
PS_CLK_500
Zynq SoC PS subsystem main clock.
U14
OTG-RCLK
52.000000 MHz
U18
REFCLK
USB3320C PHY reference clock.
U7OSCI12.000000 MHzU3OSCI
FT2232H oscillator input.
Table 13: Reference clock signals
On-board LEDs
There are three LEDs on-board TE0723:
LEDColorConnected toDescription and Notes
D2RedZynq PS bank 500, pin MIO9User LED.
D6
Green
Zynq PL bank 34, pin G14User LED.
D7
Green
3.3V
Indicating 3.3V voltage level.
Table 14: On-board LEDs
Push Buttons
The TE0723 board is equipped with one push buttons S1:
ButtonSignal Schematic NameConnected toNotes
S1NRSTVoltage Monitor Circuit, U23Triggers system reset.
Table 15: Push buttons of the module
Power and Power-On Sequence
To power-up a module, power supply with minimum current capability of 1A is recommended.
Power Supply
5V power can be supplied by the external power supply through connector J12 or via USB connection to the host system through USB connector J8 or J9. Minimum current capability of 1A for external power supply is recommended.
Following diagram shows the dependencies of the power supply:
Image Added
Figure 3: Module power supply dependencies
Power Consumption
Power consumption is to be determined by the user and depends on SoC's FPGA design and connected hardware.
Board VariantFPGADesignTypical Power, 25°C ambient
TE0723-02XC7Z010-1CLG225CNot configuredTBD*
TE0723-03MXC7Z010-1CLG225CNot configuredTBD*
TE0723-03-07S-1CXC7Z007S-1CLG225CNot configuredTBD*
Table 16: Module power consumption
Power-On Sequence
There is no specific power-on sequence, system will power-up automatically when 5V is present either through J8, J9 or J12.
Voltage Monitor Circuit
The voltages 1.0V (core voltage) and 3.3V are monitored by the voltage monitor circuit U23, which generates the POR_B reset signal at power-on. A manual reset is also possible by driving the connector pin J3-3 ('EXT_RST') to GND (leave this pin unconnected or connect to VDD (3.3V) when unused) or press switch button S1, which is assigned to the signal 'NRST'.
Image Added
Figure 4: Voltage monitor circuit
Power Rails
The voltage direction of the power rails is directed at on-board connectors' view:

Main Power Pins DesignatorVCC / VCCIODirectionPinsNotes
J125VIn
1
5V power supply pin header.
J33.3VOut2, 4On-board 3.3V voltage level available.
5VIn / Out5On-board 5.0V voltage level available or supply pin.
Table 17: Main power pin header description

I/O pin headerVCC / VCCIODirectionPinsNotes
J53.3VOut
4, 8
I/O header VCCIO.
J63.3VOut6, 12I/O header VCCIO.
Table 18: Power pin description of I/O pin header  

Peripheral Socket DesignatorVCC / VCCIODirectionPinsNotes
J8 / J9USB-VBUSIn / Out1Direction depends on USB2 mode.
J103.3VOut4MikroSD Card socket VDD.
Table 19: Power pin description of peripheral connector
Bank Voltages
Bank
Bank I/O Voltage VCCO
Voltage Range
0 (config)3.3Vfixed
500 (MIO)3.3Vfixed
501 (MIO)3.3Vfixed
34 (HR)3.3Vfixed
35 (HR)3.3Vfixed
Table 20: Board bank voltages
Variants Currently in Production
 Board VariantXilinx Zynq SoC
DDR3L SDRAM
ARM Cores
PL Cells
LUTsFlip-Flops
Block RAM
DSP Slices
Zynq SoC Operating Temp.Temp. Range
TE0723-02XC7Z010-1CLG225C128 MBytesDual-core28K17,6K35,2K2.1 MBytes800°C to +85°CCommercial
TE0723-03MXC7Z010-1CLG225C512 MBytesDual-core28K17,6K35,2K2.1 MBytes800°C to +85°CCommercial
TE0723-03-07S-1CXC7Z007S-1CLG225C512 MBytesSingle-core23K14,4K28,8K1.8 MBytes660°C to +85°CCommercial
Table 21: Board variants
Technical Specifications
Absolute Maximum Rating
Parameter
MinMax
Units
Reference Document
5V power supply voltage
4.755.25
V
USB2.0 VBUS voltage specification
HR PL I/O banks input voltage (VCCIO single ended)-0.4VCCO + 0.55VXilinx datasheet DS187 (VCCO 3.3V nominal)
PS MIO I/O banks input voltage (VCCIO single ended)-0.4VCCO + 0.55VXilinx datasheet DS187 (VCCO 3.3V nominal)
Analog Multiplexer IC pins input voltage03.3VVTI CDx4HC405x data sheet
Storage temperature
-40
+85
°C
WL-SMCW SMD LED data sheet
Table 22: Board absolute maximum ratings
Recommended Operating Conditions
ParameterMinMaxUnitsReference Document
5V power supply voltage4.755.25 VUSB2.0 VBUS voltage specification
HR PL I/O banks input voltage (VCCIO single ended)-0.20VCCO + 0.20VXilinx datasheet DS187 (VCCO 3.3V nominal)
PS MIO I/O banks input voltage (VCCIO single ended)-0.20VCCO + 0.20VXilinx datasheet DS187 (VCCO 3.3V nominal)
Analog Multiplexer IC pins input voltage03.3VVTI CDx4HC405x data sheet
Operating Temperature Commercial
0+85°CXilinx datasheet DS190
Table 23: Board recommended operating conditions
 
 Note
Please check Xilinx datasheet DS187 for complete list of absolute maximum and recommended operating ratings for the Zynq-7 device
Table x: On-board LEDs.
Power and Power-On Sequence
Power Supply
Single 5V power supply with minimum current capability of 2A for system startup is recommended.
Power Consumption
TBD - To Be Determined.
Power-On Sequence
There is no specific power-on sequence, system will power-up itself if 5V is present either from J8, J9 or J12.
Variants Currently in Production
...
DDR3L
SDRAM
...
ARM
Cores
...
PL
Cells
...
Block
RAM
...
DSP
Slices
...
Table 8: Module variants.
Technical Specifications
Absolute Maximum Ratings
...
Parameter
...
Units
...
Reference Document
...
VIN supply voltage
...
V
...
Storage temperature
...
-40
...
+85
...
°C
...
Table x: .
Recommended Operating Conditions
...
Table x: .
 
 Note
Assembly variants for higher storage temperature range are available on request.
Physical Dimensions
  • Module size: 68.58 mm × 53.34 mm.  Please download the assembly diagram for exact numbers.
  • PCB thickness: 1.6 mm.
  • Highest part on PCB: approx. 4 mm. Please download the step model for exact numbers.
Please note that two different units are used on the figures below, SI system millimeters (mm) and imperial system thousandths of an inch(mil). To convert mils to millimeters and vice versa use formula 100mil's = 2,54mm.
Image Modified        Image Modified
Figure 3: TE0723 module physical dimensions.
Operating Temperature Ranges
Commercial grade: 0°C to +70°C.
Industrial grade: -40°C to +85°C.
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.5: Board physical dimensions
Revision History
Hardware Revision History
DateRevision
Notes
PCNDocumentation Link
2016-07-1503 
Refer to Changes list in Schematic for further details in changes to REV02
-Click to see PCN.TE0723-03
2015-11-06
02 Second Production Release -TE0723-02
 -
01
 First Production Release - -
Table x24: TE0723 Board hardware revision history.

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.
Figure 6: TE0723 board hardware revision number
Document Change History
Date
Revision
Contributors
Description
 Page info
modified-date
modified-date
dateFormatyyyy-MM-dd


Ali Naseri,
Jan Kumann
Initial document.
  • First TRM release
Table x25: Document change history.
...