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Template Revision 2.12

  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"
  • Carrier: TRM Name usually "TEB Series Name" +TRM
    Example: "TEB0728 TRM"


HTML
<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
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Download PDF version of this document.

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Table of Contents

Table of Contents

Overview

The Trenz Electronic TEBA0714 is a carrier for Trenz Electronic module TE0714 which is an industrial grade module integrated with Xilinx Artix 7.

Refer to http://trenz.org/teba0714-info for the current online version of this manual and other available documentation.

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Notes :

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Important General Note: 'description: Important components and connector or other Features of the module 
→ please sort and indicate assembly options
Key Features'  must be split into 6 main groups:
  • FPGA/Module
    • Package:
    • Speed:
    • Temperature:
  • RAM/Storage
    • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension
  • Module:
    • Trenz TE0714 Modul Carrier
    • Temperature: -40 to +85 °C
  • On Board:
    • 2 x User LEDs (Red, Green)
    • 1 x DONE LED (Red)
  • Interface:
    • 2 x Pin-Header 50 (FPGA Bank I/Os and Power)
    • 2x Samtec 100 Pin LSHM Series Connectors
    • 2 x Pin-Header for FPGA Bank Power
    • 1 x XMOD (TE0790) Pin-Header
    • 1 x Pin-Header 16 Pol. (JTAG, MGT-CLK, Boot Mode, XADC, I/O's)
    • 1 x Pin-Header 10 Pol. (Ein-/ und Ausgänge)
    • 1 x SFP+ Connectors
  • Power:
    • 1 x LDO Regulator
  • Dimension: 30 mm x 40 mm
Block Diagram
...
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idComments
add drawIO object here.
 Note
For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .
  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template:
         Scroll Title
        anchorFigure_anchorname
        titleText

         Scroll Ignore
        Create DrawIO object here: Attention if you copy from other page, objects are only linked.

         Scroll Only
        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed


      • Table template:
        • Layout macro can be use for landscape of large tables

      •  Scroll Title
        anchorTable_tablename
        titleText
         Scroll Table Layout
        orientationportrait
        sortDirectionASC
        repeatTableHeadersdefault
        style
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        sortEnabledfalse
        cellHighlightingtrue
        ExampleComment
        12


    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below
      • <type>_<main section>_<name>
        • type: Figure, Table
        • main section: 
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:
        • "Figure_OV_BD" for Block Diagram
        • "Figure_OV_MC" for Main Components
        • "Table_OV_IDS" for Initial Delivery State
        • "Table_PWR_PC" for Power Consumption
        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages
        • "Table_TS_AMR" for Absolute_Maximum_Ratings
        • "Table_TS_ROC" for Recommended_Operating_Conditions
        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview
        • "Table_RH_HRH" for Hardware_Revision_History
        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>
...
anchorFigure_OV_BD
titleTEBA0714 block diagram
...
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Notes :
  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below
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 Note
For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .
 Scroll Title
anchorFigure_OV_MC
titleTEBA0714 main components
 Scroll Ignore draw.io DiagramborderfalseviewerToolbartruefitWindowfalsediagramDisplayNamelboxtruerevision6diagramNameTEBA0714_OV_MCsimpleViewerfalsewidthlinksautotbstylehiddendiagramWidth641
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  1. 6-pin header J26 for selecting PL-bank I/O voltage
  2. 6-pin header J27 for selecting XMOD/JTAG VCCIO
  3. Samtec Razor Beam™ LSHM-150 B2B connector, JM1
  4. Samtec Razor Beam™ LSHM-150 B2B connector, JM2
  5. XMOD header, JX1
  6. Voltage Regulator, U1
  7. User Red LED D2
  8. User Green LED D1 (red)
  9. SFP+ Connector, J1
  10. Red LED D3, indicating FPGA's 'Programming DONE'-signal
  11. 50-pin header solder pads J20 for access to SoM's PL I/O-banks (LVDS pairs possible)
  12. 16-pin header solder pads J3, JTAG/UART header with ADC and MGT clock input
  13. 10-pin header solder pads J4 for access to SoM's PL I/O-banks (LVDS pairs possible)
  14. 50-pin header solder pads J17 for access to SoM's PL I/O-banks (LVDS pairs possible)
Initial Delivery State
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Notes :
Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.
If there is no components which might have initial data ( possible on carrier) you must keep the table empty
...
-----------------------------------------------------------------------

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Note for Download Link of the Scroll ignore macro: 

 Scroll Ignore
Download PDF version of this document.

 Scroll pdf ignore
Table of Contents
 Table of Contents
Overview
The Trenz Electronic TEBA0714 is a carrier for Trenz Electronic module TE0714 which is an industrial grade module integrated with Xilinx Artix 7. 
Refer to http://trenz.org/teba0714-info for the current online version of this manual and other available documentation.
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Notes :
Key Features
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Note:
 'description: Important components and connector or other Features of the module 
→ please sort and indicate assembly optionsKey Features'  must be split into 6 main groups:
  • FPGA/Module
    • Package:
    • Speed:
    • Temperature:
  • RAM/Storage
    • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension
  • Module:
    • TE0714
  • On Board:
    • 2 x User LEDs (Red, Green)
    • 1 x DONE LED (Red)
  • Interface:
    • 2 x Pin Header 50 Pol. (FPGA Bank I/Os and Power)
    • 2x Samtec 100 Pin LSHM Series Connectors
    • 1 x XMOD JTAG/UART Adapter (TE0790)
    • 1 x Pin Header 16 Pol. (JTAG, MGT-CLK, Boot Mode, XADC, I/O's)
    • 1 x Pin Header 10 Pol. (FPGA Bank I/Os and Power)
    • 1 x SFP+ Connectors
  • Power:
    • 1 x LDO Regulator
    • 3.3V  Nominal Power supply
  • Dimension: 
    • 46 mm × 75 mm
Block Diagram
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add drawIO object here.
 Note
For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


 Scroll Title
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titleTEBA0714 block diagram

 Scroll Ignore
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Image Added

Main Components
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Notes :
  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below

 Note
For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .


 Scroll Title
anchorFigure_OV_MC
titleTEBA0714 main components

 Scroll Ignore
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  1. SMT pin header, J26
  2. SMT pin header, J27
  3. Board to Board  (B2B) Connector, JM1
  4. Board to Board  (B2B) Connectorr, JM2
  5. XMOD header, JX1
  6. Voltage Regulator, U1
  7. User Red LED, D2
  8. User Green LED, D1 (Red)
  9. SFP+ Connector, J1
  10. User Red LED, D3
  11. 50 pin header (Not assembled),  J20
  12. 16 pin header (Not assembled),  J3,
  13. 10-pin header (Not assembled), J4 
  14. 50-pin header (Not assembled), J17
Initial Delivery State
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Notes :Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.If there is no components which might have initial data ( possible on carrier) you must keep the table empty

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titleInitial delivery state of programmable devices on the module
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Storage device nameContentNotes
---------

Configuration Signals
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  • Overview of Boot Mode, Reset, Enables.

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titleBoot process.
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SignalMODE Signal StateBoot ModeNote
BOOTMODE0Slave SelectMAP
1Master SPI


 Scroll Title
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titleReset process.
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SignalB2BSignal StateNote
PROG_BJM1-94Active LowClear FPGA configuration  and initiate a new configuration

Signals, Interfaces and Pins
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Notes :
  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...
Board to Board (B2B) I/Os
Number of I/O signals and Interfaces connected to the B2B connector:
 Scroll Title
anchorTable_OVSIP_IDSB2B
titleInitial delivery state of programmable devices on the moduleGeneral PL I/O to B2B connectors information
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Storage device name
Content
Notes
---
---
---
Configuration Signals
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  • Overview of Boot Mode, Reset, Enables.
B2B ConnectorInterfaceNumber of I/ONotes
JM1



User I/O52 Single ended, 27 Differential-
MGT lanes4 Differential, 2 lanes
MGT reference clock input2 Single ended, 1 Differential
JTAG4 Single ended
SoM control signals2 Single endedPROG_B, DONE
JM2User I/O36 Single ended or 18 differential-
SFP+ Interface control signals8 Single ended
QSPI interface6 Single ended
UART interface2 Single ended
User LEDs2 Single endedRed, Green
SoM control signals1 Single endedBOOTMODE

On-board Pin Header
TEBA0714 is equipped with four pin headers J17, J20, J3 and J4 which are not assembled on the board, in case of need customer can solder the pins and have access to the signals in the following table.
 Scroll Title
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titleBoot process.
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Signal
MODE Signal State
Boot ModeNote
BOOTMODE
high or open
Master SPI, x4 Mode
low or ground
Slave Selects MAP
 Scroll Title
anchorTable_OVSIP_RSTPinHeader
titleReset process.General I/O to Pin headers information
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Signal
B2BSignal StateNote
PROG_B
JM1-94Active LowClear FPGA configuration (falling edge) and initiate a new configuration sequenz (next rising edge).
Signals, Interfaces and Pins
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Notes :
  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...
Board to Board (B2B) I/Os
sortByColumn1
sortEnabledfalse
cellHighlightingtrue
Pin HeaderInterfaceNumber of I/ONotes
J17



User I/O36 Single ended, 18 DifferentialModule FPGA Bank 14
SPI interface6 Single ended-
Power4 Single ended3.3V, V_CFG
J20User I/O42 Single ended or 21 differentialModule FPGA Bank 34
Power4 Single ended3.3V, V_CFG
User LEDs2 Single endedRed, Green
SoM control signals1 Single ended'BOOTMODE'
J3JTAG 4 Single ended
UART2 Single endedB14_L25, B14_L0
ADC2 Single ended
Clock2 Single ended, 1 Differential
Power4 Single ended3.3V, V_CFG
Control Signals2 Single endedBOOTMODE, PROG_B
J4User I/O6 Single ended or 3 differential
Power2 Single ended3.3V, 3.3V_OUT

JTAG Interface Base
JTAG access to the mounted SoM is provided through B2B connector JM1 and JM2 and is also routed to the XMOD JTAG/UART header JX1.FPGA bank number and number of I/O signals connected to the B2B connector:
JM1
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titleGeneral PL I/O to B2B connectors informationJTAG pins connection
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B2B ConnectorInterfaceNumber of I/ONotes
User I/O52 Single ended, 27 Differential-MGT lanes4 Differential, 2 lanesMGT reference clock input2 Single ended, 1 DifferentialJTAG4 Single ended
SoM control signals2 Single ended'PROG_B', 'DONE'
JM2User I/O36 Single ended or 18 differential-
SFP+ Interface control signals8 Single endedQSPI interface6 Single endedUART interface2 Single ended
User LEDs2 Single endedRed, Green
SoM control signals1 Single ended'BOOTMODE'
...
XMOD Header PinSchematicB2B ConnectorPin HeaderNote
AB14_L25JM2-97J3-4UART Transfer
BB14_L0JM2-99J3-7UART Receive
EBOOTMODEJM2-100J3-9
GPROG_BJM1-94J3-11
CTCKJM1-90J3-4
DTDIJM1-86J3-10
FTDOJM1-88J3-8
HTMSJM1-92J3-12
3.3V3.3VJM1-97,99J3,J4,J17,J20Nominal Input Voltage
VIOV_CFG-J17-45Configuration Voltage

The DIP-switch S2 on XMOD Adapter TE0790 must be set as the following table.
V_CFG
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titleJTAG pins connection
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S2StatusDescriptionNotes      
1ONUpdate Mode JTAG access to SC CPLD only
2OFFMust be in OFF state always
3OFF3.3V  is inputsupplied from pin headers externally
4OFFVIO is inputsupplied from pin header externally
true
XMOD Header Pin
B2B ConnectorConnected toNote
AJM2-97B14_L25UART Transfer
BJM2-99B14_L0UART Receive
EJM2-100BOOTMODEGJM1-94PROG_BCJM1-90TCKDJM1-86TDIFJM1-88TDOHJM1-92TMS3.3VJM1-97,993.3VVIOJM2-53

SFP+ Connector
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PinConnected toNotes
VCCR3.3V
VCCT3.3V
VREFGND
TD+/TD-MGT TXMGT Lane
RD+/RD-MGT RXMGT Lane
TX/FAULTSFP0_TX_FAULSFP_CTRL
TX/DISABLESFP0_TX_DISSFP_CTRL
MOD-DEF2SFP0_SDASFP_CTRL
MOD-DEF1SFP0_SCLSFP_CTRL
MOD-DEF0SFP0_MT_DEF0SFP_CTRL
RS0/RS1SFP0_RS0_1SFP_CTRL
LOSSFP0_LOSSFP_CTRL

SMT Pin 
...
Headers
There are two SMT Pin Headers, J25-J26, J26-J27.
J26 is available to choose voltage level for VCCIO34 (FPGA Bank 34) and J27 is provided to set the voltage level of V_CFG (Configuration Voltage). In order to set the voltage level, you should connect it to the corresponding pin with the target value voltage.
Connected to
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titleSMD Connector Information
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SMT Pin Header
Pin
VCCIO/VCCVoltage LevelNotes
J26
1,3,5
VCCIO34
2

1.8V
4

2.5V
6

3.3V3.3V_OUT
J27
1,3,5
V_CFG
2


1.8V
4

2.5VV_CFG0
6
3.3V3.3V_OUT

On-board Peripherals
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Notes :
  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs
...
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Notes :In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

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Chip/InterfaceDesignatorNotes
LEDsD1...3

...
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titleOn-board LEDs
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DesignatorColorConnected toActive LevelNote
D1GreenGLEDActive 
 Low
High
D2RedRLEDActive High
D3RedDONEActive 
 High
LowDONE pin

Power and Power-On Sequence
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:
  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit

 Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

Power Supply
Power supply with minimum current capability of 3A for system startup is recommended.
...
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titlePower Consumption
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Power Input PinTypical Current
VIN3.3V* TBD

* TBD - To Be Determined
...
Determined
Power Distribution Dependencies
3.3V can be supplied through Pin Headers on specific pins. 
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titlePower Distribution

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Power-On Sequence
There is no specific power-on sequence. After power on, the module and carrier will be powered on.
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titlePower Sequency

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Power Rails
B2B Connector
JM2 Pin
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titleModule power rails.
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Power Rail Name
B2B Connector
JM1 Pin
B2B , JM1 Pin
B2B JM2 Pin
Pin Header J17Pin Header J20Pin Header J3Pin Header J4DirectionNotes
3.3V99,97-5, 465, 4655Input
1.8V-18----InputComes from Module
3.3V_OUT8354---6Output
VCCIO3461--45--OutputVariable voltage level
V_CFG53-
Input
-
V_CFG0
-
53
--InputVariable voltage level