Page History
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Bank | Type | B2B Connector | Count of MGT Lanes | Schematic Names / Connector Pins | MGT Bank's Reference Clock Inputs |
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228 | GTH | J1 | 4 GTH lanes (4 RX / 4 TX) | B228_RX3_P, B228_RX3_N, pins J1-2751, J1-2953 B228_RX2_P, B228_RX2_N, pins J1-3357, J1-3559 B228_RX1_P, B228_RX1_N, pins J1-3963, J1-4165 B228_RX0_P, B228_RX0_N, pins J1-4569, J1-4771 | 1 reference clock signal (B228_CLK0) from B2B connector 1 reference clock signal (B228_CLK1) from programmable |
229 | GTH | J1 | 4 GTH lanes (4 RX / 4 TX) | B229_RX3_P, B229_RX3_N, pins J1-27, J1-29 B229_RX2_P, B229_RX2_N, pins J1-33, J1-35 B229_RX1_P, B229_RX1_N, pins J1-39, J1-41 B229_RX0_P, B229_RX0_N, pins J1-45, J1-47 | 1 reference clock signal (B229_CLK0) from B2B connector 1 reference clock signal (B229_CLK1) from programmable |
230 | GTH | J1 | 4 GTH lanes (4 RX / 4 TX) | B230_RX3_P, B230_RX3_N, pins J1-3, J1-5 B230_RX2_P, B230_RX2_N, pins J1-9, J1-11 B230_RX1_P, B230_RX1_N, pins J1-15, J1-17 B230_RX0_P, B230_RX0_N, pins J1-21, J1-23 | 1 reference clock signal (B230_CLK1) from B2B connector 1 reference clock signal (B230_CLK0) from programmable |
128 | GTH | J2 | 4 GTH lanes (4 RX / 4 TX) | B128_RX3_N, B128_RX3_P, pins J2-28, J2-30 B128_RX2_N, B128_RX2_P, pins J2-34, J2-36 B128_RX1_N, B128_RX1_P, pins J2-40, J2-42 B128_RX0_N, B128_RX0_P, pins J2-46, J2-48 | 1 reference clock signal (B128_CLK1) from B2B connector 1 reference clock signal (B128_CLK0) from programmable |
505 | GTR | J2 | 4 GTR lanes (4 RX / 4 TX) | B505_RX3_N, B505_RX3_P, pins J2-52, J2-54 B505_RX2_N, B505_RX2_P, pins J2-58, J2-60 B505_RX1_N, B505_RX1_P, pins J2-64, J2-66 B505_RX0_N, B505_RX0_P, pins J2-70, J2-72 | 2 reference clock signals (B505_CLK0, B505_CLK1) from B2B connector 2 reference clock signal (B505_CLK2, B505_CLK3) from programmable |
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The TE0808-04 SoM is equipped with with four DDR4-2400 SDRAM modules chip with up to 8 GByte memory density. The SDRAM modules chips are connected to the Zynq MPSoC's PS DDR controller (bank 504) with a 64-bit data bus.
Refer to the Xilinx Zynq UltraScale+ datasheet DS925 for more information on whether the specific package of the Zynq UltraScale+ MPSoC supports the maximum data transmission rate of 2400 MByte/s.
Programmable PLL Clock Generator
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Input | Connected to | Frequency | Notes |
---|---|---|---|
IN0 | On-board Oscillator (U25) | 25.000000 MHz | - |
IN1 | B2B Connector pins J2-4, J2-6 (differential pair) | User | AC decoupling required on base |
IN2 | B2B Connector pins J3-66, J3-68 (differential pair) | User | AC decoupling required on base |
IN3 | OUT9 | User | Loop-back from OUT9 |
Output | Connected to | Frequency | Notes |
OUT0 | B2B Connector pins J2-3, J2-1 (differential pair) | User | Default off |
OUT1 | B230 CLK0 | User | Default off |
OUT2 | B229 CLK1 | User | Default off |
OUT3 | B228 CLK1 | User | Default off |
OUT4 | B505 CLK2 | User | Default off |
OUT5 | B505 CLK3 | User | Default off |
OUT6 | B128 CLK0 | User | Default off |
OUT7 | B2B Connector pins J2-713, J2-9 15 (differential pair) | User | Default off |
OUT8 | B2B Connector pins J2-137, J2-15 9 (differential pair) | User | Default off |
OUT9 | IN3 (Loop-back) | User | Default off |
XA/XB | Quartz (Y1) | 50.000 MHz | - |
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Signal | B2B Connector Pin | Function |
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PLL_FINC | J2-81 | Frequency increment. |
PLL_LOLN | J2-85 | Loss of lock (active-low). |
PLL_SEL0 / PLL_SEL1 | J2-93 / J2-87 | Manual input switching. |
PLL_FDEC | J2-94 | Frequency decrement. |
PLL_RST | J2-5989 | Device reset (active-low) |
PLL_SCL / PLL_SDA | J2-90 / J2-92 | I2C interface, external pull-ups needed for SCL / SDA lines. I2C address in current configuration: 1101000b1101001b. |
Table 12: B2B connector pin-out of Si5345A programmable clock generator.
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Enable-Signal | B2B Connector Pin | Max. Voltage | Note | Power-Good-Signal | B2B Connector Pin | Pull-up Resistor | Note | ||
---|---|---|---|---|---|---|---|---|---|
EN_LPD | J2-108 | 6V | TPS82085SIL data sheet | LP_GOOD | J2-106 | 4K7, pulled up to LP_DCDC | - | ||
EN_FPD | J2-102 | DCDCIN | NC7S08P5X data sheet | PG_FPD | J2-110 | 4K7, pulled up to DCDCIN | - | ||
EN_PL | J2-101 | PL_DCIN | left floating for logic high (drive to GND for logic low) | PG_PL | J2-104 | External pull-up needed (max. voltage GT_DCDC), max. sink current 1 mA | 4K7, pulled up to PL_DCIN | TPS82085SIL / | |
EN_DDR | J2-112 | DCDCIN | NC7S08P5X data sheet | PG_DDR | J2-114 | 4K7, pulled up to DCDCIN | - | ||
EN_PSGT | J2-84 | DCDCIN | NC7S08P5X data sheet | PG_PSGT | J2-82 | External pull-up needed (max. 5.5V), max. sink current 1 mA | TPS74801 data sheet | ||
EN_GT_R | J2-95 | GT_DCDC | NC7S08P5X data sheet | PG_GT_R | J2-91 | External pull-up needed (max. 5.5V), max. sink current 1 mA | TPS74401 data sheet | ||
EN_GT_L | J2-79 | GT_DCDC | NC7S08P5X data sheet | PG_GT_L | J2-97 | External pull-up needed (max. 5.5V), max. sink current 1 mA | TPS74801 data sheet | ||
EN_PLL_PWR | J2-77 | 6V | TPS82085SIL data sheet | PG_PLL_1V8 | J2-80 | External pull-up needed (max. 5.5V), max. sink current 1 mA | TPS82085SIL data sheet |
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Power Rail Name | B2B J1 Pins | B2B J2 Pins | B2B J3 Pins | Directions | Note |
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PL_DCIN | 151, 153, 155, 157, 159 | - | - | Input | - |
DCDCIN | - | 154, 156, 158, 160, | - | Input | - |
LP_DCDC | - | 138, 140, 142, 144 | - | Input | - |
PS_BATT | - | 125 | - | Input | - |
GT_DCDC | - | - | 157, 158, 159, 160 | Input | - |
PLL_3V3 | - | - | 152 | Input | U5 (programmable PLL) 3.3V nominal input |
SI_PLL_1V8 | - | - | 151 | Output | Internal voltage level 1.8V nominal output |
PS_1V8 | - | 99 | 147, 148 | Output | Internal voltage level |
PL_1V8 | 91, 121 | - | - | Output | Internal voltage level |
DDR_1V2 | - | 135 | - | Output | Internal voltage level |
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Parameter | Min | Max | Unit | Notes / Reference Document |
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PL_DCIN | -0.3 | 74 | V | TPS82085SIL / EN63A0QI data sheet / Limit is LP_DCDC over EN/PG |
DCDCIN | -0.3 | 74 | V | TPS82085SIL / TPS51206 data sheet / Limit is LP_DCDC over EN/PG |
LP_DCDC | -0.3 | 4 | V | TPS3106K33DBVR data sheet |
GT_DCDC | -0.3 | 74 | V | TPS82085SIL data sheet / Limit is LP_DCDC over EN/PG |
PS_BATT | -0.5 | 2 | V | Xilinx DS925 data sheet |
PLL_3V3 | -0.5 | 3.8 | V | Si5345/44/42 data sheet |
VCCO for HD I/O banks | -0.5 | 3.4 | V | Xilinx DS925 data sheet |
VCCO for HP I/O banks | -0.5 | 2 | V | Xilinx DS925 data sheet |
VREF | -0.5 | 2 | V | Xilinx DS925 data sheet |
I/O input voltage for HD I/O banks | -0.55 | VCCO + 0.55 | V | Xilinx DS925 data sheet |
I/O input voltage for HP I/O banks | -0.55 | VCCO + 0.55 | V | Xilinx DS925 data sheet |
PS I/O input voltage (MIO pins) | -0.5 | VCCO_PSIO + 0.55 | V | Xilinx DS925 data sheet, VCCO_PSIO 1.8V nominally |
Receiver (RXP/RXN) and transmitter | -0.5 | 1.2 | V | Xilinx DS925 data sheet |
Voltage on input pins of | -0.5 | VCC + 0.5 | V | NC7S08P5X data sheet, see schematic for VCC |
Voltage on input pins (nMR) of | -0.3 | VDD + 0.3 | V | TPS3106 data sheet, |
"Enable"-signals on TPS82085SIL (EN_PLL_PWR, EN_LPD) | -0.3 | 7 | V | TPS82085SIL data sheet |
Storage temperature (ambient) | -40 | 100 | °C | ROHM Semiconductor SML-P11 Series data sheet |
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Parameter | Min | Max | Unit | Notes / Reference Document |
---|---|---|---|---|
PL_DCIN | 23.53 | 3.6 | V | EN63A0QI / TPS82085SIL data sheet / Limit is LP_DCDC over EN/PG |
DCDCIN | 3.13 | 3.6 | V | TPS82085SIL / TPS51206PSQ data sheet / Limit is LP_DCDC over EN/PG |
LP_DCDC | 23.53 | 3.6 | V | TPS82085SIL / TPS3106 TPS3106K33DBVR data sheet |
GT_DCDC | 23.53 | 3.6 | V | TPS82085SIL data sheet/ Limit is LP_DCDC over EN/PG |
PS_BATTPS_BATT | 1.2 | 1.5 | V | Xilinx DS925 data sheet |
PLL_3V3 | 3.14 | 3.47 | V | Si5345/44/42 data sheet 3.3V typical |
VCCO for HD I/O banks | 1.14 | 3.4 | V | Xilinx DS925 data sheet |
VCCO for HP I/O banks | 0.95 | 1.9 | V | Xilinx DS925 data sheet |
I/O input voltage for HD I/O banks. | -0.2 | VCCO + 0.2 | V | Xilinx DS925 data sheet |
I/O input voltage for HP I/O banks | -0.2 | VCCO + 0.2 | V | Xilinx DS925 data sheet |
PS I/O input voltage (MIO pins) | -0.2 | VCCO_PSIO + 0.2 | V | Xilinx DS925 data sheet, VCCO_PSIO 1.8V nominally |
Voltage on input pins of NC7S08P5X 2-Input AND Gate | 0 | VCC | V | NC7S08P5X data sheet, |
Voltage on input pin 'MR' of | 0 | VDD | V | TPS3106 data sheet, |
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Module size: 52 mm × 76 mm. Please download the assembly diagram for exact numbers
Mating height with standard connectors: 4mm5mm
PCB thickness: 1.6mm
Highest part on PCB: approx. 3mm. Please download the step model for exact numbers
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Document Change History
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2022-09-13 | v.41 | Vadim Yunitski |
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2021-09-07 | V.39 | John Hartfiel |
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2021-05-17 | v.37 | John Hartfiel |
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2021-03-11 | v.35 | Antti Lukats |
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2019-01-27 | v.30 | Martin Rohrmüller |
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2018-11-20 | v.29 | John Hartfiel |
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2018-08-27 | v.27 | John Hartfiel |
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2028-06-28 | v.26 | John Hartfiel |
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2017-11-13 | SI5348 B2B IOs + link correctionv.24 | Ali Naseri |
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2017-11-13 | John Hartfiel |
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2017-10-20 | v.21 | Ali Naseri |
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2017-08-28 | v.15 | John Hartfiel |
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2017-08-28 | v.14 | Jan Kumann |
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2017-08-15 | v.12 | Vitali Tsiukala | Changed signals count in the B2B connectors table | ||||||||||||||||||||||||||||||||||
2017-08-15 | v.11 | John Hartfiel, Ali Naseri |
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2017-02-06 | v.1 | Jan Kumann | Initial document |
Disclaimer
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