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Scroll Title
titleSPI Physical Interfcaces Available
TE0630 (error)TE0300  (tick)
 TE Module SPI busB2B connection
is available?		SPI Header connection
is available?
TE0300 SPI bus(error)(tick)
TE0320 SPI bus(tick)(error)
TE0630 SPI bus(error)(error)


SPI Bus connections

Scroll pdf title
titleSPI Flash and FPGA connection; SPI Flash and USB FX2 microcontroller
TE USB FX2 module typeSPI Bus connections
TE0630TE0300Image Modified
TE0320
TE0300TE0630Image Modified

FPGA SPI Configuration Interface with FX2 microcontroller and SPI Flash

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FPGA SPI Configuration Interface (CONTROL/STATUS) Pins: PD[3:1]  for every TE USB FX2 module:

  • INIT_B, DONE, FX2_PROG_B ( aka PROG_B (Spartan3E/ASpartan-3E and Spartan-3A) or PROGRAM_B (Spartan6)),Spartan-6).
Info
FX2_PS_EN (PD0) is used to control the signal PS_EN (if the switch FX2_ON is set to on), so it is not really part of the SPI Configuration Interface. The signal PS_EN could enable/disable some power rails.

FPGA SPI Configuration Interface (DATA) Pins

TE0630 module: FPGA Spartan6

SPI_buswidth = 1 (single mode), 2 (dual mode) or 4 (quad mode) are supported by TE0630 module

ISE procedure, for example.

...

TE0300 (Spartan-3E) and TE0320 (Spartan-3A) module

This interface section is common to TE0300 (Spartan-3E) and TE0320 (Spartan-3A) module.

Only SPI_buswidth (for SPI Flash memory) = 1 is supported by TE0300 and TE0320 module.

...

Scroll Title
titleFPGA SPI Configuration Interface (DATA) Pins: PD[7:4] and MISO[3:2] for TE0630for TE0300 and TE0320 module

Pin Name
Schematic

Pin Name FPGA
FPGA Direction		Pin Name FX2
FX2 direction		DescriptionDuring ConfigurationAfter Configuration
 CSO_B

 SPI/S

CSO_B of Spartan-3

Output

PD4

Output when
the FPGA is
powerd off by
spi functions (1) 

Master SPI Chip Select Output
.

Active Low.
Connect to the SPI
Flash PROM’s
Slave Select input
If HSWAPEN_B =1,
connect this signal to VCCO
through pull-up resistor
externally.
User I/O.
Drive CSO_B High
after configuration
to disable the SPI
Flash and reclaim
MOSI, DIN, and
CCLK pins.
Optionally reuse
this pin,
MOSI, DIN,
and CCLK
to continue
communicating
with SPI flash
.

Chip select: When the S# input
signal is HIGH, the device is deselected
and DQ1 is at HIGH impedance.
Unless an internal PROGRAM, ERASE,
or WRITE STATUS REGISTER cycle
is in progress, the device will be in
the standby power mode (not the
DEEP POWERDOWN mode).
Driving S# LOW enables the device,
placing it in the active power mode.
After power-up, a falling edge on S#
is required prior to the start of any
command.

If HSWAP
or PUDC_B =1,
connect this signal
to a 4.7 kΩ
pull-up resistor
to 3.3V.
Drive CSO_B High after
configuration to disable
the SPI Flash and reclaim
the MOSI, DIN, and
CCLK pins. Optionally,
re-use this pin and MOSI,
DIN, and CCLK to
continue communicating
with SPI Flash.
 SPI/C

CCLK

Output

PD5

Output when
the FPGA is
powerd off by
spi functions (1)

Configuration Clock. Generated by
FPGA
CCLK

CCLK

Output

PD5

Output when
the FPGA is
powerd off by
spi functions (1)

 

Configuration clock source
for all configuration modes
except JTAG.
Generated by FPGA
internal oscillator.
Connect to the SPI flash Flash PROM’s
PROM’s Slave Clock input.
Drive SPI Flash’s clock input.User I/O.
Drive High
or Low
if not used.
MOSI/DI

MOSI/DI

Output/Input

Bidirectional

PD6

Output when
the FPGA is
powerd off by
spi functions (1)

 

Master FPGA Serial Data Output
and
Master FPGA Serial Data Input.
Connect to the SPI Flash PROM’s
Slave Data Input pin.

It is used in x1 (single mode),
x2 (dual mode) and x4 (quad) mode.

FPGA sends SPI flash
memory read commands
and starting address to the
PROM’s serial data input.
User I/O

MISO/DO

MISO/DO

Input

PD7

Input, by default (2)

 

Master FPGA Serial Data Input
and Slave SPI flash output.
Connect to the SPI Flash

PROM’s Slave Data Output pin.
It is used in x2 (dual mode) and
x4 (quad) mode.
FPGA receives serial data
from PROM’s serial data
output.
User I/O
MISO2 and
MISO3 aka
MISO[3:2]

MISO3 and
MISO2

Input

NOT CONNECTED

Master FPGA Serial Data Input
and Slave SPI data output.

They are used in x4 (quad) mode.
Used only when using the
fast-read quad output
command.
User I/O

TE0320 and TE0300 module:  FPGA Spartan3A and Spartan3E

Only SPI_buswidth = 1 is supported by TE0300 and TE0320 module.

Frequency controlled by ConfigRate
bitstream generator option.
If CCLK PCB trace is long or has
multiple connections, terminate this
output to maintain signal integrity.

Clock: The C input signal provides the
timing of the serial interface.
Commands, addresses, or data present
at serial data input (DQ0) is latched on
the rising edge of the serial clock (C).
Data on DQ1 changes after the falling
edge of C.

Drives SPI Flash
PROM’s clock input.
User I/O. Drive High or
Low if not used.
SPI_D

MOSI

Output

PD6

Output when
the FPGA is
powerd off by
spi functions (1)

Master SPI Serial Data Output Connect
to the SPI Flash PROM’s Slave
Data Input pin.

Serial data: The DQ0 input signal is
used to transfer data serially into the
SPI Flash device.
It receives commands, addresses,
and the data to be programmed.
Values are latched on the rising edge
of the serial clock (C).

FPGA sends
SPI Flash memory
read commands
and starting address
to the PROM’s
serial data input.
User I/O

SPI_Q

DIN

Input

PD7

Input, by default (2)

Master SPI Serial Data Input Connect
to the SPI Flash PROM’s Slave Data
Output pin.

Serial data: The DQ1 output signal is
used to transfer data serially out of the
SPI Flash device.
Data is shifted out on the falling edge
of the serial clock (C).

FPGA receives serial
data from SPI Falsh
PROM’s serial data
output.
User I/O

TE0630 (Spartan-6) module

This interface section is used only by TE0630 (Spartan-6) module.

SPI_buswidth (for SPI Flash memory) = 1 (single mode), 2 (dual mode) or 4 (quad mode) are supported by TE0630 module.

ISE procedure, for example.

  1. Open TE USB FX2  project
  2. Generate Programming File -> Process Properties
  3. Configuration options "-g SPI_buswidth" = 1,2 or 4 then Apply and OK
  4. Run "Generate programming file"
  5. Open iMPACT and generate msc from bit
  6. Program mcs to Flash in x1 (single), x2 (dual) or x4 (quad) mode
Scroll Title
titleFPGA SPI Configuration Interface (
Scroll Title
titleFPGA SPI Configuration Interface (DATA) Pins: PD[7:4] and MISO[3:2] for TE0300 and TE0320 moduleTE0630
FPGA receives serial
data from SPI Falsh
PROM’s serial data
output

Pin Name
Schematic

Pin Name FPGA
FPGA Direction

Pin Name FX2
FX2 direction

DescriptionDuring ConfigurationAfter Configuration
 SPI/S CSO_B

CSO_B of Spartan3

Output

PD4

Output when
the FPGA is
powerd off by
spi functions (1)

Master SPI Chip Select Output
Active Low.
Connect to the SPI Flash PROM’s
Slave Select input.

Chip select: When the S# input
signal is HIGH, the device is deselected
and DQ1 is at HIGH impedance.
Unless an internal PROGRAM, ERASE,
or WRITE STATUS REGISTER cycle
is in progress, the device will be in
the standby power mode (not the
DEEP POWERDOWN mode).
Driving S# LOW enables the device,
placing it in the active power mode.
After power-up, a falling edge on S#
is required prior to the start of any
command.

If HSWAP
or PUDC_B =1,
connect this signal
to a 4.7 kΩ
pull-up resistor
to 3.3V.
Drive CSO_B High after
configuration to disable
the SPI Flash and reclaim
the MOSI, DIN, and
CCLK pins. Optionally,
re-use this pin and MOSI,
DIN, and CCLK to
continue communicating
with SPI Flash.

functions (1)

 

Master SPI Chip Select Output.
Active Low. Connect to the SPI
Flash PROM’s Slave Select input
If HSWAPEN_B =1,
connect this signal to VCCO
through pull-up resistor
externally.
User I/O.
Drive CSO_B High
after configuration
to disable the SPI
Flash and reclaim
MOSI, DIN, and
CCLK pins.
Optionally reuse
this pin,
MOSI, DIN,
and CCLK
to continue
communicating
with SPI flash
CCLK

CCLK

Output

PD5

Output when
the FPGA is
powerd off by
spi functions (1)

 

Configuration clock source
for all configuration modes
except JTAG.
Generated by FPGA
internal oscillator.
Connect to the SPI flash
PROM’s Slave Clock input.
Drive SPI Flash’s clock input.User I/O.
Drive High
or Low
if not used.
MOSI/DI

MOSI/DI

Output/Input

Bidirectional

PD6

 SPI/C

CCLK

Output

PD5

Output when
the FPGA is
powerd off by
spi functions (1)

 

Master FPGA Serial Data Output
and
Master FPGA Serial Data Input
Configuration Clock. Generated by
FPGA internal oscillator
.
Connect to the SPI Flash PROM’s
Slave
Clock input.
Frequency controlled by ConfigRate
bitstream generator option.
If CCLK PCB trace is long or has
multiple connections, terminate this
output to maintain signal integrity.

Clock: The C input signal provides the
timing of the serial interface.
Commands, addresses, or data present
at serial data input (DQ0) is latched on
the rising edge of the serial clock (C).
Data on DQ1 changes after the falling
edge of C.

Data Input pin.

It is used in x1 (single mode),
x2 (dual mode) and x4 (quad) mode.

FPGA sends SPI flash
memory read commands
and starting address to the
PROM’s serial data
Drives SPI Flash
PROM’s clock
input.
User I/O. Drive High or
Low if not used.

MISO/DO

MISO/DO

Input

PD7

Input, by default (2)

 

Master FPGA Serial Data Input
and Slave SPI flash output.
Connect

SPI_D

MOSI

Output

PD6

Output when
the FPGA is
powerd off by
spi functions (1)

Master SPI Serial Data Output Connect

to the SPI Flash

PROM’s Slave
Data Input Output pin.

Serial data: The DQ0 input signal is
used to transfer data serially into the
SPI Flash device.
It receives commands, addresses,
and the data to be programmed.
Values are latched on the rising edge
of the serial clock (C).

It is used in x2 (dual mode) and
x4 (quad) mode.
FPGA receives serial data
from PROM’s serial data
output
FPGA sends
SPI Flash memory
read commands
and starting address
to the PROM’s
serial data input.
User I/O

SPI_Q

DIN

Input

PD7

Input, by default (2)

Master SPI Serial Data Input Connect
to the SPI Flash PROM’s Slave Data
Output pin.

Serial data: The DQ1 output signal is
used to transfer data serially out of the
SPI Flash device.
Data is shifted out on the falling edge
of the serial clock (C).

MISO2 and
MISO3 aka
MISO[3:2]

MISO3 and
MISO2

Input

NOT CONNECTED

Master FPGA Serial Data Input
and Slave SPI data output.

They are used in x4 (quad) mode.
Used only when using the
fast-read quad output
command.
User I/O

FPGA SPI Configuration Interface (CONTROL/STATUS) Pins

All This interface section is common to all TE USB FX2 module modules (TE0630TE0300,TE0320,TE0300TE0630): FPGA Spartan6, Spartan3A and Spartan3ESpartan-3E, Spartan-3A and Spartan-6.

FX2_PS_EN is used to control the signal PS_EN (if the switch FX2_ON is set to on), so it is not really part of the SPI Configuration Interface.

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Code Block
languagecpp
titlespi.c, TE USB FX2 firmware v3.02
OED = 0x73;       // 0b01110001; => PD6,PD5,PD4,PD0 pins output enabled;
FPGA_POWER = 0;   // power off fpga

(2) See For default direction of pin, see table 10 ("FX2LP Pin Descriptions") of the document "EZ-USB® FX2LP™ USB Microcontroller High-Speed USB Peripheral Controller" (link).

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