Versions Compared

Old Version 29

changes.mady.by.user Pedram Babakhani

Saved on

compared with

New Version Current

changes.mady.by.user John Hartfiel

Saved on

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

The Trenz Electronic TE0802 is an evalution modulea development board integrating a Xilinx Zynq UltraScale+ . Other assymbly assembly options for the FPGA and the memory chips are available. Please ask contact us for further information.

Refer to http://trenz.org/te0802-info for the current online version of this manual and other available documentation.

Page properties
hiddentrue
idComments

Notes :

...

Page properties
hiddentrue
idComments

Note:
 'Key Features' description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

  • MPSoC: Xilinx Zynq XCZU2CG-1SBVA484E  XCZU2CG - Xilinx Zynq UltraScale+ MPSoC
    • Package: 1SBVA484E
    • Speed Grade: -1 (Slowest)

    • Temperature Grade: Extended (0 to +100 °C)

  • RAM/Storages:
    • SDRAM: LPDDR4
    -3733
    • 8Gb
    256Mx32
    • 256Mx16x 2 
    Storages:
    • SPI Flash 256Mb (32M x 8) 133 MHz
    • microSD Card
    • EEPROMs 2Kb (256 x 8)
    • EEPROMs 4Kb (512 x 8)
  • Interfaces: 
    • USB JTAG/UART microUSB
    • 1GB Ethernet RJ45
    • USB 3.0 Host (Type A Connector)
    • microSD Card
    • M.2 SSD PCIe
    • 3.5 mm Earphone Jack (PWM Output)
    • Display
    Interfaces: 
    • DisplayPortPort
    • VGA
    • 4 Digit 7-Segment LED Display
    • 8 LEDs
    Audio:
    • 3.5 mm Jack (PWM Output)
    Input:
    • 5 User Buttons
    • 8 Bit Slide Switches
    • Reset Button
    User I/O:
    • 2x Pmod Connector
  • Communication:
    • 1GB Ethernet RJ45
    • USB 3.0 Host (Type A Connector)
  • Debug
    • USB JTAG/UART microUSB
  • Power
    • 5 V +/- 10%
    • ~3.5 W
  • Power
    • 5 V +/- 10%
    • ~3.5 W
  • Dimension: 100mm x 100mm

Block Diagram

Page properties
hiddentrue
idComments

add drawIO object here.

Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


...

Scroll Title
anchorFigure_OV_BD
titleTE0802 Block Diagram


Scroll Ignore

draw.io Diagram
bordertruefalse
viewerToolbartrue
fitWindowfalse
diagramDisplayName
lboxtrue
revision4
diagramNameTEMPTE0802_OV_BD
simpleViewerfalse
width
linksauto
tbstylehidden
diagramWidth638
revision3



Scroll Only

|Image RemovedImage Added


Main Components

Page properties
hiddentrue
idComments

Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


Note

For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .


...

Scroll Title
anchorFigure_OV_MC
titleTE0802 Main Components (Picture shows Revision 01)


Scroll Ignore

draw.io Diagram
bordertruefalse
viewerToolbartrue
fitWindowfalse
diagramDisplayName
lboxtrue
revision10
diagramNameTE0802_OV_MC
simpleViewertrue
width
linksauto
tbstyletophidden
diagramWidth640


Scroll Only


...

Scroll Title
anchorTable_OV_IDS
titleInitial Delivery State of Programmable Devices on the Module

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Storage device name

Content

Notes

SPI Flash (U16)

Not programmed


EEPROM (U2)Not programmedExcept Ethernet MAC
EEPROM (U18)Programmed

FTDI Configuration

LPDDR4 SDRAM (U13)Not programmed


Configuration Signals

Page properties
hiddentrue
idComments
  • Overview of Boot Mode, Reset, Enables.

Bootmode signals must be set through DIP Switch S1. 

Scroll Title
anchorTable_OV_BP
titleBoot Process

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

MODE Signal State

MODE0

MODE1

S1-

1MODE1

2(B)

MODE0

S1-

2

1(A)

Boot Mode

MODE[

1

2:0]=

00b

000

OFFOFF

JTAG

MODE[

1

2:0]=

01b

001

OFFON
-
not supported

MODE[

1

2:0]=

10b

010

ONOFFQSPI(32 bit)

MODE[

1

2:0]=

11b

011

ONONSD0(2.0)


Reset setting is available through Push Button BTN6.

Scroll Title
anchorTable_OV_RST
titleReset Process

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Signal

Connected toNote

POR_B

BTN6, Push ButtonConnected to nRESET


Signals, Interfaces and Pins

...

J3, (Display Port Connector
Scroll Title
anchorTable_SIP_B2B
titleGeneral I/O to Pin Header and Connectors Information

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

FPGA BankConnector I/O Signal CountVoltage LevelNotes
Bank 503
J8
Micro USB, J8 (
Micro USB
over FTDI)4 Single Ended3.3 VJTAG
Bank 500
J8
Micro USB, J8 (
Micro USB
over FTDI)2 Single Ended3.3 VUART
Bank 500
J9, (
Micro SD Card
)
, J97 Single Ended3.3 V
Bank 502ETH RJ45, J4
,
(
RJ45
over ETH PHY)14 Single Ended1.8 V
Bank 505, 502
J11, (
USB 3.0, J11 (USB2 over USB PHY)2 Differential Pairs
0.85 V
, 12 Single Ended-- / 1.8V

Bank 505, 501

U5, (
SSD M.2
)
, U5

2 Differential Pairs

, 5 Single Ended

-- / 3.3

0.85

V


Bank
501
U5, (SSD M.2)5 Single Ended3.3 VBank 505
505, 501Display Port Connector, J3
)
2 Differential Pairs
0.85 VBank 26J7, (D-Sub Host Socket)2
, 5 Single Ended--/ 3.3 V
Bank 26, 65, 66,
J7, (
D-Sub Host Socket (VGA), J7
12
14 Single Ended3.3 V / 1.8 V / 1.8 V
Bank 65Earphone, J12
, Headphone
3 Single Ended1.8 V
Bank 500
J10, (
Grove Connector
)
, J102 Single Ended3.3 V
Bank 26
J5 (
Pmod Host Socket
)
, J58 Single Ended3.3 V
Bank 26
J6 (
Pmod Host Socket
)
, J6 8 Single Ended3.3 V


Micro

...

SD Card

TE0802

FTDI FT2232 (U17) can be accessed through micro USB 2.0 B connector (J8) for JTAG (channel A). Channel B is connected to the FPGA and can be used for UART.

Micro SD Card

TEI0802 is equipped with a micro SD card connector (J9).

Scroll Title
anchorTable_SIP_SD
titleMicro SD Card Connector Information

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

SchematicConnected toNotes
SD_DAT0

MIO 13, FPGA Bank 500


SD_DAT1MIO 14, FPGA Bank 500
SD_DAT2MIO 15, FPGA Bank 500
SD_DAT3MIO 16, FPGA Bank 500
SD_CLKMIO 22, FPGA Bank 500
SD_CMDMIO 21, FPGA Bank 500
SD_CDMIO 24, FPGA Bank 500


RJ45 Connector

TEI0802 TE0802 is equipped with a RJ45 connector and an Ethernet PHYs. RJ45 connectors connector J4 is connected to Ethernet PHYs U6.

Scroll Title
anchorTable_SIP_RJ45
titleRJ45 Connector Information

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

PinSchematicETH PinNotes
2PHY_MDI0_PMDIP[0]
3PHY_MDI0_NMDIN[0]
4PHY_MDI1_PMDIP[1]
5PHY_MDI1_NMDIN[1]
6PHY_MDI2_PMDIP[2]
7PHY_MDI2_NMDIN[2]
8PHY_MDI3_PMDIP[3]
9PHY_MDI3_NMDIN[3]

...



USBs Sockets

TEI0802 TE0802 is equipped with a USB connector (J11).Micro USB2.0 B connector J8 and a USB3.0 connector J11.

FTDI FT2232 (U17) can be accessed through Micro USB 2.0 B connector (J8) for JTAG (channel A). Channel B is connected to the FPGA and can be used for UART.

Scroll Title
anchorTable_SIP_USB2
titleUSB2.0 B
Scroll Title
anchorTable_SIP_USB
titleUSB Socket Information

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

USB2.0 PinSchematic
Corresponding Signals
Connected toNotes
D-
USB0_
D_N
USB0_DATA0...7MIO 52...63 FPGA Bank 502

FTDI, U17


D+
USB0_
D_P
USB0_DATA0...7MIO 52...63 FPGA Bank 502StdA_SSRX-
FTDI, U17
VbusUSB_
RX2_N
VBUS
-FPGA Bank 505StdA_SSRX+USB_RX2_P-FPGA Bank 505StdA_SSTX-U3D2_NUSB_TX2_NFPGA Bank 505StdA_SSTX+U3D2_PUSB_TX2_PFPGA Bank 505

SSD M.2

TEI0802 is equipped with a SSD M.2 connector (U5).

GND



Scroll Title
anchorTable_SIP_SSDUSB3
titleSSD M.2 Connector USB3.0 A Socket Information

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

USB3.0 PinSchematicConnected toNotes
PERn0/SATA
D-
B+
SSD
USB0_
RX3
D_N
Pin M22, FPGA Bank 505PERp0/SATA-B-SSD_RX3_PPin M21, FPGA Bank 505PERn0/SATA-A+

SSD_TXC3_N

Pin K22, FPGA Bank 505PERp0/SATA-A-SSD_TXC3_PPin M21, FPGA Bank 505REFCLKN

SSD_RCLK_N

Pin 9, Clock Generator U8REFCLKPSSD_RCLK_PPin 10, Clock Generator U8DAS/DSS#SSD_DASMIO35, FPGA Bank 501DEVSLPSSD_SLEEPMIO32, FPGA Bank 501PERST#SSD_PERSTnMIO31, FPGA Bank 501CLKREQ#SSD_CLKRQMIO33, FPGA Bank 501PEWake#SSD_WAKEMIO34, FPGA Bank 501

Display Port

USB PHY, U22
D+USB0_D_PUSB PHY, U22
StdA_SSRX-USB_RX2_NFPGA Bank 505
StdA_SSRX+USB_RX2_PFPGA Bank 505
StdA_SSTX-USB_TX2_NFPGA Bank 505
StdA_SSTX+USB_TX2_PFPGA Bank 505
VBUSVBUSUSB PHY, U22


SSD M.2 Connector

TE0802 is equipped with a SSD M.2 connector (U5TEI0802 is equipped with a Display Port connector (J3).

Scroll Title
anchorTable_SIP_DPSSD
titleDisplay Port Socket SSD M.2 Connector Information

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

PinSchematic
Corresponding Signals
Connected toNotes
DP_TX_L0_P/NDP0_TX_P/N
PERn0/SATA-B+

SSD_RX3_N

Pin M22
Pin A19/A20
, FPGA Bank 505
DP_TX_L1_P/NDP1_TX_P/NPin C19/C20

PERp0/SATA-B-SSD_RX3_PPin M21, FPGA Bank 505
PERn0/SATA-A+

SSD_TXC3_N

Pin K22, FPGA Bank 505
DP_TX_AUX_P/NDP_AUX_TX/RXMIO27, MIO30, FPGA Bank 501