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HTML

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id	Comments

Important General Note:

If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

Figure template:

Scroll Title

anchor	Figure_anchorname
title	Text

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, objects are only linked.

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf PDF export bug is fixed

Table template:
- Layout macro can be use for landscape of large tables
Scroll Title
anchor Table_tablename
title Text
Scroll Table Layout
orientation portrait
sortDirection ASC
repeatTableHeaders default style
widths sortByColumn 1
sortEnabled false
cellHighlighting true
Example Comment
1 2

The anchors of the Scroll Title should be named consistant consistent across TRMs. A An incomplete list of examples is given below
- <type>_<main section>_<name>
  - type: Figure, Table
  - main section:
    - "OV" for Overview
    - "SIP" for Signal Interfaces and Pins,
    - "OBP" for On board Peripherals,
    - "PWR" for Power and Power-On Sequence,
    - "B2B" for Board to Board Connector,
    - "TS" for Technical Specification
    - "VCP" for Variants Currently in Production
    - "RH" for Revision History
  - name: custom, some fix names, see below
- Fix names:
  - "Figure_OV_BD" for Block Diagram
  - "Figure_OV_MC" for Main Components
  - "Table_OV_IDS" for Initial Delivery State
  - "Table_PWR_PC" for Power Consumption
  - "Figure_PWR_PD" for Power Distribution
  - "Figure_PWR_PS" for Power Sequence
  - "Figure_PWR_PM" for Power Monitoring
  - "Table_PWR_PR" for Power Rails
  - "Table_PWR_BV" for Bank Voltages
  - "Table_TS_AMR" for Absolute_Maximum_Ratings
  - "Table_TS_ROC" for Recommended_Operating_Conditions
  - "Figure_TS_PD" for Physical_Dimensions
  - "Table_VCP_SO" for TE_Shop_Overview
  - "Table_RH_HRH" for Hardware_Revision_History
  - "Figure_RH_HRN" for Hardware_Revision_Number
  - "Table_RH_DCH" for Document_Change_History
Use Anchor in the document: add link macro and add "#<anchorname>
Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>

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id	Comments

Note for Download Link of the Scroll ignore macro:

Link to the base folder of the module (remove de/ or en/ from the URL): for example:https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/6x6/TE0728

Scroll Ignore
Download PDF version of this document.

Scroll pdf ignore

Table of Contents

Table of Contents

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Trenz Electronic TE0728 is an automotive-grade FPGA module integrating an Automotive Xilinx Zynq-7 FPGA, two 100 Mbit Ethernet transceivers (PHY) , DDR3L SDRAMDDR3 SDRAM, QSPI Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips.

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- Note:

Xilinx

XA7Z020

XC7Z020-1CLG484Q (Automotive) [

Z7014S is

XA7Z014S is available on

demand]

Rugged for shock and high vibration
Dimensions: 6 x 6 cm

Temperature range: Automotive

other assembly options]
- Package: CL/CLG484
- Speed Grade: -1
- Temperature Grade: Expanded (-40 to +128 °C)
Dual-Core ARM Cortex-A9 MPCore
2 x 100 MBit Ethernet transceiver (PHY)

DDR3L SDRAM, 16-bit-width [

DDR3 SDRAM, up to 512MB, up to 1066 Mb/s, connected to PS [different size is available on other assembly options]
QSPI Flash memory (with XiP support) [different size is available on other assembly options]
Programmable SIT8918A , PS clock generator
2 Kbit serial EEPROM
Three user LEDs
CAN transceiver (PHY)
Temperature compensated RTC (real-time clock)
2 x 100 MBit Ethernet transceiver (PHY)
Board to Board (B2B)
- Plug-on module with 3 x 80-pin Samtec Micro Tiger Eye(TM) high-speed connectors

76 single ended

I/O

, 24 LVDS pairs (48 I/O) and 42 MIO available on board-to-board connectorsCAN transceiver (PHY)

Interface
- 42x MIO
- 200x HR
- 128x PS IO
- 0x GTP Transceiver
- 0x GTX Transceiver

Power Supply
- 12 V power supply with watchdog
Others:
- Dimensions: 6 x 6 cm
- Rugged for shock and high vibration
- On-board high-efficiency DC-DC converters
- System management and power sequencing
- eFUSE bit-stream encryption
- AES bit-stream encryption
Temperature compensated RTC (real-time clock)
Three user LEDs
- Evenly-spread supply pins for good signal integrity

Depending on the customer design, additional cooling might be required.

Block Diagram

Scroll Title

anchor	Figure_OV_BD
title	TE0728 block diagram

Scroll Ignore

draw.io Diagram

lboxwidth

border	false
viewerToolbar	true
fitWindow	false	diagramDisplayName	true
revision	14
diagramName	TE0728_OV_BD
simpleViewer	false
links	auto
tbstyle	hidden
lbox	true
diagramWidth	641
revision	25

Scroll Only

Main Components

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id	Comments

Notes :

|Picture of the PCB (top and bottom side) with labels of important components
Add List below

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Scroll Title

anchor	Figure_OV_MC
title	TE0728 main components

Scroll Ignore

draw.io Diagram

border	false
viewerToolbar	true
fitWindow	false	diagramDisplayName	lbox	false	revision	44
diagramName	TE0728_MC2
simpleViewer	true
width	640
links	auto
tbstyle	hidden
lbox	false
diagramWidth	633
revision	117350

Scroll Only

scroll-pdf	true
scroll-office	true
scroll-chm	true
scroll-docbook	true
scroll-eclipsehelp	true
scroll-epub	true
scroll-html	true

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DDR3 SDRAM, U1
Xilinx Automotive XA7Z020-1CLG484Q ,U2
100 MBit Ethernet transceiver, U3
100 MBit Ethernet transceiver, U10
User LED Green, D4
Real Time Clock, Micro Crystal , U7
Standard Clock Oscillators, U5
64 Kbit I2C EEPROM, U11
CAN Tranceiver, U16
QSPI Nor NOR Flash memory, U13
Standard Clock Oscillators, U14
Low-Quiescent-Current Programmable Delay Supervisory Circuit, U15
Low-Quiescent-Current Programmable Delay Supervisory Circuit, U12
B2B connector , JM2
B2B connector , JM3
B2B connector , JM1

Initial Delivery State

FPGA (U2), DDR3 SDRAM (U1) and QSPI (U13) can be varied on other assembly option, for more information contact us.

Initial Delivery State

Scroll Title

anchor

Scroll Title

anchor	Table_OV_IDS
title	Initial delivery state of programmable devices on the module

Scroll Table Layout

style

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
widths	sortByColumn	1
sortEnabled	false
cellHighlighting	true

Storage Device	Symbol	Content
Quad SPI Flash	U13	Not Programmed
EEPROM	U11	Not Programmed

...

Page properties

hidden	true
id	Comments

Overview of Boot Mode, Reset, Enables,

...

Scroll Title

anchor	Table_OV_BP
title	Boot process.

Scroll Table Layout

widths

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default	style
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Signal	FPGA Bank	Pin	B2B	Signal State	Boot Mode
Boot_R	500	E4	J2-11	Low	QSPI
Boot_R	500	E4	J2-11	High	SD Card

Scroll Title

anchor	Table_OV_RST
title	Reset process.

Zynq-7020SoC includes a reset that is driven by the reset system. Hardware resets are driven by the power-on reset signal (Reset) connected to carrier and the system reset signal (PS_SRST_B) connected to VMIO, it means after power on the PS will be reset.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default

Scroll Title

anchor	Table_OV_RST
title	Reset process.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style	widths	sortByColumn	1
sortEnabled	false
cellHighlighting	true

Signal	B2B	I/O	Note
Reset	J2-7	Input	Comes from Carrier
RST_OUT	J2-9	Output	PS_PROB_B

...

Board to Board (B2B) I/Os

TE0728 Module has 3 B2B connectors and every connector has 80 pins (2 row, 40 pins).

FPGA bank number and number of I/O signals connected to the B2B connector:

22

Scroll Title

anchor	Table_SIP_B2B
title	General PL I/O to B2B connectors information

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default	style
widths	sortByColumn	1
sortEnabled	false
cellHighlighting	true

FPGA Bank	Type	B2B Connector	I/O Signal Count	Voltage Level	Notes
13	HR	J1	48 Single

-end,

ended (24 Diff)	VCCO_13	variable from carrier
500	MIO	J1	4 Singel ended	3.3V
501	MIO	J2

37

38 Singel ended

VMIO1

variable from carrier

33

HR

J3

34 Single ended (17 Diff)

3.3V

35

HR

J3

J2

20

Single ended (10 Diff)

22 Single ended (11 Diff)

3.3V

35

HR

J2

3.3V


RD+	J3-52	J3-22	In

Receive
RD-	J3-50	J3-20	In


LED1	J3-55	J3-23	Out

LED Yellow on carrier, multiple usage-ACK
LED2	J3-53	J3-21	Out


LED3	J3-51	J3-19	Out

Trenz Electronic Documentation

Versions Compared

Old Version 292

New Version Current

Key

Block Diagram

Block Diagram

Main Components

Initial Delivery State

Initial Delivery State

Board to Board (B2B) I/Os

Ethernet PHY

CAN PHY

JTAG Interface

Quad SPI Flash Memory

RTC

EEPROM

LEDs

DDR3 SDRAM

Ethernet

Ethernet

CAN Transceiver

CAN Transceiver

Oscillators

Power

Distribution Dependencies

Power on Sequence

Power Distribution Dependencies

Voltage Monitor Circuit

Power Rails

Technical Specifications

Absolute Maximum Ratings

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditionse

Physical Dimensions

Currently

Offered Variants

Hardware Revision History

	LED Green on carrier, multiple usage-Link
POWERDOWN/INT	L21	R20	In