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Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"
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Important General Note:
Export PDF to download, if vivado revision is changed!
Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)Figure template (note: inner scroll ignore/only only with drawIO object):
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Important General Note:
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Overview
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Create DrawIO object here: Attention if you copy from other page, use |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
Table template:
- Layout macro can be use for landscape of large tables
- Set column width manually (can be used for small tables to fit over whole page) or leave empty (automatically)
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Overview
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ZynqMP PS Design with Linux Example and simple frequency counter to measure SI5338 Reference CLK with Vivado HW-Manager.
Wiki Resources page: http://trenz.org/te0821-info
Key Features
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ZynqMP PS Design with Linux Example and simple frequency counter to measure SI5338 Reference CLK with Vivado HW-Manager.
Wiki Resources page: http://trenz.org/te0821-info
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Date | Vivado | Project Built | Authors | Description | ||||||||||||||||||||||||||
2021-08-17 | 2020.2 | TE0821-test_board_noprebuilt-vivado_2020.2-build_7_20210817112843.zip TE0821-test_board-vivado_2020.2-build_7_20210817112826.zip | Mohsen Chamanbaz |
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2020-10-06 | 2019.2 | TE0821-test_board_noprebuilt-vivado_2019.2-build_15_20201006104048.zip TE0821-test_board-vivado_2019.2-build_15_20201006103533.zip | John Hartfiel |
| 2020-05-29 | 2019
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- initial release
Release Notes and Know Issues
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Requirements
Software
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Vivado is included into Vitis installation
Hardware
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
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Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | EMMC | Others | Notes | |||||||
TE0821-01-2AE31KA * | 2cg_1e_4gb | REV03 | 4GB | 128MB | 64GB | NA | NA | |||||||
TE0821-01-3BI21FA | 3eg_1i_2gb | REV03 | 2GB | 128MB | 8GB | NA | NA | |||||||
TE0821-01-3BI21FL | 3eg_1i_2gb | REV03 | 2GB | 128MB | 8GB | 2.5 mm connectors | NA | |||||||
TE0821-01-3BE21FA | 3eg_1e_2gb | REV03 | 2GB | 128MB | 8GB | NA | NA | |||||||
TE0821-01-3BE21FL | 3eg_1e_2gb | REV03 | 2GB | 128MB | 8GB | 2.5 mm connectors | NA | |||||||
TE0821-01-3BE21FC | 3eg_1e_2gb | REV03 | 2GB | 128MB | 8GB | NA | without encryption/NCNR | TE0821-01-3AE31KA | 3cg_1e_4gb | REV03 | 4GB | 128MB | 64GB | NA | TE0821-01-4DE31FL | 4ev_1e_4gb | REV03 | 4GB | 128MB | 8GB | 2.5 mm connectors |
Design supports following carriers:
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Requirements
Software
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Hardware
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
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TE0701 |
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TE0703 |
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TE0705 |
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TE0706 * |
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TEBA0841 |
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Additional HW Requirements:
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Design supports following carriers
Content
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For general structure and of the reference design, see Project Delivery - Xilinx devices
Design Sources
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<design name>/constraints
<design name>/ip_lib
Additional Sources
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Prebuilt
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File | File-Extension | Description | ||||||||||||
BIF-File | *.bif | File with description to generate Bin-File | ||||||||||||
BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | ||||||||||||
BIT-File | *.bit | FPGA (PL Part) Configuration File | ||||||||||||
DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | ||||||||||||
Debian SD-Image | *.img | Debian Image for SD-Card | ||||||||||||
Diverse Reports | --- | Report files in different formats | ||||||||||||
Hardware-Platform-Specification-Files | *.xsa | Exported Vivado Hardware Specification for Vitis and PetaLinux | ||||||||||||
LabTools Project-File | *.lpr | Vivado Labtools Project File | ||||||||||||
MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) | ||||||||||||
MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) | ||||||||||||
OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | ||||||||||||
Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems | ||||||||||||
SREC-File | *.srec | Converted Software Application for MicroBlaze Processor Systems | ||||||||||||
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*used as reference |
Additional HW Requirements:
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For general structure and of the reference design, see Project Delivery - AMD devices
Design Sources
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Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
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Additional Sources
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Prebuilt
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Reference Design is available on:
Design Flow
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scroll-chm | true |
scroll-docbook | true |
scroll-eclipsehelp | true |
scroll-epub | true |
scroll-html | true |
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Download
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
Design Flow
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
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Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Code Block language bash theme Midnight title _create_win_setup.cmd/_create_linux_setup.sh ---
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Note |
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Note |
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Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Code Block language bash theme Midnight title _create_win_setup.cmd/_create_linux_setup.sh ------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- ---------------------Set design paths---------------------------- ------ Run Design with: _create_win_setup -- Use Design Path: <absolute project path> ------------- --- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide):
- Press 0 and enter to start "Module Selection Guide"
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>) Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
---------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide):
Press 0 and enter to start "Module Selection Guide"
Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note Note: Select correct one, see also Vivado Board Part Flow
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
- Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
- use TE Template from "<project folder>\os\petalinux"
use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.
The build images are located in the "<plnx-proj-root>/images/linux" directory
- Configure the boot.scr file as needed, see Distro Boot with Boot.scr
- Copy PetaLinux build image files to prebuilt folder
copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
Info "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"
Page properties hidden true id Comments This step depends on Xilinx Device/Hardware
for Zynq-7000 series
- copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
for ZynqMP
- copy u-boot.elf, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
for ...
- ...
Generate Programming Files with Vitis
Code Block language py theme Midnight title run on Vivado TCL (Script generates applications design and bootable files, which are defined in "test_board\sw_lib\apps_list.csvexport files into "<project folder>\prebuilt\hardware\<short name>") TE::swhw_runbuild_vitisdesign -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)
Note TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note |
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Note: Select correct one, see also Vivado Board Part Flow |
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
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TE::hw_build_design -export_prebuilt |
Info |
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Using Vivado GUI is the same, except file export to prebuilt folder. |
Launch
export_prebuilt
Info Using Vivado GUI is the same, except file export to prebuilt folder.
Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
use TE Template from "<project folder>\os\petalinux"
use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.
The build images are located in the "<plnx-proj-root>/images/linux" directory
Configure the boot.scr file as needed, see Distro Boot with Boot.scr
- Generate Programming Files with Vitis (recommended)
- Copy PetaLinux build image files to prebuilt folder
copy u-boot.elf, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
Info "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"
- Copy PetaLinux build image files to prebuilt folder
Page properties hidden true id Comments
Note:
- Programming and Startup procedure
Programming
Note |
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Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
Note: Depending on CPLD Firmware and Boot Mode settings, QSPI boot with Linux image on SD or complete SD Boot is possible.
Get prebuilt boot binaries
Select Create and open delivery binary folder
Info |
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Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated |
QSPI-Boot mode
Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
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TE::pr_program_flash -swapp u-boot
TE::pr_program_flash -swapp hello_te0821 (optional) |
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To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup |
- use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
- Depends on Carrier, see carrier TRM.
SD-Boot mode
Use this description for CPLD Firmware with SD Boot selectable.
- Copy image.ub, boot.src and Boot.bin on SD
- use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
- or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
- Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
Select SD Card or QSPI as Boot Mode (Depends on used programming variant)
Info |
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Note: See TRM of the Carrier, which is used. |
Tip |
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Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable. |
Power On PCB
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1. ZynqMP Boot ROM loads PMU Firmware and FSBL from SD/QSPI Flash into OCM 2. FSBL init PS, programs PL using the bitstream and loads U-boot from SD into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR |
Linux
Open Serial Console (e.g. putty)Info |
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Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1) |
Linux Console:
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petalinux login: root
Password: root |
Info |
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Note: Wait until Linux boot finished |
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i2cdetect -y -r 0 (check I2C 0 Bus)
dmesg | grep rtc (RTC check)
udhcpc (ETH0 check)
lsusb (USB check) |
This step depends on Xilinx Device/Hardware
for Zynq-7000 series
- copy u-boot.elf, system.dtb, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
for ZynqMP
- copy u-boot.elf, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
for Microblaze
- ...
- Generate Programming Files with Vitis
Code Block language py theme Midnight title run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv") TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)
Note TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis
- Generate Programming Files with Petalinux (alternative), see PetaLinux KICKstart
Launch
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Programming
Note |
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Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging
Note: Depending on CPLD Firmware and Boot Mode settings, QSPI boot with Linux image on SD or complete SD Boot is possible.
Get prebuilt boot binaries
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
Press 0 and enter to start "Module Selection Guide"
Select assembly version
Validate selection
Select Create and open delivery binary folder
Info Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated
QSPI-Boot mode
Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.
Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Code Block language py theme Midnight title run on Vivado TCL (Script programs BOOT.bin on QSPI flash) TE::pr_program_flash -swapp u-boot TE::pr_program_flash -swapp hello_te0821 (optional)
Note To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup
Copy image.ub and boot.scr on SD or USB
use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
Set Boot Mode to QSPI-Boot and insert SD or USB.
Depends on Carrier, see carrier TRM.
SD-Boot mode
Use this description for CPLD Firmware with SD Boot selectable.
Copy image.ub, boot.src and Boot.bin on SD
use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
Set Boot Mode to SD-Boot.
Depends on Carrier, see carrier TRM.
Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
Prepare HW like described on section Programming
Connect UART USB (most cases same as JTAG)
Select SD Card or QSPI as Boot Mode (Depends on used programming variant)
Info Note: See TRM of the Carrier, which is used.
Tip Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
The boot options described above describe the common boot processes for this hardware; other boot options are possible.
For more information see Distro Boot with Boot.scrPower On PCB
Expand title boot process 1. ZynqMP Boot ROM loads PMU Firmware and FSBL from SD/QSPI Flash into OCM
2. FSBL init PS, programs PL using the bitstream and loads U-boot from SD into DDR,
3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
Linux
Open Serial Console (e.g. putty)
Speed: 115200
Select COM Port
Info Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
Linux Console:
Code Block language bash theme Midnight # password disabled petalinux login: root Password: root
Info Note: Wait until Linux boot finished
You can use Linux shell now.
Code Block language bash theme Midnight i2cdetect -y -r 0 (check I2C 0 Bus) dmesg | grep rtc (RTC check) udhcpc (ETH0 check) lsusb (USB check)
Option Features
Webserver to get access to Zynq
insert IP on web browser to start web interface
init.sh scripts
add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")
Vivado HW Manager
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Monitoring:
SI5338_CLK0 Counter:
Set radix from VIO signals to unsigned integer.
Note: Frequency Counter is inaccurate and displayed unit is Hz for CLK signals
SI5338 CLK1 is configured to 200MHz by default and SI5338 CLK3 is configured to 125MHz by default.
Control:
Simple loopback vio_test_in test_out
LED over X0/X1 , see TE0821 CPLD#LED
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System Design - Vivado
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Block Design
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PS Interfaces
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Activated interfaces:
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Constrains
Basic module constrains
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
Design specific constrain
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set_property PACKAGE_PIN E5 [get_ports {SI5338_CLK0 |
- Webserver to get access to Zynq
- insert IP on web browser to start web interface
- init.sh scripts
- add init.sh script on SD, content will be load automatically on startup (template included in ./misc/SD)
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Note:
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Monitoring:
- SI5338_CLK0 Counter:
- Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
- Set radix from VIO signals to unsigned integer.
Note: Frequency Counter is inaccurate and displayed unit is Hz for CLK signals
- Set radix from VIO signals to unsigned integer.
- Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
- SI5338 CLK1 is configured to 200MHz by default amd SI5338 CLK3 is configured to 125MHz by default.
Control:
- Simple loopback vio_test_in test_out
- LED over X0/X1 , see TE0821 CPLD#LED
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System Design - Vivado
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scroll-eclipsehelp | true |
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Block Design
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title-alignment | center |
title | PS Interfaces |
Constrains
Basic module constrains
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design |
Design specific constrain
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set_property PACKAGE_PIN E5 [get_ports {SI5338_CLK0_D_clk_p[0]}] set_property IOSTANDARD LVDS [get_ports {SI5338_CLK0_D_clk_p[0]}] set_property PACKAGE_PIN C3 [get_ports {SI5338_CLK3_D_clk_p[0]}] set_property IOSTANDARD LVDS [get_ports {SI5338_CLK3CLK0_D_clk_p[0]}] set_property PACKAGE_PIN B1C3 [get_ports {x0SI5338_CLK3_D_clk_p[0]}] set_property IOSTANDARD LVCMOS18LVDS [get_ports {x0[0]}] set_SI5338_CLK3_D_clk_p[0]}] set_property PACKAGE_PIN B1 [get_ports {x0[0]}] set_property IOSTANDARD LVCMOS18 [get_ports {x0[0]}] set_property PACKAGE_PIN C1 [get_ports {x1[0]}] set_property IOSTANDARD LVCMOS18 [get_ports {x1[0]}] set_property PACKAGE_PIN G8 [get_ports {PHY_LED[0]}] set_property PACKAGE_PIN E9 [get_ports {PHY_LED[1]}] set_property PACKAGE_PIN D9 [get_ports {PHY_LED[2]}] set_property IOSTANDARD LVCMOS18 [get_ports {PHY_LED[*]}] set_property PACKAGE_PIN A5 [get_ports {TEST_IN[0]}] set_property PACKAGE_PIN B6 [get_ports {TEST_OUT[0]}] set_property IOSTANDARD LVCMOS18 [get_ports {TEST_IN[0]}] set_property IOSTANDARD LVCMOS18 [get_ports {TEST_OUT[0]}] |
Software Design - Vitis
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_ports {TEST_OUT[0]}] |
Software Design - Vitis
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For Vitis project creation, follow instructions from:
Application
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For SDK project creation, follow instructions from:
Application
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---------------------------------------------------------- FPGA Example ---------------------------------------------------------- scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2022.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 2022.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: ---------------------------------------------------------- fsblTE modified 2022.2 FSBL General:
Module Specific:
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---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2020.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 2020.2 xilisf_v5_11
---------------- ZynqMP Example: ---------------------------------------------------------- Zynq Example: zynqmp_fsblTE modified 20202022.2 FSBL General:
Module Specific:
fsbl_flashTE modified 2020.2 FSBL General:
Module Specific:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General ZynqMP Example: --------------------------------------------------------------- hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. |
zynqmp_fsbl
TE modified
20202022.2 FSBL
General:
- Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
- Add Files: te
- Display FSBL Banner and Device Name
Module Specific:
- Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO
zynqmp_fsbl_flash
TE modified 2020.2 FSBL
General:
Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c- _xfsbl_hooks.h/.c (for hooks and board)
- General Changes:
- Display FSBL Banner
zynqmp_pmufw
Xilinx default PMU firmware.
----------------------------------------------------------
General Example:
hello_te0820
- and Device Name
Module Specific:
- Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO
zynqmp_pmufw
Xilinx default PMU firmware.
hello_te0821
Hello TE0821
Hello TE0820is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.
Template location: ./sw_lib/sw_apps/
zynqmp_fsbl
TE modified 2020.2 FSBL
General:
- Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device Name
Module Specific:
- Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO
zynqmp_fsbl_flash
TE modified 2020.2 FSBL
General:
- Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
zynqmp_pmufw
Xilinx default PMU firmware.
hello_te0821
Hello TE0821 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
Software Design - PetaLinux
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For PetaLinux installation and project creation, follow instructions from:
Config
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
- CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
- CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC=""
U-Boot
Start with petalinux-config -c u-boot
Changes:
CONFIG_ENV_IS_NOWHERE=y
# CONFIG_ENV_IS_IN_SPI_FLASH is not set
CONFIG_I2C_EEPROM=y
CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SYS_I2C_EEPROM_BUS=0
CONFIG_SYS_EEPROM_SIZE=256
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=0
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=0
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=1
u-boot
U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.
Software Design - PetaLinux
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For PetaLinux installation and project creation, follow instructions from:
Config
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
- select SD default instead of eMMC:
- CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
- add new flash partition for bootscr and sizing
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0_SIZE=0x2000000
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART1_SIZE=0x2000000
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_SIZE=0x40000
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_NAME="bootscr"
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_SIZE=0x80000
- Identification
- CONFIG_SUBSYSTEM_HOSTNAME="trenz"
- CONFIG_SUBSYSTEM_PRODUCT="TE0821"
U-Boot
Start with petalinux-config -c u-boot
Changes:
- MAC from eeprom together with uboot and device tree settings:
- CONFIG_ENV_OVERWRITE=y
- CONFIG_ZYNQ_MAC_IN_EEPROM is not set
- CONFIG_NET_RANDOM_ETHADDR is not set
- Boot Modes:
- CONFIG_QSPI_BOOT=y
- CONFIG_SD_BOOT=y
- CONFIG_ENV_IS_IN_FAT is not set
- CONFIG_ENV_IS_IN_NAND is not set
- CONFIG_ENV_IS_IN_SPI_FLASH is not set
- CONFIG_SYS_REDUNDAND_ENVIRONMENT is not set
- CONFIG_BOOT_SCRIPT_OFFSET=0x4040000
- Identification
- CONFIG_IDENT_STRING=" TE0821"
Change platform-top.h:
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#include <configs/xilinx_zynqmp.h>
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Device Tree
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/include/ "system-conf.dtsi"
/*----------------------- SD1 sd2.0 -----------------------*/
&sdhci1 {
disable-wp;
no-1-8-v;
};
/*----------------------- USB 2.0 only --------------------*/
&dwc3_0 {
status = "okay";
dr_mode = "host";
maximum-speed = "high-speed";
/delete-property/phy-names;
/delete-property/phys;
/delete-property/snps,usb3_lpm_capable;
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
};
&usb0 {
status = "okay";
/delete-property/ clocks;
/delete-property/ clock-names;
clocks = <0x3 0x20>;
clock-names = "bus_clk";
};
/*------------------------- ETH PHY -----------------------*/
&gem3 {
/delete-property/ local-mac-address;
phy-handle = <&phy0>;
nvmem-cells = <ð0_addr>;
nvmem-cell-names = "mac-address";
phy0: phy0@1 {
device_type = "ethernet-phy";
reg = <1>;
};
};
/*------------------------- QSPI ------------------------- */
&qspi {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
#address-cells = <1>;
#size |
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0
Change platform-top.h:
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/include/ "system-conf.dtsi" / { chosen { xlnx,eeprom = &eeprom; }; }; /* SDIO */ &sdhci1 { disable-wp; no-1-8-v; }; /* ETH PHY */ &gem3 { status = "okay"; ethernet_phy0: ethernet-phy@0 { compatible = "marvell,88e1510"; device_type = "ethernet-phy"; reg = <1>; }; }; /* USB 2.0 */ /* USB */ &dwc3_0 { status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; /delete-property/phy-names; /delete-property/phys; /delete-property/snps,usb3_lpm_capable; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; }; &usb0 { status = "okay"; /delete-property/ clocks; /delete-property/ clock-names; clocks = <0x3 0x20>; clock-names = "bus_clk"; }; /* QSPI PHY */ &qspi { #address-cells = <1>; #size-cells = <0>; status = "okay";}; }; /*---------------------------- I2C ------------------------*/ &i2c0 { flash0eeprom: flash@0eeprom@50 { compatible = "jedec,spi-nor"microchip,24aa025", "atmel,24c02"; reg = <0x0><0x50>; #address-cells = <1>; #size-cells = <1>; }; }; &i2c0 { eeprometh0_addr: eeprom@50eth-mac-addr@FA { compatible reg = "atmel,24c08" <0xFA 0x06>; reg = <0x50>}; }; }; |
FSBL patch
Must be add manually, see template
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Kernel
Start with petalinux-config -c kernel
Changes:
Only needed to fix JTAG Debug issue:
CONFIG_CPU_
FREQ is not set
CONFIG_CPU_FREQ is not set (only needed to fix JTAG Debug issue)
- CONFIG_EDAC_CORTEX_ARM64=y
Rootfs
Start with petalinux-config -c rootfs
Changes:
Rootfs
Start with petalinux-config -c rootfs
Changes:
- For web server app:
- CONFIG_busybox-httpd=y
- For additional test tools only:
- CONFIG_i2c-tools=y
- CONFIG_packagegroup-petalinux-utils=y (util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)
- For auto login:
- CONFIG_auto-login=y
- CONFIG_ADD_EXTRA_USERS="root:root;petalinux:;"
FSBL patch (alternative for vitis fsbl trenz patch)
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw"
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te_* files are identical to files in "<project folder>\sw_lib\sw_apps\zynqmp_fsbl\src" except for the PLL files (SI5338) which depend on PLL revision. The PLL files may have to be copied again manually into the appropriate petalinux folder "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw\fsbl-firmware\git\lib\sw_apps\zynqmp_fsbl\src" |
Applications
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"
startup
Script App to load init.sh from SD Card if available.See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files
webfwu
Webserver application accemble suitable for Zynq access. Need busybox-httpd
Additional Software
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SI5338
File location <design name>/misc/Si5338/"<project folder>\misc\PLL\Si5338_B\Si5338-*.slabtimeproj"
General documentation how you work with these project will be available on Si5338
Appx. A: Change History and Legal Notices
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Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
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