Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"
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Important General Note:
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Notes :
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ZynqMP PS Design with Linux Example and simple frequency counter to measure SI5338 Reference CLK with Vivado HW-Manager.
Wiki Resources page: http://trenz.org/te0821-info
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
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Design supports following carriers:
*used as reference |
Additional HW Requirements:
*used as reference |
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For general structure and of the reference design, see Project Delivery - AMD devices
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Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide): |
Press 0 and enter to start "Module Selection Guide"
Create project and follow instructions of the product selection guide, settings file will be configured automatically during this process.
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see also Vivado Board Part Flow |
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
TE::hw_build_design -export_prebuilt |
Using Vivado GUI is the same, except file export to prebuilt folder. |
Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
use TE Template from "<project folder>\os\petalinux"
use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.
The build images are located in the "<plnx-proj-root>/images/linux" directory
Configure the boot.scr file as needed, see Distro Boot with Boot.scr
copy u-boot.elf, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
"<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>" |
This step depends on Xilinx Device/Hardware for Zynq-7000 series
for ZynqMP
for Microblaze
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TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL) |
TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis |
Note:
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Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging
Note: Depending on CPLD Firmware and Boot Mode settings, QSPI boot with Linux image on SD or complete SD Boot is possible.
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
Press 0 and enter to start "Module Selection Guide"
Select assembly version
Validate selection
Select Create and open delivery binary folder
Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated |
Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.
Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
TE::pr_program_flash -swapp u-boot TE::pr_program_flash -swapp hello_te0821 (optional) |
To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup |
Copy image.ub and boot.scr on SD or USB
use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
Set Boot Mode to QSPI-Boot and insert SD or USB.
Depends on Carrier, see carrier TRM.
Use this description for CPLD Firmware with SD Boot selectable.
Copy image.ub, boot.src and Boot.bin on SD
use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
Set Boot Mode to SD-Boot.
Depends on Carrier, see carrier TRM.
Insert SD-Card in SD-Slot.
Not used on this Example.
Prepare HW like described on section Programming
Connect UART USB (most cases same as JTAG)
Select SD Card or QSPI as Boot Mode (Depends on used programming variant)
Note: See TRM of the Carrier, which is used. |
Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable. |
Power On PCB
1. ZynqMP Boot ROM loads PMU Firmware and FSBL from SD/QSPI Flash into OCM 2. FSBL init PS, programs PL using the bitstream and loads U-boot from SD into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR |
Open Serial Console (e.g. putty)
Speed: 115200
Select COM Port
Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1) |
Linux Console:
# password disabled petalinux login: root Password: root |
Note: Wait until Linux boot finished |
You can use Linux shell now.
i2cdetect -y -r 0 (check I2C 0 Bus) dmesg | grep rtc (RTC check) udhcpc (ETH0 check) lsusb (USB check) |
Option Features
Webserver to get access to Zynq
insert IP on web browser to start web interface
init.sh scripts
add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")
Note:
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Monitoring:
SI5338_CLK0 Counter:
Set radix from VIO signals to unsigned integer.
Note: Frequency Counter is inaccurate and displayed unit is Hz for CLK signals
SI5338 CLK1 is configured to 200MHz by default and SI5338 CLK3 is configured to 125MHz by default.
Control:
Simple loopback vio_test_in test_out
LED over X0/X1 , see TE0821 CPLD#LED
Note:
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Note:
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Activated interfaces:
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
set_property PACKAGE_PIN E5 [get_ports {SI5338_CLK0_D_clk_p[0]}] set_property IOSTANDARD LVDS [get_ports {SI5338_CLK0_D_clk_p[0]}] set_property PACKAGE_PIN C3 [get_ports {SI5338_CLK3_D_clk_p[0]}] set_property IOSTANDARD LVDS [get_ports {SI5338_CLK3_D_clk_p[0]}] set_property PACKAGE_PIN B1 [get_ports {x0[0]}] set_property IOSTANDARD LVCMOS18 [get_ports {x0[0]}] set_property PACKAGE_PIN C1 [get_ports {x1[0]}] set_property IOSTANDARD LVCMOS18 [get_ports {x1[0]}] set_property PACKAGE_PIN G8 [get_ports {PHY_LED[0]}] set_property PACKAGE_PIN E9 [get_ports {PHY_LED[1]}] set_property PACKAGE_PIN D9 [get_ports {PHY_LED[2]}] set_property IOSTANDARD LVCMOS18 [get_ports {PHY_LED[*]}] set_property PACKAGE_PIN A5 [get_ports {TEST_IN[0]}] set_property PACKAGE_PIN B6 [get_ports {TEST_OUT[0]}] set_property IOSTANDARD LVCMOS18 [get_ports {TEST_IN[0]}] set_property IOSTANDARD LVCMOS18 [get_ports {TEST_OUT[0]}] |
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For Vitis project creation, follow instructions from:
---------------------------------------------------------- FPGA Example ---------------------------------------------------------- scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2022.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 2022.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: ---------------------------------------------------------- fsblTE modified 2022.2 FSBL General:
Module Specific:
---------------------------------------------------------- ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2022.2 FSBL General:
Module Specific:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: ---------------------------------------------------------- hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. |
TE modified 2022.2 FSBL
General:
Module Specific:
Xilinx default PMU firmware.
Hello TE0821 is a Xilinx Hello World example as endless loop instead of one console output.
U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.
Note:
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For PetaLinux installation and project creation, follow instructions from:
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
Start with petalinux-config -c u-boot
Changes:
Change platform-top.h:
#include <configs/xilinx_zynqmp.h> #no changes |
/include/ "system-conf.dtsi" /*----------------------- SD1 sd2.0 -----------------------*/ &sdhci1 { disable-wp; no-1-8-v; }; /*----------------------- USB 2.0 only --------------------*/ &dwc3_0 { status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; /delete-property/phy-names; /delete-property/phys; /delete-property/snps,usb3_lpm_capable; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; }; &usb0 { status = "okay"; /delete-property/ clocks; /delete-property/ clock-names; clocks = <0x3 0x20>; clock-names = "bus_clk"; }; /*------------------------- ETH PHY -----------------------*/ &gem3 { /delete-property/ local-mac-address; phy-handle = <&phy0>; nvmem-cells = <ð0_addr>; nvmem-cell-names = "mac-address"; phy0: phy0@1 { device_type = "ethernet-phy"; reg = <1>; }; }; /*------------------------- QSPI ------------------------- */ &qspi { #address-cells = <1>; #size-cells = <0>; status = "okay"; flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; }; }; /*---------------------------- I2C ------------------------*/ &i2c0 { eeprom: eeprom@50 { compatible = "microchip,24aa025", "atmel,24c02"; reg = <0x50>; #address-cells = <1>; #size-cells = <1>; eth0_addr: eth-mac-addr@FA { reg = <0xFA 0x06>; }; }; }; |
Start with petalinux-config -c kernel
Changes:
Only needed to fix JTAG Debug issue:
CONFIG_CPU_FREQ is not set
Start with petalinux-config -c rootfs
Changes:
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw"
te_* files are identical to files in "<project folder>\sw_lib\sw_apps\zynqmp_fsbl\src" except for the PLL files (SI5338) which depend on PLL revision. The PLL files may have to be copied again manually into the appropriate petalinux folder "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw\fsbl-firmware\git\lib\sw_apps\zynqmp_fsbl\src" |
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"
Webserver application suitable for Zynq access. Need busybox-httpd
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File location "<project folder>\misc\PLL\Si5338_B\Si5338-*.slabtimeproj"
General documentation how you work with these project will be available on Si5338
To get content of older revision got to "Change History" of this page and select older document revision number.
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