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  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"

Template Change history:

DateVersionChangesAuthor

4.1
  • Minor changes
    • Notes
    • Tables
ED

4.0
  • Rework for smaller TRM which can be generated faster
    • Reduce Signal Interfaces Pin
    • Reduce On Board Perihery
    • Reduce Power
    • Move Configuration Signals from Overview to own section
JH

3.12
  • Version History
    • changed from list to table
  • all
    • changed title-alignment for tables from left to center
ma

3.11
  • update "Recommended Operating Conditions" section


3.1
  • New general notes for temperature range to "Recommended Operating Conditions"


3.02
  • add again fix table of content with workaround to use it for pdf and wiki
  • Export Link for key features examples
    • Notes for different Types (with and without Main FPGA)
  • Export Link for Signals, Interfaces and Pins examples
    • Notes for different Types (Modul, Modul Hypride, Evalboard, Carrier)


3.01
  • remove fix table of content and page layout ( split page layout make trouble with pdf export)
  • changed and add note to signal and interfaces, to on board periphery section
  • ...(not finished)


3.00
  • → separation of Carrier/Module and evaluation kit TRM


2.15
  • add excerpt macro to key features


2.14
  • add fix table of content
  • add table size as macro



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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

      • Figure template:

        Scroll Title
        anchorFigure_anchorname
        title-alignmentcenter
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables


      • Scroll Title
        anchorTable_tablename
        title-alignmentcenter
        titleText

        Scroll Table Layout
        orientationportrait
        sortDirectionASC
        repeatTableHeadersdefault
        style
        widths
        sortByColumn1
        sortEnabledfalse
        cellHighlightingtrue

        ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:

        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages

        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview

        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>



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-----------------------------------------------------------------------


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Note for Download Link of the Scroll ignore macro:


Scroll Ignore

Download PDF version of this document.

Overview

The Trenz Electronic TE0818 is an industrial grade MPSoC SOM integrating a Xilinx an AMD Zynq UltraScale+ MPSoC, DDR4 SDRAM with 64-Bit width data bus connection, SPI Boot Flash memory for configuration and operation, transceivers and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking connections in a compact 5.2 cm x 7.6 cm form factor.

Refer to http://trenz.org/te0818-info for the current online version of this manual and other available documentation.

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Notes :

Key Features

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Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

→ See examples fro different types <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-KeyFeatures


Excerpt
  • SoC
    • Device: ZU6 / ZU9 / ZU15 1)
    • Engine: CG / EG  1)
    • Speedgrade: -1 / -2  1)
    • Temperature Range: Extended / Industrial 1)
    • Package: FFVC900
  • RAM/Storage
    • 4 GByte DDR4 SDRAM 2)
    • 2 x 64 MByte Serial Flash 3)
    • EEPROM with MAC address
  • On Board
    • Oscillator
  • Interface
    • 4 x B2B Connector (ADM6)

      • up to 204 PL IO

        • HP: 156
        • HD: 48

      • up to 65 PS MIO

      • 4 GTR
      • 16 GTH
      • I2C, JTAG, CONFIG
  • Power
    • 3.3 V power supply via B2B Connector needed 4).
  • Dimension
    • 76 mm x 52 mm
  • Notes
    1) Please, take care of the possible assembly options. Furthermore, check whether the power supply is powerful enough for your FPGA design.
    2) Up to 32 GByte are possible with a maximum bandwidth of 2400 MBit/s.
    3) Please, take care of the possible assembly options.
    4) Dependant Dependent on the assembly option a higher input voltage may be possible

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add drawIO object in Scroll Ignore section and add reference image in Scroll Only.

Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


Note

Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name.

Example: TE0812 Block Diagram


Note

All created DrawIOs  should be named according to the Module name:

Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD



Scroll Title
anchorFigure_OV_BD
title-alignmentcenter
titleTExxxx TE0818 block diagram


Scroll Ignore

draw.io Diagram
bordertrue
diagramNameTE0818_OV_BD
simpleViewerfalse
width
linksauto
tbstyletop
lboxtrue
diagramWidth641
revision35


Scroll Only


Main Components

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Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


Note

For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .



Scroll Title
anchorFigure_OV_MC
title-alignmentcenter
titleTExxxx main components


Scroll Ignore

Create DrawIO object here: Attention if you copy from other page, objects are only linked.

Scroll Only

image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

  1. ...
  2. ...
  3. ...

Initial Delivery State

draw.io Diagram
bordertrue
diagramNameFigure_OV_MC
simpleViewerfalse
width
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tbstyletop
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diagramWidth751
revision4


Scroll Only

Image Added


  1. SoC, U1
  2. DDR4, U2, U3, U9, U12
  3. Quad SPI Flash, U7, U17
  4. Connector, J1, J2, J3, J4
  5. EEPROM, U4
  6. Clock Generator, U5
  7. Oscillator, U25, U32

Initial Delivery State

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Note

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty



Scroll Title
anchorTable_OV_IDS
title-alignmentcenter
titleInitial delivery state of programmable devices on the module

Scroll Table Layout
orientationportrait
sortDirectionASC
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style
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cellHighlightingtrue

Quad SPI

Storage device name

Content

Notes

DDR4 SDRAMnot programmed
Quad SPI Flashnot programmed
EEPROMSystem Controller CPLDnot programmed besides factory programmed MAC address
DDR4 SDRAMeMMCProgrammable Clock Generatornot programmed


Signals, Interfaces and Pins

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For subsection examples see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-Signals,InterfacesandPins

Note
  • Table with all connectors and Designtor
  • List of different interfaces per connector
  • IO CNT (for FPGA IOs where functionality can be changed by customer)


Connectors

Scroll Title
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titleBoard Connectors

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Connector TypeDesignatorInterfaceIO CNTNotes

Test Points

B2BJ1MGT PL12 x MGT (RX/TX)
B2BJ1HP52 SE / 24 DIFF
B2BJ2MGT PS2 x MGT CLK
B2BJ2CLKDIFF CLK
B2BJ2MGT PL4 x MGT (RX/TX)
B2BJ2MGT PS4 x MGT (RX/TX)
B2BJ2CFGJTAG
B2BJ2CFGMODE
B2BJ3HD48 SE / 24 DIFF
B2BJ3MGT PL3 x MGT CLK
B2BJ3CLKDIFF CLK
B2BJ3MIO65 GPIO
B2BJ4HP104 SE / 48 DIFF



Test Points

you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.

Example:

1) Direction:

    • IN (C2M): Carrier to Module, means it's an input from the point of view of this board
    • OUT (M2C): Module to Carrier, means it's output from the point of view of this board
true

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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.

Example:

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Test PointSignalNotes1)
TP1PWR_PL_OK
Scroll Title
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title-alignmentcenter
titleTest Points Information

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
stylewidths
sortByColumn1
sortEnabledfalse
cellHighlighting
Test PointSignalNotes1)
TP1PWR_PL_OK

11) Direction:

    • IN (C2M): Carrier to Module, means it's an input from the point of view of this board
    • OUT (M2C): Module to Carrier, means it's output from the point of view of this board
On


scroll-
board Peripherals

Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection

Example:

title
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Chip/InterfaceDesignatorConnected ToNotes
ETH PHYU10
  • B2B connector J1
  • SoC MIO
Gigabit ETH PHY
Scroll Title
anchorTable_OBP
title-alignmentcenter
titleOn board peripherals
Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
stylewidths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue
Chip/InterfaceDesignatorConnected ToNotes
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For example subsections see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-On-boardPeripherals

Configuration and System Control Signals

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  • Overview  all Controller signals, like Reset, Boote Mode, JTAG Interface(Connector or USB In case of FTDI)...
  • In case it's connected to CPLD always link to CPLD description and add not from the  current implementation here(in case it's available)
Scroll Title
anchorTable_OV_CNTRL
title-alignmentcenter
titleController signal.
Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueConnector+Pin

Signal Name

Direction1)Description

1) Direction:

    • IN (C2M): Carrier to Module, means it's an input from the point of view of this board
    • OUT (M2C): Module to Carrier, means it's output from the point of view of this board

Power and Power-On Sequence

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Enter the default value for power supply and startup of the module here.

  • Order of power provided Voltages and Reset/Enable signals

Link to Schematics, for power images or more details

Power Rails

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List of all Powerrails which are accessible by the customer

  • Main Power Rails and Variable Bank Power
Scroll Title
anchorTable_PWR_PR
title-alignmentcenter
titleModule power rails.
Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtruePower Rail Name/ Schematic NameConnector + PinDirection1)Notes

1) Direction:

    • IN (C2M): Carrier to Module, means it's an input from the point of view of this board
    • OUT (M2C): Module to Carrier, means it's output from the point of view of this board

Recommended Power up Sequencing

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List baseboard design hints for final baseboard development.

Scroll Title
anchorTable_BB_DH
title-alignmentcenter
titleBaseboard Design Hints
Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueSequenceNet nameRecommended Voltage RangePull-up/downDescriptionNotes

Board to Board Connectors

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  • This section is optional and only for modules.

    • use "include page" macro and link to the general B2B connector page of the module series,

    For example: 6 x 6 SoM LSHM B2B Connectors
    Include PagePD:6 x 6 SoM LSHM B2B ConnectorsPD:6 x 6 SoM LSHM B2B Connectors

    Technical Specifications

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    List of all Powerrails which are accessible by the customer

    • Main Power Rails and Variable Bank Power add boarder one time maximum Rating (Board will damaged)

    Absolute Maximum Ratings *)

    Scroll Title
    anchorTable_TS_AMR
    title-alignmentcenter
    titlePS absolute maximum ratings
    Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtruePower Rail Name/ Schematic NameDescriptionMinMaxUnitVVVVVVVV°C

    *) Stresses beyond those listed under TE0818 TRM (more or less equal to TE0808 but other connectors) may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
       or any other conditions beyond those indicated under TE0818 TRM (more or less equal to TE0808 but other connectors). Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

    Recommended Operating Conditions

    This TRM is generic for all variants. Temperature range can be differ depending on the assembly version.  Voltage range is mostly the same during variants (exceptions are possible, depending on custom request)

    Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

  • Variants of modules are described here: Article Number Information
  • Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C
  • Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
  • Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C
    • anchorTable_SIP_TPs
    title-alignmentcenter
    titleTest Points Information

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
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    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Test PointSignalNotesRevision Notes
    TP1PLL_SCLpulled-up to PS_1V8
    TP2PLL_SDApulled-up to PS_1V8
    TP3LP_DCDC

    TP4DCDCIN

    TP5GND

    TP6TCK

    TP7PL_DCIN

    TP8GND

    TP9GT_DCDC

    TP10GND

    TP11TDI

    TP12TDO

    TP13TMS

    TP14PS_1V8

    TP151V25_REFREF3312AIDCKT (U33) ouput voltageNo Net Name for REV01.
    TP16FP_0V85

    TP17DDR_2V5

    TP18DDR_PLL

    TP19PL_VCCINT

    TP20AUX_R

    TP21AVTT_R

    TP22AUX_L

    TP23DDR4-TEN
    		Only REV02.
    TP24AVCC_R

    TP25PLL_SDApulled-up to PS_1V8Only REV02.
    TP26AVTT_L

    TP27PLL_SCLpulled-up to PS_1V8Only REV02.
    TP28AVCC_L

    TP29LP_DCDC
    		Only REV02.
    TP30PS_PLL

    TP31PS_AVTT

    TP32LP_0V85

    TP33PS_AUX

    TP34PS_AVCC

    TP35DCDCIN
    		Only REV02.
    TP36POR_B

    TP37PL_DCIN
    		Only REV02.
    TP38GT_DCDC
    		Only REV02.
    TP39PS_1V8
    		Only REV02.
    TP401V25_REF
    		Only REV02.
    TP41FP_0V85
    		Only REV02.
    TP42DDR_2V5
    		Only REV02.
    TP43DDR_PLL
    		Only REV02.
    TP44PL_VCCINT
    		Only REV02.
    TP45AUX_R
    		Only REV02.
    TP46AVTT_R
    		Only REV02.
    TP47AUX_L
    		Only REV02.
    TP48AVCC_R
    		Only REV02.
    TP49AVTT_L
    		Only REV02.
    TP50AVCC_L
    		Only REV02.
    TP51PS_PLL
    		Only REV02.
    TP52PS_AVTT
    		Only REV02.
    TP53LP_0V85
    		Only REV02.
    TP54PS_AUX
    		Only REV02.
    TP55PS_AVCC
    		Only REV02.
    TP56DDR_1V2
    		Only REV02.
    TP57DDR_1V2
    		Only REV02.
    TP58SI_PLL_1V8
    		Only REV02.
    TP59SI_PLL_1V8
    		Only REV02.
    TP60PL_GT2_1V35
    		Only REV02.
    TP61PL_GT2_1V35
    		Only REV02.
    TP62PL_GT2_1V05
    		Only REV02.
    TP63PL_GT2_1V05
    		Only REV02.
    TP64PL_GT_1V35
    		Only REV02.
    TP65PL_GT_1V35
    		Only REV02.
    TP66PL_GT_1V05
    		Only REV02.
    TP67PL_GT_1V05
    		Only REV02.
    TP683.3VIN
    		Only REV02.
    TP693.3VIN
    		Only REV02.
    TP70DCDC_2V0
    		Only REV02.
    TP71DCDC_2V0
    		Only REV02.
    TP72PS_GT_1V0
    		Only REV02.
    TP73PS_GT_1V0
    		Only REV02.
    TP74PL_1V8
    		Only REV02.
    TP75PL_1V8
    		Only REV02.
    TP76VREFA
    		Only REV02.
    TP77VREFA
    		Only REV02.
    TP78VTT
    		Only REV02.
    TP79VTT
    		Only REV02.


    On-board Peripherals

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    Notes :

    In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection

    Example:

    Chip/InterfaceDesignatorConnected ToNotes
    ETH PHYU10
    • B2B connector J1
    • SoC MIO
    		Gigabit ETH PHY
    The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.



    Scroll Title
    anchorTable_TS_ROCOBP
    title-alignmentcenter
    titleRecommended operating conditions.On board peripherals

    Scroll Table Layout
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    sortEnabledfalse
    cellHighlightingtrue

    Parameter
    Chip/Interface
    Min
    Designator
    Max
    Connected To
    Units
    Notes
    		Reference DocumentVSee ???? datasheets.VSee  ???? datasheet.VSee  ???? datasheet.VSee  ???? datasheet.VSee  ???? datasheet.VSee  ???? datasheet.VSee  ???? datasheet.°CSee  ???? datasheet.

    Physical Dimensions

    • Module size: ?? mm × ?? mm.  Please download the assembly diagram for exact numbers.

    • Mating height with standard connectors: ? mm.

    PCB thickness: ?? mm.

    DDR4 SDRAM

    		U2, U3, U9, U12SoC - PS

    Quad SPI Flash

    		U7, U17SoC - PSBooting.

    EEPROM

    		U4B2B - J2

    Clock Generator

    		U5SoC, B2B

    Oscillator

    		U25Clock Generator25 MHz

    Oscillator

    		U32SoC33.333333 MHz



    Page properties
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    For example subsections see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-On-boardPeripherals

    Configuration and System Control Signals

    In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

    For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

    https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

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    Note

    For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

    • Overview  all Controller signals, like Reset, Boote Mode, JTAG Interface(Connector or USB In case of FTDI)...
    • In case it's connected to CPLD always link to CPLD description and add not from the  current implementation here(in case it's available)


    Scroll Title
    anchorTable_OV_CNTRL
    Scroll Title
    anchorFigure_TS_PD
    title-alignmentcenter
    titlePhysical DimensionController signal.

    scroll-

    ignore

    Create DrawIO object here: Attention if you copy from other page, objects are only linked.

    Scroll Only
    scroll-pdftrue
    scroll-officetrue
    scroll-chmtrue
    scroll-docbooktrue
    scroll-eclipsehelptrue
    scroll-epubtrue
    scroll-htmltrue

    image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

    Currently Offered Variants 

    Page properties
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    Set correct link to the shop page overview table of the product on English and German.

    Example for TE0706:

        ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

        DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706

    Scroll Title
    anchorTable_VCP_SO
    title-alignmentcenter
    titleTrenz Electronic Shop Overview
    Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueTrenz shop TEXXXX overview pageEnglish pageGerman page

    tablelayout
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    sortEnabledfalse
    cellHighlightingtrue

    Connector+Pin

    Signal Name

    		Direction1)Description
    J1.A45POR_OVERRIDEINOverride power-on reset delay 2).
    J2.A30PG_PLL_1V8OUTSI_PLL_1V8 power rail powered-up.
    J2.A31ERR_OUTOUTPS error indication 2).
    J2.A34ERR_STATUSOUTPS error status 2).
    J2.A35LP_GOODOUTLow-power domain powered-up. Pulled up to 3.3VIN.
    J2.A36PLL_SCLINI2C clock. Pulled up to PS_1V8.
    J2.A37PLL_SDAIN/OUTI2C data. Pulled up to PS_1V8.
    J2.A40PG_GT_LOUTLeft GTH Transceivers powered-up.
    J2.A41EN_PSGTINEnable GTR transceiver power-up.
    J2.A44 / J2.A45 /
    J2.A46 / J2.A47    		TCK / TDI / TDO / TMSSignal-dependent

    JTAG configuration and debugging interface.

    JTAG reference voltage: PS_1V8

    J2.B29PG_PSGTOUTGTR transceivers powered-up.
    J2.B30PROG_BIN/OUTPower-on reset 2). Pulled-up to PS_1V8.
    J2.B33SRST_BINSystem reset 2). Pulled-up to PS_1V8.
    J2.B34INIT_BIN/OUTInitialization completion indicator after POR 2). Pulled-up to PS_1V8.
    J2.B37PG_PLOUTProgrammable logic powered-up.
    J2.B38EN_FPDINEnable full-power domain power-up.
    J2.B41PG_FPDOUTFull-power domain powered-up.
    J2.B42EN_LPDINEnable low-power domain power-up.
    J2.B45PG_DDROUTDDR power supply powered-up.
    J2.B46DONEOUTPS done signal 2). Pulled-up to PS_1V8.
    J2.B47EN_DDRINEnable DDR power-up.
    J2.C30EN_GT_LINEnable left GTH transceiver power-up.
    J2.C31MRINManual reset.
    J2.C32PLL_SEL0INPLL clock selection.
    J2.C33PLL_RSTINPLL reset. Pulled-up to PS_1V8.
    J2.C35EN_PLINEnable programable logic power-up.
    J2.C36EN_GT_RINEnable right GTH transceiver power-up.
    J2.C37PLL_FDECINPLL Frequency decrementation.
    J2.C44 / J2.C45 / J2.C46 / J2.C47MODE3..0INBoot mode selection 2):
    • JTAG
    • QUAD-SPI (32 Bit)
    • SD1 (2.0)
    • eMMC (1.8 V)
    • SD1 LS (3.0)

    Supported Modes depends also on used Carrier.

    J2.D29EN_PLL_PWRINEnable PLL power supply.
    J2.D30PLL_FINCINPLL Frequency incrementation.
    J2.D31PLL_LOLnOUTLoss of lock status.
    J2.D32PLL_SEL1INPLL clock selection.
    J2.D33PG_GT_ROUTRight GTH Transceivers powered-up.
    J2.D37PSBATTINPS RTC Battery supply voltage 2) 3).
    J2.D38PUDC_BINConfiguration pull-ups setting 2). Pulled-up to PL_1V8.
    J2.D45 / J2.D46DX_P / DX_N-SoC temperatur sensing diode pins 2).

    1) Direction:

      • IN: Input from the point of view of this board.
      • OUT: Output from the point of view of this board.

    2) See UG1085 for additional information.

    3) See Recommended Operating Conditions.


    Power and Power-On Sequence

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    • Order of power provided Voltages and Reset/Enable signals

    Link to Schematics, for power images or more details


    Power Rails

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    List of all Powerrails which are accessible by the customer

    • Main Power Rails and Variable Bank Power



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    Power Rail Name/ Schematic NameConnector + PinDirection1)Notes
    VCCO_66J1.A32 / J1.A33IN
    VREF_66J1.A41IN
    3.3VINJ1.A54 / J1.A55 / J1.B55 / J1.B56IN

    PL_1V8

    		J1.C32 / J1.C33 / J1.D33 / J1.D34OUT
    PL_DCINJ1.C56 / J1.C57 / J1.C58 / J1.C59 / J1.C60 / J1.D56 / J1.D57 / J1.D58 / J1.D59 / J1.D60IN
    LP_DCDCJ2.A50 / J2.A51 / J2.A52 / J2.B50 / J2.B51 / J2.B52 / J2.C50 / J2.C51 / J2.C52 / J2.D50 / J2.D51 / J2.D52IN
    DCDCINJ2.A57 / J2.A58 / J2.A59 / J2.A60 / J2.B57 / J2.B58 / J2.B59 / J2.B60 / J2.C57 / J2.C58 / J2.C59 / J2.C60 / J2.D57 / J2.D58 / J2.D59 / J2.D60 / IN
    PS_BATTJ2.D37IN
    DDR_1V2J2.D47OUT
    PS_1V8J2.C34 / J2.D34 / J3.A56 / J3.B56 / J3.C56 / J3.D56OUT
    PLL_3V3J3.A55IN
    GT_DCDCJ3.A59 / J3.A60 / J3.B59 / J3.B60 / J3.C59 / J3.C60 / J3.D59 / J3.D60 /IN
    VCCO_48J3.C7 / J3.C8 / J3.D8 / J3.D9IN
    VCCO_47J3.C19 / J3.C20 / J3.D20 / J3.D21IN
    VCCO_64J4.B21 / J4.B39IN
    VREF_64J4.B30IN
    VCCO_65J4.C21 / J4.C39IN
    VREF_65J4.C30IN

    1) Direction:

      • IN: Input from the point of view of this board.
      • OUT: Output from the point of view of this board.

    Recommended Power up Sequencing

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    The power up sequencing highly depends on the use case. In general, it should be possible to enable/disable the processing system (PS) / programmable logic (PL) independently. Furthermore, within the processing logic it should be possible to enable/disable only low-power domain and/or low-power and full-power domain. Additionally, usage of GTR for PS side and GTH for PL side should be possible. GTH transceivers on left and right side are usable independently. Because of this flexibility the needed parts of the following table needs to be selected individually. For detailed information take a look into schematics.

    SequenceNet nameRecommended Voltage RangePull-up/downDescriptionNotes
    0---Configuration signal setup.See Configuration and System Control Signals.
    1 1)PSBATT1.2 V ... 1.5 V-Battery connection.Battery Power Domain usage. When not used, tie to GND.
    13.3VIN3.3 V (± 5 %)-Management power supply.Management module power supply. 0.5 A recommended.
    GTH / GTR Transceiver clocking (Only necessary in cases where the PLL clock is used for GTH / GTR.):
    1 1)GT_DCDC3.3 V (± 5 %) 2)
    		GTH transceiver power supply.Main module power supply for GTH / GTY transceiver. 5 A recommended. Power consumption depends mainly on design and cooling solution.
    1 1)EN_PLL_PWR-PU 3), 3.3VINPLL power enable.
    1 1)PG_PLL_1V8-PU 3), 3.3VINPLL power good status.
    1 1)PLL_3V33.3 V (± 5 %)
    		PLL power supply
    2Processing System (PS):

    		Procedure for PS starting.
    2.1Low-power domain:Bring-up for low-power domain PS.
    2.1.1LP_DCDC3.3 V (± 5 %) 2)-Low-power domain power supply.Main module power supply for low-power domain. 5.5 A recommended. Power consumption depends mainly on design and cooling solution.
    2.1.2EN_LPD-PU 3), 3.3VINLow-power domain power enable.
    2.1.3LP_GOOD-PU 3), 3.3VINLow-power domain power good status.Module power-on sequencing for low-power domain finished.
    2.2Full-power domain:Bring-up for full-power domain PS.Full-power PS domain needs powered low-power PS domain.
    2.2.1DCDCIN3.3 V (± 5 %) 2)
    		Full-power domain and GTR transceiver power supply.Main module power supply for full-power domain. 7 A recommended. Power consumption depends mainly on design and cooling solution.
    2.2.2EN_FPD3.3 V-Full-power domain power enable.
    2.2.3PG_FPD-PU 3), 3.3VINFull-power domain power good status.Module power-on sequencing for full-power domain finished.
    2.2.4EN_DDR3.3 V-DDR memory power enable.
    2.2.5PG_DDR
    		PU 3), 3.3VINDDR memory power good status.Module power-on sequencing for DDR memory finished.

    2.3

    		GTR TransceiverProcedure for GTR transceiver starting.PS transceiver usage needs powered PS (low- and full-power domain).
    2.3.1EN_PSGT3.3 V-GTR transceiver power enable.
    2.3.2PG_PSGT-PU 3), 3.3VINGTR transceiver power good status.Module power-on sequencing for GTR transceiver finished.
    2Programmable Logic (PL)Procedure for PL starting.PS and PL can be started independently.
    2.1PL_DCIN3.3 V (± 5 %) 2)-Programmable logic power supply.Main module power supply for programmable logic. 12 A recommended. Power consumption depends mainly on design and cooling solution.
    2.2EN_PL-PU 3), 3.3VINProgrammable logic power enable.
    2.3PG_PL-PU 3), 3.3VINProgrammable logic power good status.Module power-on sequencing for programmable logic finished. Periphery and variable bank voltages can be enabled on carrier.
    2.4VCCO_47 / VCCO_48 / VCCO_64 / VCCO_65 / VCCO_66 4)-Module bank voltages.Enable bank voltages after PG_PL deassertion.
    3GTH / GTY TransceiverProcedure for GTH / GTY transceiver starting.PL transceiver usage needs powered PL and low-power PS domain.
    3.1GT_DCDC3.3 V (± 5 %) 2)-GTH transceiver power supply.Main module power supply for GTH transceiver. 5 A recommended. Power consumption depends mainly on design and cooling solution.
    3.2EN_GT_L / EN_GT_R3.3 V-GTH / GTY left / right transceiver power enable.Transceivers on left / right side can be used independently.
    3.3PG_GT_L / PG_GT_R-PU 3), 3.3VINGTH / GTY transceiver power good status.

    1) (optional)

    2) Dependent on the assembly option a higher input voltage may be possible. 

    3) (on module)

    4) See DS925 for additional information.

    Board to Board Connectors

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    • use "include page" macro and link to the general B2B connector page of the module series,

      For example: 6 x 6 SoM LSHM B2B Connectors

      Include Page
      6 x 6 SoM LSHM B2B Connectors
      6 x 6 SoM LSHM B2B Connectors

    Include Page
    5.2 x 7.6 UltraSoM+ ADF6 and ADM6 B2B Connectors
    5.2 x 7.6 UltraSoM+ ADF6 and ADM6 B2B Connectors

    Technical Specifications

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    List of all Powerrails which are accessible by the customer

    • Main Power Rails and Variable Bank Power add boarder one time maximum Rating (Board will damaged)

    Absolute Maximum Ratings *)

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    Power Rail Name/ Schematic NameDescriptionMinMaxUnit
    LP_DCDCMicromodule Power-0.3006.0V
    DCDCINMicromodule Power-0.3007.0V
    GT_DCDCMicromodule Power-0.3006.0V
    PL_DCINMicromodule Power-0.300

    7.0

    		V
    3.3VINMicromodule Power-0.3003.600V
    PLL_3V3PLL power supply-0.5003.8V
    PS_BATTRTC / BBRAM-0.5002.000V
    VCCO_47HD IO Bank power supply-0.5003.400V
    VCCO_48HD IO Bank power supply-0.5003.400V
    VCCO_64HP IO Bank power supply-0.5002.000V

    VCCO_65

    		HP IO Bank power supply-0.5002.000V
    VCCO_66HP IO Bank power supply-0.5002.000V
    VREF_64Bank input reference voltage-0.5002.000V
    VREF_65Bank input reference voltage-0.5002.000V
    VREF_66Bank input reference voltage-0.5002.000V


    *) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

    Recommended Operating Conditions

    This TRM is generic for all variants. Temperature range can be differ depending on the assembly version. Voltage range is mostly the same during variants (exceptions are possible, depending on custom request).

    Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

    • Variants of modules are described here: Article Number Information
    • Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C
    • Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
    • Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C
    • The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.


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    ParameterMinMaxUnitsReference Document
    LP_DCDC 1)3.2013.399V
    DCDCIN 1)3.1353.465V
    GT_DCDC 1)3.2013.399V
    PL_DCIN 1)3.135

    3.465

    		V
    3.3VIN3.1353.465V
    PLL_3V33.2013.399V
    PS_BATT1.2001.500VSee FPGA datasheet.
    VCCO_471.1643.399VSee FPGA datasheet.
    VCCO_481.1643.399VSee FPGA datasheet.
    VCCO_640.9701.854VSee FPGA datasheet.

    VCCO_65

    		0.9701.854VSee FPGA datasheet.
    VCCO_660.9701.854VSee FPGA datasheet.
    VREF_640.61.2VSee FPGA datasheet.
    VREF_650.61.2VSee FPGA datasheet.
    VREF_660.61.2VSee FPGA datasheet.

    1) Higher values may possible. For more information consult schematic and according datasheets.


    Physical Dimensions

    • Module size: 76 mm × 52 mm.  Please download the assembly diagram for exact numbers.

    • Mating height with standard connectors: 5 mm.

    PCB thickness: 1.6 mm (± 10 %).

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    In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

    For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

    https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

    Note

    For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .



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    Currently Offered Variants 

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    Set correct link to the shop page overview table of the product on English and German.

    Example for TE0706:

        ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

        DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706


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    Trenz shop TE0818 overview page
    English pageGerman page


    Revision History

    Hardware Revision History

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    Set correct links to download  Carrier, e.g. TE0706 REV02:

      TE0706-02  ->   https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

    Note:

    • Date format:  YYYY-MM-DD

    • Example: 

      DateRevisionChangesDocumentation Link
      2020-11-25REV02
      • Resistors R14 and R15 was replaced by 953R (was 5K1)
      • Resistor R5 was replaced by 5K1, R8 by 953R (was 9K09 and 1K69 respectively)
      		REV02



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    DateRevisionChangesDocumentation Link
    -REV02
    1. Added capacitors C178, C187, C188, C189 (470nF) to VTT net.
    2. Added U18/ U37 compensation network: R119, C190, C191. R118 is optional jumper and is installed when using the internal compensation network. External compensation network is used by default.
    3. Connected all DDR4 TEN pins together and pulled them down with resistor R120 and added testpoint TP23.
    4. Added testpoints TP25, TP27, TP29, TP35, TP37...TP79.
    5. Changed capacitor C112 size from 0402 to 0201 and voltage rating from 16 V to 10 V.
    6. Changed ferrid beads from MPZ0603S121HT000 to BLM15PX800SZ1D for L1, L2, L3, L4, L5, and L7.
    7. Changed ferrid beads from MPZ1608S221A to BLM15PX800SZ1D for L6 and L8.
    8. Added diode D2 between U41 pin 3 net MR and voltage rail 3.3VIN.
    9. Modified trace length.
    10. Updated documentation overviews.
    		REV02
    -REV01First Production ReleaseREV01

    Revision History

    Hardware Revision History

    Set correct links to download  Carrier, e.g. TE0706 REV02:

      TE0706-02  ->   https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

    Note:

  • Date format:  YYYY-MM-DD

    • Example: 

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    DateRevisionChangesDocumentation Link
    2020-11-25REV02
    • Resistors R14 and R15 was replaced by 953R (was 5K1)
    • Resistor R5 was replaced by 5K1, R8 by 953R (was 9K09 and 1K69 respectively)
    		REV02
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    Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

    Document Change History

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      • Add new row below first

      • Copy "Page Information Macro (date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

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    DateRevisionContributorDescription

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    <add TRM change list here>

    • Added power supply PLL_3V3 in table "Recommended Power up Sequencing".
    • Fix typo.

    2023-09-20

    v.16

    ED

    • Updated for REV02

    2023-01-12

    v.13

    ED

    • Initial Document

    --

    all

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    • --


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