Versions Compared

Old Version 30

changes.mady.by.user Manuela Strücker

Saved on

compared with

New Version Current

changes.mady.by.user John Hartfiel

Saved on

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.


Page properties
hiddentrue
idComments

Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"


20220125102022-019
  • extended notes for microblaze boot process with linux
  • add u.boot.dtb to petalinux notes
  • add dtb to prebuilt content
    • replace 20.2 with 21jh2021288202172021046removed zynq_ from zynq_fsbl202104285

  • added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export

    • minor typos, formatting202104274

    Date

    Version

    Changes

    Author

    2024-06-183.1.
    • removed u-boot.dtb from QSPI-Boot mode and SD-Boot mode. Is implemented in BOOT.bin
    • corrected Boot Source File in Boot Script-File
    		ma18
    • Design flow → point 6 changed: the file boot.scr ... changed from required to optional
    		ma
    2023-12-143.1.17
    • updated according to Vivado 2023
    • .2
    		ma
    2023-06-133.1.16
    • Design flow:
      • added alternative programming files in Petalinux
    • added chapter FSBL Patch in Software Design - Petalinux
    		ma
    2023-06-013.1.15
    • removed u-boot.dtb from Design flow
    		ma
    2023

    • added boot process for Microblaze

    • minor typos, formatting

    ma

    		-06-013.1.

    • carrier reference note

    jh

    		14
    • expandable lists for revision history and supported hardware
    		wh
    2023-05-253.1.13
    • updated according to Vivado 2022.2
    		ma
    2023-02-083.1.12
    • removed content of
      • Special FSBL for QSPI programming
    		ma
    2022-08-243.1.

    • Version History

      • changed from list to table

    • Design flow

      • removed step 5 from Design flow

      • changed link from TE Board Part Files to Vivado Board Part Flow

      • changed cmd shell from picture to codeblock

      • added hidden template for "Copy PetaLinux build image files", depending from hardware

      • added hidden template for "Power on PCB", depending from hardware

    • Usage update of boot process

    • Requirements - Hardware

      • added "*used as reference" for hardware requirements

    • all

      • placed a horizontal separation line under each chapter heading

      • changed title-alignment for tables from left to center

    • all tables

      • added "<project folder>\board_files" in Vivado design sources

    ma

    3.1.3

    • Design Flow

      • formatting

    • Launch

      • formatting

    ma

    3.1.2

    • minor typing corrections

    • replaced SDK by Vitis

    • changed from / to \ for windows paths

    • replaced <design name> by <project folder>

    • added "" for path names

    • added boot.src description

    • added USB for programming

    ma

    3.1.1

    • swapped order from prebuilt files

    • minor typing corrections

    • removed Win OS path length from Design flow, added as caution in Design flow

    ma

    3.1

    • Fix problem with pdf export and side scroll bar

    • update 19.2 to 20.2

    • add prebuilt content option

    3.0

    • add fix table of content

    • add table size as macro

    • removed page initial creator

    Custom_table_size_100

    Page properties
    hiddentrue
    idComments

    Important General Note:

  • Export PDF to download, if vivado revision is changed!

    • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

    Figure template (note: inner scroll ignore/only only with drawIO object):

    Scroll Title
    anchorFigure_xyz
    titleText
    Scroll Ignore

    Create DrawIO object here: Attention if you copy from other page, use

    Scroll Only

    image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

    11
    • Modification from link "available short link"
    		ma
    2022-01-253.1.10
    • removed u-boot.dtb from QSPI-Boot mode and SD-Boot mode. Is implemented in BOOT.bin
    • corrected Boot Source File in Boot Script-File
    		ma
    2022-01-143.1.9
    • extended notes for microblaze boot process with linux
    • add u.boot.dtb to petalinux notes
    • add dtb to prebuilt content
    • replace 20.2 with 21.2
    		jh

    2021-06-28

    3.1.8

    • added boot process for Microblaze

    • minor typos, formatting

    ma

    2021-06-01

    3.1.7

    • carrier reference note

    jh

    2021-05-04

    3.1.6

    • removed zynq_ from zynq_fsbl

    ma

    2021-04-28

    3.1.5

    • added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export

    • minor typos, formatting

    ma

    2021-04-27

    3.1.4

    • Version History

      • changed from list to table

    • Design flow

      • removed step 5 from Design flow

      • changed link from TE Board Part Files to Vivado Board Part Flow

      • changed cmd shell from picture to codeblock

      • added hidden template for "Copy PetaLinux build image files", depending from hardware

      • added hidden template for "Power on PCB", depending from hardware

    • Usage update of boot process

    • Requirements - Hardware

      • added "*used as reference" for hardware requirements

    • all

      • placed a horizontal separation line under each chapter heading

      • changed title-alignment for tables from left to center

    • all tables

      • added "<project folder>\board_files" in Vivado design sources

    ma


    3.1.3

    • Design Flow

      • formatting

    • Launch

      • formatting

    ma


    3.1.2

    • minor typing corrections

    • replaced SDK by Vitis

    • changed from / to \ for windows paths

    • replaced <design name> by <project folder>

    • added "" for path names

    • added boot.src description

    • added USB for programming

    ma


    3.1.1

    • swapped order from prebuilt files

    • minor typing corrections

    • removed Win OS path length from Design flow, added as caution in Design flow

    ma


    3.1

    • Fix problem with pdf export and side scroll bar

    • update 19.2 to 20.2

    • add prebuilt content option



    3.0

    • add fix table of content

    • add table size as macro

    • removed page initial creator



    Custom_table_size_100

    Page properties
    hiddentrue
    idComments

    Important General Note:

    • Export PDF to download, if vivado revision is changed!

    • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

      • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

        • Figure template (note: inner scroll ignore/only only with drawIO object):

          Scroll Title
          anchorFigure_xyz
          titleText


          Scroll Ignore

          Create DrawIO object here: Attention if you copy from other page, use


          Scroll Only

          image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



        • Table template:

          • Layout macro can be use for landscape of large tables

          • Set column width manually (can be used for small tables to fit over whole page) or leave empty (automatically)


        • Scroll Title
          anchorTable_xyz
          titleText

          Scroll Table Layout
          orientationportrait
          sortDirectionASC
          repeatTableHeadersdefault
          sortByColumn1
          sortEnabledfalse
          cellHighlightingtrue

          Example

          Comment

          1

          2



    • ...

    Overview

    Scroll Ignore
    scroll-pdftrue
    scroll-officetrue
    scroll-chmtrue
    scroll-docbooktrue
    scroll-eclipsehelptrue
    scroll-epubtrue
    scroll-htmltrue


    Page properties
    hiddentrue
    idComments

    Notes :

    • short description of the design

    • Short Link of

  • Table template:

    • Layout macro can be use for landscape of large tables

    • Set column width manually (can be used for small tables to fit over whole page) or leave empty (automatically)

    • Scroll Title
    anchorTable_xyz
    titleText

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Example

    Comment

    1

    2

  • ...

    • Overview

    Scroll Ignore
    scroll-pdftrue
    scroll-officetrue
    scroll-chmtrue
    scroll-docbooktrue
    scroll-eclipsehelptrue
    scroll-epubtrue
    scroll-htmltrue
    Page properties
    hiddentrue
    idComments

    Notes :

    Design Example with minimum PS Setup (DDR, QSPI, UART0) only for custom boards or easier debug via Vitis.

    Refer to http://trenz.org/te0803-info for the current online version of this manual and other available documentation.

    Key Features

    Page properties
    hiddentrue
    idComments

    Notes :

    • Add basic key futures, which can be tested with the design


    Excerpt

    • Vitis/Vivado 20212023.2

    • QSPI

    • Custom Carrier (minimum PS Design with available module components only)

    • Modified FSBL (some additional outputs only)

    Revision History

    Page properties
    hiddentrue
    idComments

    Notes :

    • add every update file on the download

    • add design changes on description

    Expandscroll-
    titleanchorExpand List
    Scroll Title
    anchorTable_DRH
    title-alignmentcenter
    titleDesign Revision History

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Date

    Vivado

    Project Built

    Authors

    Description

    2022
    2024-
    04
    08-
    05
    28
    2021
    2023.2TE0803-test_board-vivado_
    2021
    2023.2-build_
    11
    4_
    20220405100116
    20240823075240.zip
    TE0803-test_board_noprebuilt-vivado_
    2021
    2023.2-build_
    11
    4_
    20220405100116
    20240823075240.zip
    Manuela Strücker
    John Hartfiel
    2021
    • 2023.2 update
    • new assembly variants
    • board files: fixed PS refc clk rounding issue
    2023
    2021
    -09-
    06
    14
    2020
    2022.2TE0803-test_board-vivado_
    2020
    2022.2-build_
    7
    8_
    20210906104518
    20230914124756.zip
    TE0803-test_board_noprebuilt-vivado_
    2020
    2022.2-build_
    7
    8_
    20210906104536
    20230914124756.zipManuela Strücker
    2020
    • 2022.2 update
  • update document style

    • 2020-04-06

    • new assembly variants
    2022-10-172021.2.1
    2019.2
    TE0803-test_board-vivado_
    2019
    2021.2-build_
    9
    18_
    20200406081019
    20221017093148.zip
    TE0803-test_board_noprebuilt-vivado_
    2019
    2021.2-build_
    9
    18_
    20200406081036
    20221017093148.zip

    John Hartfiel

    • new assembly variants

    Manuela Strücker
    • script update
    2022-08-302021.2.1

    2020-03-25

    2019.2
    TE0803-test_board-vivado_
    2019
    2021.2-build_
    8
    15_
    20200325082253
    20220830131430.zip
    TE0803-test_board_noprebuilt-vivado_
    2019
    2021.2-build_
    8
    15_
    20200325082311
    20220830131430.zip

    John Hartfiel

    • script update

    2020-01-23

    Manuela Strücker
    • new assembly variants
    2022-04-052021.
    2019-
    2TE0803-test_board-vivado_
    2019
    2021.2-build_
    3
    11_
    20200123070036
    20220405100116.zip
    TE0803-test_board_noprebuilt-vivado
    _2019.2-build_3_20200123070049.zip

    John Hartfiel

    • 2019.2 update

    • Vitis support

    • FSBL SI programming procedure update 

    2019-5-06

    2018.3

    TE0803-test_board_noprebuilt-vivado_2018.3-build_05_20190506161948.zip

    TE0803-test_board-vivado_2018.3-build_05_20190506161936.zip

    John Hartfiel

    • custom FSBL

    • new assembly variants

    2018-10-26

    2018.2

    TE0803-test_board_noprebuilt-vivado_2018.2-build_03_20181026141705.zip

    TE0803-test_board-vivado_2018.2-build_03_20181026141651.zip

    John Hartfiel

    • new assembly variant

    2018-08-14

    2018.2

    TE0803-test_board_noprebuilt-vivado_2018.2-build_02_20180814103119.zip

    TE0803-test_board-vivado_2018.2-build_02_20180814103105.zip

    John Hartfiel

    • new assembly variant

    2018-07-13

    2018.2

    TE0803-test_board_noprebuilt-vivado_2018.2-build_02_20180713085721.zip

    TE0803-test_board-vivado_2018.2-build_02_20180713085704.zip

    John Hartfiel

    • additional notes for FSBL generated with Win SDK

    • changed *.bif

    2018-05-17

    2017.4

    TE0803-test_board_noprebuilt-vivado_2017.4-build_09_20180517152118.zip

    TE0803-test_board-vivado_2017.4-build_09_20180517152103.zip

    John Hartfiel

    • new assembly variant

    2018-04-11

    2017.4

    TE0803-test_board_noprebuilt-vivado_2017.4-build_07_20180411081821.zip

    TE0803-test_board-vivado_2017.4-build_07_20180411081757.zip

    John Hartfiel

    • bugfix TE0803-01-04EG board part file

    2018-02-13

    2017.4

    TE0803-test_board_noprebuilt-vivado_2017.4-build_06_20180213120257.zip

    TE0803-test_board-vivado_2017.4-build_06_20180213120229.zip

    John Hartfiel

    • new assembly variant

    2018-02-05

    2017.4

    TE0803-test_board-vivado_2017.4-build_05_20180205101915.zip

    TE0803-test_board_noprebuilt-vivado_2017.4-build_05_20180205101943.zip

    John Hartfiel

    • new assembly variant

    2018-01-31

    2017.4

    TE0803-test_board-vivado_2017.4-build_05_20180131124202.zip

    TE0803-test_board_noprebuilt-vivado_2017.4-build_05_20180131124215.zip

    John Hartfiel

    • new assembly variant

    2018-01-18

    2017.4

    TE0803-test_board-vivado_2017.4-build_05_20180118160549.zip

    TE0803-test_board_noprebuilt-vivado_2017.4-build_05_20180118160604.zip

    John Hartfiel

    • rework Board Part Files

    2017-11-16

    2017.2

    TE0803-test_board-vivado_2017.2-build_05_20171116152716.zip

    TE0803-test_board_noprebuilt-vivado_2017.2-build_05_20171116154619.zip

    John Hartfiel

    • Update Board Part CSV File with new Flash assembly variants

    2017-11-14

    2017.2

    TE0803-test_board-vivado_2017.2-build_05_20171114090712.zip

    TE0803-test_board_noprebuilt-vivado_2017.2-build_05_20171114090725.zip

    John Hartfiel

    • Initial release

    Release Notes and Know Issues

    Page properties
    hiddentrue
    idComments
    Notes :
    • add known Design issues and general notes for the current revision
    • do not delete known issue, add fixed version time stamp if issue fixed
    Scroll Title
    anchorTable_KI
    title-alignmentcenter
    titleKnown Issues
    _2021.2-build_11_20220405100116.zipManuela Strücker
    • 2021.2 update
    2021-09-062020.2TE0803-test_board-vivado_2020.2-build_7_20210906104518.zip
    TE0803-test_board_noprebuilt-vivado_2020.2-build_7_20210906104536.zip    		Manuela Strücker
    • 2020.2 update
    • update document style

    2020-04-06

    2019.2

    TE0803-test_board-vivado_2019.2-build_9_20200406081019.zip

    TE0803-test_board_noprebuilt-vivado_2019.2-build_9_20200406081036.zip

    John Hartfiel

    • new assembly variants

    2020-03-25

    2019.2

    TE0803-test_board-vivado_2019.2-build_8_20200325082253.zip

    TE0803-test_board_noprebuilt-vivado_2019.2-build_8_20200325082311.zip

    John Hartfiel

    • script update

    2020-01-23

    2019-2

    TE0803-test_board-vivado_2019.2-build_3_20200123070036.zip

    TE0803-test_board_noprebuilt-vivado_2019.2-build_3_20200123070049.zip

    John Hartfiel

    • 2019.2 update

    • Vitis support

    • FSBL SI programming procedure update 

    2019-5-06

    2018.3

    TE0803-test_board_noprebuilt-vivado_2018.3-build_05_20190506161948.zip

    TE0803-test_board-vivado_2018.3-build_05_20190506161936.zip

    John Hartfiel

    • custom FSBL

    • new assembly variants

    2018-10-26

    2018.2

    TE0803-test_board_noprebuilt-vivado_2018.2-build_03_20181026141705.zip

    TE0803-test_board-vivado_2018.2-build_03_20181026141651.zip

    John Hartfiel

    • new assembly variant

    2018-08-14

    2018.2

    TE0803-test_board_noprebuilt-vivado_2018.2-build_02_20180814103119.zip

    TE0803-test_board-vivado_2018.2-build_02_20180814103105.zip

    John Hartfiel

    • new assembly variant

    2018-07-13

    2018.2

    TE0803-test_board_noprebuilt-vivado_2018.2-build_02_20180713085721.zip

    TE0803-test_board-vivado_2018.2-build_02_20180713085704.zip

    John Hartfiel

    • additional notes for FSBL generated with Win SDK

    • changed *.bif

    2018-05-17

    2017.4

    TE0803-test_board_noprebuilt-vivado_2017.4-build_09_20180517152118.zip

    TE0803-test_board-vivado_2017.4-build_09_20180517152103.zip

    John Hartfiel

    • new assembly variant

    2018-04-11

    2017.4

    TE0803-test_board_noprebuilt-vivado_2017.4-build_07_20180411081821.zip

    TE0803-test_board-vivado_2017.4-build_07_20180411081757.zip

    John Hartfiel

    • bugfix TE0803-01-04EG board part file

    2018-02-13

    2017.4

    TE0803-test_board_noprebuilt-vivado_2017.4-build_06_20180213120257.zip

    TE0803-test_board-vivado_2017.4-build_06_20180213120229.zip

    John Hartfiel

    • new assembly variant

    2018-02-05

    2017.4

    TE0803-test_board-vivado_2017.4-build_05_20180205101915.zip

    TE0803-test_board_noprebuilt-vivado_2017.4-build_05_20180205101943.zip

    John Hartfiel

    • new assembly variant

    2018-01-31

    2017.4

    TE0803-test_board-vivado_2017.4-build_05_20180131124202.zip

    TE0803-test_board_noprebuilt-vivado_2017.4-build_05_20180131124215.zip

    John Hartfiel

    • new assembly variant

    2018-01-18

    2017.4

    TE0803-test_board-vivado_2017.4-build_05_20180118160549.zip

    TE0803-test_board_noprebuilt-vivado_2017.4-build_05_20180118160604.zip

    John Hartfiel

    • rework Board Part Files

    2017-11-16

    2017.2

    TE0803-test_board-vivado_2017.2-build_05_20171116152716.zip

    TE0803-test_board_noprebuilt-vivado_2017.2-build_05_20171116154619.zip

    John Hartfiel

    • Update Board Part CSV File with new Flash assembly variants

    2017-11-14

    2017.2

    TE0803-test_board-vivado_2017.2-build_05_20171114090712.zip

    TE0803-test_board_noprebuilt-vivado_2017.2-build_05_20171114090725.zip

    John Hartfiel

    • Initial release



    Release Notes and Know Issues

    Page properties
    hiddentrue
    idComments
    Notes :
    • add known Design issues and general notes for the current revision
    • do not delete known issue, add fixed version time stamp if issue fixed


    Scroll Title
    anchorTable_KI
    title-alignmentcenter
    titleKnown Issues

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    IssuesDescriptionWorkaroundTo be fixed version
    Xilinx SoftwareIncompatibility of board files for ZynqMP with eMMC activated between 2021.2 and 2021.2.1 patch, see Xilinx Forum Requestuse corresponding board files for the Vivado versions--
    QSPI FlashFlash programming is not supported with boot mode QSPI or SD. If flash programming fails, configure device for JTAG boot mode and try again or
    use older Vivado Versions for programming. (Vivado 2020.2 or 2019.2)    		--


    Requirements

    Software

    Page properties
    hiddentrue
    idComments

    Notes :

    • list of software which was used to generate the design


    Scroll Title
    anchorTable_SW
    title-alignmentcenter
    titleSoftware

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    SoftwareVersionNote
    Vitis2023.2needed, Vivado is included into Vitis installation



    Hardware

    Page properties
    hiddentrue
    idComments

    Notes :

    • list of hardware which was used to generate the design
    • mark the module and carrier board, which was used tested with an *
    Basic description of TE Board Part Files is available on TE Board Part Files.

    Complete List is available on "<project folder>\board_files\*_board_files.csv"

    Design supports following modules:


    Expand
    titleExpand List
    Scroll Title
    anchorTable_HWM
    title-alignmentcenter
    titleHardware Modules

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    tableStylingconfluence
    sortEnabledtrue
    cellHighlightingtrue

    Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
    TE0803-01-02CG-1E2cg_2gbREV012GB64MBNANANA
    TE0803-01-02CG-1EA2cg_2gbREV012GB128MBNANANA
    TE0803-01-02EG-1E2eg_2gbREV012GB64MBNANANA
    TE0803-01-02EG-1EA2eg_2gbREV012GB128MBNANANA
    TE0803-01-03CG-1E3cg_2gbREV012GB64MBNANANA
    TE0803-01-03CG-1EA3cg_2gbREV012GB128MBNANANA
    TE0803-01-03EG-1E3eg_2gbREV012GB64MBNANANA
    TE0803-01-03EG-1EA3eg_2gbREV012GB128MBNANANA
    TE0803-01-04CG-1EA4cg_2gbREV012GB128MBNANANA
    TE0803-01-04CG-1EB4cg_2gbREV012GB256MBNANANA
    TE0803-01-04EG-1EA4eg_2gbREV012GB128MBNANANA
    TE0803-01-04EV-1E34ev_2gbREV012GB128MBNA1 mm connectorsNA
    TE0803-01-05EV-1EA5ev_2gbREV012GB128MBNANANA
    TE0803-01-05EV-1IA5ev_i_2gbREV012GB128MBNANANA
    TE0803-02-03EG-1EB3eg_4gbREV02|REV014GB128MBNANANA
    TE0803-02-04EG-1E34eg_4gbREV024GB128MBNA1 mm connectorsNA
    TE0803-02-04EV-1EA4ev_2gbREV02|REV012GB128MBNANANA
    TE0803-02-04EV-1E34ev_4gbREV024GB128MBNA1 mm connectorsNA
    TE0803-03-2AE11-A2cg_2gbREV032GB128MBNANANA
    TE0803-03-2BE11-A2eg_2gbREV032GB128MBNANANA
    TE0803-03-3AE11-A3cg_2gbREV032GB128MBNANANA
    TE0803-03-3AE11-AK3cg_2gbREV032GB128MBNANANA
    TE0803-03-3AE10-R3cg_0_2gbREV032GBNANANAPS MIO 3.3V, not compatible to trenz carrier
    TE0803-03-3BE11-A3eg_2gbREV032GB128MBNANANA
    TE0803-03-3BE21-A3eg_4gbREV034GB128MBNANANA
    TE0803-03-3BE31-A3eg_8gbREV038GB128MBNANAdual die ddr
    TE0803-03-3BI21-A3eg_i_4gbREV034GB128MBNANANA
    TE0803-03-3RI21-A3eg_li_4gbREV034GB128MBNANANA
    TE0803-03-4AE11-A4cg_2gbREV032GB128MBNANANA
    TE0803-03-4BE11-A4eg_2gbREV032GB128MBNANANA
    TE0803-03-4BE21-L4eg_4gbREV034GB128MBNA1 mm connectorsNA
    TE0803-03-4BI21-A4eg_i_4gbREV034GB128MBNANANA
    TE0803-03-4BI21-X4eg_i_4gbREV034GB128MBNANAU41 replaced with diode
    TE0803-03-4BI61-A4eg_8gbREV038GB128MBNANAdual die ddr
    TE0803-03-4BI61-X4eg_8gbREV038GB128MBNANAdual die ddr
    TE0803-03-4DE11-A4ev_2gbREV032GB128MBNANANA
    TE0803-03-4DE21-L4ev_4gbREV034GB128MBNA1 mm connectorsNA
    TE0803-03-4DE21-LZ4ev_4gbREV034GB128MBNA1 mm connectorsNA
    TE0803-03-4DI21-D4ev_i_4gbREV034GB128MBNA
    		NA
    TE0803-03-4DI21-L4ev_i_4gbREV034GB128MBNA1 mm connectorsNA
    TE0803-03-4GE11-A4eg_2_2gbREV03

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    IssuesDescriptionWorkaroundTo be fixed versionQSPI FlashFlash programming is not supported with boot mode QSPI or SD. If flash programming fails, configure device for JTAG boot mode and try again or
    use older Vivado Versions for programming. (Vivado 2020.2 or 2019.2)    --

    Requirements

    Software

    Page properties
    hiddentrue
    idComments

    Notes :

    • list of software which was used to generate the design
    Scroll Title
    anchorTable_SW
    title-alignmentcenter
    titleSoftware

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    SoftwareVersionNoteVitis2021.2needed, Vivado is included into Vitis installation

    Hardware

    Page properties
    hiddentrue
    idComments

    Notes :

    • list of hardware which was used to generate the design
    • mark the module and carrier board, which was used tested with an *
    Basic description of TE Board Part Files is available on TE Board Part Files.

    Complete List is available on "<project folder>\board_files\*_board_files.csv"

    Design supports following modules:

    REV01
    Scroll Title
    anchorTable_HWM
    title-alignmentcenter
    titleHardware Modules

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
    TE0803-01-02EG-1E2eg_2gbREV012GB64MBNANANA
    TE0803-01-02CG-1E2cg_2gbREV012GB64MBNANANA
    TE0803-01-03EG-1E3eg_2gbREV012GB64MBNANANA
    TE0803-01-03CG-1E3cg_2gbREV012GB64MBNANANA
    TE0803-01-02EG-1EA2eg_2gbREV012GB128MBNANANA
    TE0803-01-02CG-1EA2cg_2gbREV012GB128MBNANANA
    TE0803-01-03EG-1EA3eg_2gbREV012GB128MBNANANA
    TE0803-01-03CG-1EA3cg_2gb
    2GB128MBNANANA
    TE0803-
    02
    03-
    03EG
    4GE21-
    1EB
    L
    3eg
    4eg_2_4gb
    REV02|REV01
    REV034GB128MBNA
    NA
    1 mm connectorsNA
    TE0803-
    01
    03-
    04CG
    4GI11-
    1EA
    A
    4cg
    4eg_2i_2gb
    REV01
    REV032GB128MBNANANA
    TE0803-
    02
    03-
    04EV
    4GI21-
    1EA
    A
    4ev
    4eg_2i_
    2gb
    4gb
    REV02|REV01
    REV03
    2GB
    4GB128MBNANANA
    TE0803-
    01
    03-
    04EV
    5BE11-
    1E3
    A
    4ev
    5eg_2gb
    REV01
    REV032GB128MBNA
    1 mm connectors
    NANA
    TE0803-
    01
    03-
    04EG
    5DE11-
    1EA
    A
    4eg
    5ev_2gb
    REV01
    REV032GB128MBNANANA
    TE0803-
    01
    03-
    04CG
    5DI21-
    1EB
    A
    4cg
    5ev_i_
    2gb
    4gb
    REV01
    REV03
    2GB
    4GB
    256MB
    128MBNANANA
    TE0803-
    01
    03-
    05EV
    5DI24-
    1EA
    A5ev_i_
    2gb
    4gb
    REV01
    REV03
    2GB
    4GB
    128MB
    512MBNANANA
    TE0803-
    01
    03-
    05EV-1IA
    S0034ev
    5ev_i
    _2gb
    REV01
    REV032GB128MBNANA
    NA
    CAO: TE0803-03-4DE11-A
    TE0803-
    02
    03-
    04EV-1E3
    S005
    4ev
    4eg_
    4gb
    2gb
    REV02
    REV03
    4GB
    2GB128MBNA
    1 mm connectors
    NACAO: TE0803-03-4BI1?-A
    NA
    TE0803-
    02
    04-
    04EG
    2AE11-
    1E3
    A
    4eg
    2cg_
    4gb
    2gb
    REV02
    REV04
    4GB
    2GB128MBNA
    1 mm connectors
    NANA
    TE0803-
    03
    04-
    2AE11
    2BE11-A
    2cg
    2eg_2gb
    REV03
    REV042GB128MBNANANA
    TE0803-
    03
    04-2BE11-
    A
    AK2eg_2gb
    REV03
    REV042GB128MBNANANA
    TE0803-
    03
    04-
    3AE11
    3AE10-
    A
    R3cg_0_2gb
    REV03
    REV042GB
    128MB
    NANANA
    NA
    PS MIO 3.3V, not compatible to trenz carrier
    TE0803-
    03
    04-
    3BE11
    3AE11-A
    3eg
    3cg_2gb
    REV03
    REV042GB128MBNANANA
    TE0803-
    03
    04-
    4AE11
    3AE11-
    A
    AK
    4cg
    3cg_2gb
    REV03
    REV042GB128MBNANANA
    TE0803-
    03
    04-
    4BE11
    3BE11-A
    4eg
    3eg_2gb
    REV03
    REV042GB128MBNANANA
    TE0803-
    03
    04-
    4BE21
    3BE21-
    L
    A
    4eg
    3eg_4gb
    REV03
    REV044GB128MBNA
    1 mm connectors
    NANA
    TE0803-
    03
    04-
    4BI21
    3BE21-
    A
    L
    4eg
    3eg_
    i_
    4gb
    REV03
    REV044GB128MBNANANA
    TE0803-
    03
    04-
    4DE11
    4AE11-A
    4ev
    4cg_2gb
    REV03
    REV042GB128MBNANANA
    TE0803-
    03
    04-
    4DE21
    4AE11-
    L
    AK
    4ev
    4cg_
    4gb
    2gb
    REV03
    REV04
    4GB
    2GB128MBNA
    1 mm connectors
    NANA
    TE0803-
    03
    04-
    4GE21
    4AE11-
    L
    AZ
    4eg
    4cg_
    2_4gb
    2gb
    REV03
    REV04
    4GB
    2GB128MBNA
    1 mm connectors
    NANA
    TE0803-
    03
    04-
    5DE11
    4BE11-A
    5ev
    4eg_2gb
    REV03
    REV042GB128MBNANANA
    TE0803-
    03
    04-
    5DI21
    4BE11-
    A
    AK
    5ev
    4eg_
    i_4gb
    2gb
    REV03
    REV04
    4GB
    2GB128MBNANANA
    TE0803-
    03
    04-
    3RI21
    4BE21-
    A
    L
    3eg
    4eg_
    li_
    4gb
    REV03
    REV044GB128MBNA
    NA
    1 mm connectorsNA
    TE0803-
    03
    04-
    3BI21
    4BI21-A
    3eg
    4eg_i_4gb
    REV03
    REV044GB128MBNANANA
    TE0803-
    03
    04-
    4DI21
    4BI21-
    L
    X
    4ev
    4eg_i_4gb
    REV03
    REV044GB128MBNA
    1 mm connectors
    NAU41 replaced with diode
    NA
    TE0803-
    03
    04-
    4GI11
    4BI61-A4eg_
    2i_2gb
    8gb
    REV03
    REV04
    2GB
    8GB128MBNANA
    NA
    dual die ddr
    TE0803-
    03
    04-
    4GE11
    4BI61-
    A
    X4eg_
    2_2gb
    8gb
    REV03
    REV04
    2GB
    8GB128MBNANA
    NA
    dual die ddr
    TE0803-
    03
    04-
    4GI21
    4DE11-A
    4eg
    4ev_
    2i_4gb
    2gb
    REV03
    REV04
    4GB
    2GB128MBNANANA
    TE0803-
    03
    04-
    5BE11
    4DE11-
    A
    AK
    5eg
    4ev_2gb
    REV03
    REV042GB128MBNANANA
    TE0803-
    03
    04-
    5DI24
    4DE11-
    A
    AZ
    5ev
    4ev_
    i_4gb
    2gb
    REV03
    REV04
    4GB
    2GB
    512MB
    128MBNANANA
    TE0803-
    03
    04-
    4BI21
    4DE21-
    X
    L
    4eg_i
    4ev_4gb
    REV03
    REV044GB128MBNA1 mm connectorsNA
    U41 replaced with diode
    TE0803-
    03
    04-
    3BE21
    4DE21-
    A
    LZ
    3eg
    4ev_4gb
    REV03
    REV044GB128MBNA
    NA
    1 mm connectorsNA
    TE0803-
    03
    04-
    3BE31
    4DI21-
    A*3eg_8gbREV03
    D4ev_i_4gbREV044GB
    8GB
    128MBNA
    		NA
    dual die ddr
    TE0803-04-
    2AE11
    4DI21-
    A
    L
    2cg
    4ev_i_
    2gb
    4gbREV04
    2GB
    4GB128MBNA
    NA
    1 mm connectorsNA
    TE0803-04-
    2BE11
    4GE21-
    A
    L
    2eg
    4eg_2_
    2gb
    4gbREV04
    2GB
    4GB128MBNA
    NA
    1 mm connectorsNA
    TE0803-04-
    3AE11
    4GE81-
    A
    L
    3cg
    4eg_2_
    2gb
    4gbREV04
    2GB
    4GB128MBNA
    NA
    1 mm connectorsNA
    TE0803-04-
    3BE11
    4GI21-A
    3eg
    4eg_2i_
    2gb
    4gbREV04
    2GB
    4GB128MBNANANA
    TE0803-04-
    4BE21
    5BE11-
    L
    A
    4eg
    5eg_
    4gb
    2gbREV04
    4GB
    2GB128MBNA
    1 mm connectors
    NANA
    TE0803-04-
    4BI21
    5DE11-A
    4eg
    5ev_
    i_4gb
    2gbREV04
    4GB
    2GB128MBNANANA
    TE0803-04-
    4BI21
    5DI21-
    X
    A
    4eg
    5ev_i_4gbREV044GB128MBNANA
    U41 replaced with diode
    NA
    TE0803-
    03
    04-
    4BI61-A
    S006
    4eg
    4ev_
    8gb
    4gb
    REV03
    REV04
    8GB
    4GB128MBNA
    NA
    1 mm connectorsCAO: TE0803-04-4DE21-L
    dual die ddr
    TE0803-
    03
    04-
    4BI61-X
    S0094eg_
    8gb
    2_4gb
    REV03
    REV04
    8GB
    4GB128MBNA
    NA
    1 mm connectorsCAO: TE0803-04-4GE21-L
    dual die ddr
    TE0803-04-
    4BI61-A
    S010
    4eg
    5ev_
    8gb
    2gbREV04
    8GB
    2GB128MBNANA
    dual die ddr
    CAO: TE0803-04-5DE11-A
    TE0803-04-
    4BI61-X
    S0114eg_2_
    8gb
    4gbREV04
    8GB
    4GB
    128MB
    64MBNA
    NA
    1 mm connectorsCAO: TE0803-04-4GE25-L
    dual die ddr
    TE0803-04-
    4DE11-A
    S012
    4ev
    2cg_2gbREV042GB128MBNANANA
    TE0803-04-
    4DE21-L
    S013
    4ev
    3cg_
    4gb
    2gbREV04
    4GB
    2GB128MBNA
    1 mm connectors
    NANA
    TE0803-04-
    4DI21-L
    S014
    4ev
    4eg_
    i
    2_4gbREV044GB
    128MB
    64MBNA1 mm connectors
    NA
    CAO: TE0803-
    03
    04-
    4DI21
    4GE2?-
    D4ev_i_4gbREV034GB128MBNANA
    LZ
    TE0803-04-
    4DI21-D
    S016
    4ev
    4cg_
    i_4gb
    2gbREV04
    4GB
    2GB128MBNANANA
    TE0803-04-
    4GE21-L
    S017
    4eg
    2eg_
    2_4gb
    2gbREV04
    4GB
    2GB128MBNA
    1 mm connectors
    NANA
    TE0803-04-
    4GI21-A
    S0184eg_
    2i
    2_4gbREV044GB128MBNA
    NA
    1 mm connectorsNA
    TE0803-04-
    5BE11-A
    S020
    5eg
    4cg_2gbREV042GB128MBNANANA
    TE0803-04-
    5DE11-A5ev_2gb
    S0224eg_2_4gbREV04
    2GB
    4GB128MBNA
    NA
    1 mm connectorsCAO: TE0803-04-4GE21-LZ
    NA
    TE0803-04-
    5DI21-A
    S023
    5ev
    4eg_
    i
    2_4gbREV044GB128MBNA
    NA
    1 mm connectorsCAO: TE0803-04-4GE81-L
    NA
    TE0803-
    03
    04-
    S003
    S026
    4ev
    5ev_i_
    2gb
    4gbREV04
    2GB
    4GB128MBNANACAO: TE0803-04-5DI21-A
    TE0803-
    03
    04-
    S006
    S027
    4ev
    3cg_
    4gb
    2gbREV04
    4GB
    2GB128MBNANA
    1 mm connectorsCAO
    CAO:TE0803-04-3AE11-A

    *used as reference


    Note: Design contains also Board Part Files for TE0803+TEBF0808 configuration, this board part files are not used for this reference design.

    Design supports following carriers:

    Scroll Title
    anchorTable_HWC
    title-alignmentcenter
    titleHardware Carrier

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Carrier Model

    Notes

    Custom PCB

    use simple Board Part files, if MIO connected is different to TEBF0808

    TEBF0808*

    Used as reference carrier. Important: CPLD Firmware REV07 or newer is recommended

    TEBT0808-01

    Change UART0 to UART1 (MIO68...69) and regenerate design

    *used as reference

    Additional HW Requirements:

    Scroll Title
    anchorTable_AHW
    title-alignmentcenter
    titleAdditional Hardware

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Additional Hardware

    Notes

    ---

    ---

    *used as reference

    Content

    Page properties
    hiddentrue
    idComments

    Notes :

    • content of the zip file

    For general structure and usage of the reference design, see Project Delivery - Xilinx AMD devices

    Design Sources

    Scroll Title
    anchorTable_DS
    title-alignmentcenter
    titleDesign sources

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    TypeLocationNotes
    Vivado<project folder>\block_design
    <project folder>\constraints
    <project folder>\ip_lib
    <project folder>\board_files    		Vivado Project will be generated by TE Scripts
    Vitis<project folder>\sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation



    Additional Sources

    Scroll Title
    anchorTable_ADS
    title-alignmentcenter
    titleAdditional design sources

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Type

    Location

    Notes

    ---

    ---

    ---


    Prebuilt

    Page properties
    hiddentrue
    idComments

    Notes :

    • prebuilt files
    • Template Table:


      • Scroll Title
        anchorTable_PF
        title-alignmentcenter
        titlePrebuilt files

        Scroll Table Layout
        orientationportrait
        sortDirectionASC
        repeatTableHeadersdefault
        sortByColumn1
        sortEnabledfalse
        cellHighlightingtrue

        File

        File-Extension

        Description

        BIF-File*.bifFile with description to generate Bin-File
        BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
        BIT-File*.bitFPGA (PL Part) Configuration File
        Boot Script-File*.scr

        Distro Boot Script file

        DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

        Debian SD-Image

        *.img

        Debian Image for SD-Card

        Diverse Reports---Report files in different formats
        Device Tree*.dtsDevice tree (2 possible, one for u-boot and one for linux)
        Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
        LabTools Project-File*.lprVivado Labtools Project File

        MCS-File

        *.mcs

        Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

        MMI-File

        *.mmi

        File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

        OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
        Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

        SREC-File

        *.srec

        Converted Software Application for MicroBlaze Processor Systems





    Scroll Title
    anchorTable_PF
    title-alignmentcenter
    titlePrebuilt files (only on ZIP with prebult content)

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    File

    File-Extension

    Description

    BIF-File

    *.bif

    File with description to generate Bin-File

    BIN-File

    *.bin

    Flash Configuration File with Boot-Image (Zynq-FPGAs)

    BIT-File

    *.bit

    FPGA (PL Part) Configuration File

    Diverse Reports

    ---

    Report files in different formats

    Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux

    LabTools Project-File

    *.lpr

    Vivado Labtools Project File

    Software-Application-File

    *.elf

    Software Application for Zynq or MicroBlaze Processor Systems


    Download

    Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

    Page properties
    hiddentrue
    idComments

    Reference Design is available on:

    Design Flow

    Scroll Ignore
    scroll-pdftrue
    scroll-officetrue
    scroll-chmtrue
    scroll-docbooktrue
    scroll-eclipsehelptrue
    scroll-epubtrue
    scroll-htmltrue


    Page properties
    hiddentrue
    idComments

    Notes :

    • Basic Design Steps

    • Add/ Remove project specific description


    Note

    Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

    Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

    See also:

    The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

    TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

    Note

    Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")


    1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

      Code Block
      languagebash
      themeMidnight
      title_create_win_setup.cmd/_create_linux_setup.sh
      ------------------------Set design paths----------------------------
-- Run Design with: _create_win_setup
-- Use Design Path: <absolute project path>
--------------------------------------------------------------------
-------------------------TE Reference Design---------------------------
--------------------------------------------------------------------
-- (0)  Module selection guide, project creation...prebuilt export...
-- (1)  Create minimum setup of CMD-Files and exit Batch
-- (2)  Create maximum setup of CMD-Files and exit Batch
-- (3)  (internal only) Dev
-- (4)  (internal only) Prod
-- (c)  Go to CMD-File Generation (Manual setup)
-- (d)  Go to Documentation (Web Documentation)
-- (g)  Install Board Files from Xilinx Board Store (beta)
-- (a)  Start design with unsupported Vivado Version (beta)
-- (x)  Exit Batch (nothing is done!)
----
Select (ex.:'0' for module selection guide):


    2. Press 0 and enter to start "Module Selection Guide"

    3. Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.

      • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

        Note

        Note: Select correct one, see also Vivado Board Part Flow

        Important: Use Board Part Files, which did not ends with *_tebf0808


    4. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

      Code Block
      languagepy
      themeMidnight
      titlerun on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
      TE::hw_build_design -export_prebuilt


      Info

      Using Vivado GUI is the same, except file export to prebuilt folder.


    5. Generate Programming Files with Vitis

      Code Block
      languagepy
      themeMidnight
      titlerun on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
      TE::sw_run_vitis -all
TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)


      Note

      TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis


    Launch

    Scroll Ignore
    scroll-pdftrue
    scroll-officetrue
    scroll-chmtrue
    scroll-docbooktrue
    scroll-eclipsehelptrue
    scroll-epubtrue
    scroll-htmltrue


    Page properties
    hiddentrue
    idComments

    Note:

    • Programming and Startup procedure

    Programming

    Note

    Check Module and Carrier TRMs for proper HW configuration before you try any design.

    Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

    Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

    Get prebuilt boot binaries

    1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
    2. Press 0 and enter to start "Module Selection Guide"
      1. Select assembly version
      2. Validate selection

      3. Select create and open delivery binary folder

        Info

        Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated


    QSPI-Boot mode

    1. Connect JTAG and power on carrier with module

    2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

      Code Block
      languagepy
      themeMidnight
      titlerun on Vivado TCL (Script programs BOOT.bin on QSPI flash)
      TE::pr_program_flash -swapp hello_te0803


    SD-Boot mode

    This does not work, because SD controller is not selected on PS.

    JTAG

    Load configuration and Application with Vitis Debugger into device

    Usage

    QSPI Boot:

    1. Prepare HW like described on section Programming

    2. Connect UART USB (most cases same as JTAG)

    3. Select QSPI as Boot Mode

      Info

      Note: See TRM of the Carrier, which is used.


    4. Power On PCB

      Expand
      titleboot process

      1. ZynqMP Boot ROM loads FSBL from QSPI into OCM,

      2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from QSPI into DDR,


    System Design - Vivado

    Scroll Ignore
    scroll-pdftrue
    scroll-officetrue
    scroll-chmtrue
    scroll-docbooktrue
    scroll-eclipsehelptrue
    scroll-epubtrue
    scroll-htmltrue


    Page properties
    hiddentrue
    idComments

    Note:

    • Description of Block Design, Constrains... BD Pictures from Export...

    Block Design

    Scroll Title
    anchorFigure_BD
    title-alignmentcenter
    titleBlock Design


    PS Interfaces

    Page properties
    hiddentrue
    idComments

    Note:

    • optional for Zynq / ZynqMP only

    • add basic PS configuration

    Activated interfaces:

    Scroll Title
    anchorTable_PSI
    title-alignmentcenter
    titlePS Interfaces

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Type

    Note

    DDR


    QSPI

    MIO

    UART0

    MIO, please select other one, if you have connected UART to second controller or other MIO

    SWDT0..1


    TTC0..3



    Constrains

    Basic module constrains

    Code Block
    languageruby
    title_i_bitgen.xdc
    set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

    Design specific constrain

    Not needed.

    Software Design - Vitis

    Scroll Ignore
    scroll-pdftrue
    scroll-officetrue
    scroll-chmtrue
    scroll-docbooktrue
    scroll-eclipsehelptrue
    scroll-epubtrue
    scroll-htmltrue


    Page properties
    hiddentrue
    idComments

    Note:

    • optional chapter separate

    • sections for different apps

    For Vitis project creation, follow instructions from:

    Vitis

    Application

    instructions from:

    Vitis


    Application

    Page properties
    hiddentrue
    idComments
    Page properties
    hiddentrue
    idComments

    ----------------------------------------------------------

    FPGA Example

    ----------------------------------------------------------

    FPGA Example

    scu

    MCS Firmware to configure SI5338 and Reset System.

    srec_spi_bootloader

    TE modified 20212023.2 SREC

    Bootloader to load app or second bootloader from flash into DDR

    Descriptions:

    • Modified Files: blconfig.h, bootloader.c
    • Changes:
      • Add some console outputs and changed bootloader read address.
      • Add bugfix for 2018.2 qspi flash

    xilisf_v5_11

    TE modified 20212023.2 xilisf_v5_11

    • Changed default Flash type to 5.

    ----------------------------------------------------------

    Zynq Example:Example:

    ----------------------------------------------------------

    fsbl

    TE modified 20212023.2 FSBL

    General:

    • Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)

    • Add Files: te_fsbl_hooks.h/.c (for hooks and board)

    • General Changes: 
      • Display FSBL Banner and Device ID

    Module Specific:

    • Add Files: all TE Files start with te_*
      • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
      • CPLD access
      • Read CPLD Firmware and SoC Type
      • Configure Marvell PHY

    fsbl_flash

    TE modified 2021.2 FSBL

    General:

  • Modified Files: main.c
    • General Changes:
  • Display FSBL Banner
  • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation


    ----------------------------------------------------------

    ZynqMP Example:

    ----------------------------------------------------------

    zynqmp_fsbl

    TE modified 20212023.2 FSBL

    General:

    • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
    • Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
    • General Changes: 
      • Display FSBL Banner and Device Name

    Module Specific:

    • Add Files: all TE Files start with te_*
      • Si5338 Configuration
      • ETH+OTG Reset over MIO

    zynqmp_

    fsbl_flash

    pmufw

    Xilinx default PMU firmware.

    ----------------------------------------------------------

    General Example:

    TE modified 2021.2 FSBL

    General:

    • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
    • General Changes:
      • Display FSBL Banner
      • Set FSBL Boot Mode to JTAG
      • Disable Memory initialisation

    zynqmp_pmufw

    Xilinx default PMU firmware.

    ----------------------------------------------------------General Example:

    hello_te0820

    Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

    u-boot

    U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

    Template location: "<project folder>\sw_lib\sw_apps\"

    zynqmp_fsbl

    TE modified 20212023.2 FSBL

    General:

    • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
    • Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
    • General Changes: 
      • Display FSBL Banner and Device Name

    zynqmp_fsbl_flash

    TE modified 2021.2 FSBL

    General:

    • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c.c (for hooks and board)
    • General Changes: 
      • Display FSBL Banner
      • Set FSBL Boot Mode to JTAG
      • Disable Memory initialisation
      • and Device Name

    hello_te0803

    Hello TE0803 is a Xilinx Hello World example as endless loop instead of one console output.

    Additional Software

    Scroll Ignore
    scroll-pdftrue
    scroll-officetrue
    scroll-chmtrue
    scroll-docbooktrue
    scroll-eclipsehelptrue
    scroll-epubtrue
    scroll-htmltrue


    Page properties
    hiddentrue
    idComments

    Note:

    • Add description for other Software, for example SI CLK Builder ...

    • SI5338 and SI5345 also Link to:

    No additional software is needed.

    Appx. A: Change History and Legal Notices

    Scroll Ignore
    scroll-pdftrue
    scroll-officetrue
    scroll-chmtrue
    scroll-docbooktrue
    scroll-eclipsehelptrue
    scroll-epubtrue
    scroll-htmltrue

    Document Change History

    To get content of older revision go to "Change History" of this page and select older document revision number.

    Page properties
    hiddentrue
    idComments
    • Note this list must be only updated, if the document is online on public doc!
    • It's semi automatically, so do following

      • Add new row below first

      • Copy "Page Information Macro (date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

      • Metadata is only used of compatibility of older exports

    Scroll Title
    anchorTable_dch
    title-alignmentcenter
    titleDocument change history.

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    widths2*,*,3*,4*
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Date

    Document Revision

    Authors

    Description

    Page info
    modified-date
    modified-date
    dateFormatyyyy-MM-dd

    Page info
    infoTypeCurrent version
    dateFormatyyyy-MM-dd
    prefixv.
    typeFlat

    Page info
    infoTypeModified by
    typeFlat

    • Release 2023.2
    • new assembly variants

    2023-09-14

    v.34

    Manuela Strücker

    • Release 2023.2
    • new assembly variants
    2022-10-17v.33Manuela Strücker
    • script update
    2022-09-06v.32Manuela Strücker
    • new assembly variants
    2022-07-15v.30Manuela Strücker
    • Release 2021.2
    2021-09-09v.25Manuela Strücker
    • Release 2020.2
    2020-04-06v.24John Hartfiel
    • new assembly variants

    2020-03-25

    v.23

    John Hartfiel

    • Script update

    2020-01-23

    v.22

    John Hartfiel

    • Release 2019.2

    2019-05-07

    v.21

    John Hartfiel

    • Release 2018.3

    2018-10-26

    v.18

    John Hartfiel

    • new assembly variant

    2018-08-14

    v.16

    John Hartfiel

    • new assembly variant

    2018-07-13

    v.15

    John Hartfiel

    • Release 2018.2

    2018-05-18

    v.14

    John Hartfiel

    • new assembly variant

    2018-04-11

    v.13

    John Hartfiel

    • bugfix board part file

    2018-04-03

    v.11

    John Hartfiel

    • new assembly variant

    2018-01-18

    v.6

    John Hartfiel

    • Release 2017.4

    2017-11-16

    v.4

    John Hartfiel

    • Update assembly versions with new Flash size

    2017-11-14

    v.3

    John Hartfiel

    • Release 2017.2


    All

    Page info
    modified-users
    modified-users




    Legal Notices

    Include Page
    IN:Legal Notices
    IN:Legal Notices




    Scroll Only


    HTML
    <style>
.wiki-content .columnLayout .cell.aside {
width: 0%;
}</style>



    Scroll pdf ignore


    Custom_fix_page_content

    Table of contents

    Table of Contents
    outlinetrue