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Trenz Electronic TE0728 is an automotive-grade FPGA module integrating an Automotive Xilinx  Zynq-7 FPGA, two 100 Mbit Ethernet transceivers (PHY) , DDR3L SDRAMDDR3 SDRAM, QSPI Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. 

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• Xilinx
XA7Z020
• XC7Z020-1CLG484Q (Automotive) [XA7Z014S is available on other assembly options]
  • Rugged for shock and high vibration
  • Dimensions: 6 x 6 cm
  Temperature range: Automotive
  • • Package: CL/CLG484
    • Speed Grade: -1
    • Temperature Grade: Expanded (-40 to +128 °C)
      
  • Dual-Core ARM Cortex-A9 MPCore
    
  • 2 x 100 MBit Ethernet transceiver (PHY)
  DDR3L SDRAM, 16-bit-width [different size is
  • DDR3 SDRAM, up to 512MB, up to 1066 Mb/s, connected to PS  [different size is available on other assembly options]
  • QSPI Flash memory (with XiP support) [different size is available on other assembly options]
  • Programmable SIT8918A , PS clock generator
  • 2 Kbit serial EEPROM
  • Three user LEDs
  • CAN transceiver (PHY)
  • Temperature compensated RTC (real-time clock)
  • 2 x 100 MBit Ethernet transceiver (PHY)
  • Board to Board (B2B)
    • Plug-on module with 3 x 80-pin Samtec Micro Tiger Eye(TM) high-speed connectors
  76 single ended
  • I/O
  , 24 LVDS pairs (48 I/O) and 42 MIO available on board-to-board connectorsCAN transceiver (PHY)
  • Interface
    • 42x MIO
    • 200x HR
    • 128x PS IO
    • 0x GTP Transceiver
    • 0x GTX Transceiver
  • Power Supply
    • 12 V power supply with watchdog
  • Others:
    • Dimensions: 6 x 6 cm
    • Rugged for shock and high vibration
    • On-board high-efficiency DC-DC converters
    • System management and power sequencing
    • eFUSE bit-stream encryption
    • AES bit-stream encryption
  • Temperature compensated RTC (real-time clock)
  • Three user LEDs
  • • Evenly-spread supply pins for good signal integrity
      

  Depending on the customer design, additional cooling might be required.

  • • 
      

  Block Diagram

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  anchor Figure_OV_BD title TE0728 block diagram
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  Main Components

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  Notes : |Picture of the PCB (top and bottom side) with labels of important components Add List below

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  1. DDR3 SDRAM, U1
  2. Xilinx Automotive XA7Z020-1CLG484Q ,U2
  3. 100 MBit Ethernet transceiver, U3
  4. 100 MBit Ethernet transceiver, U10
  5. User LED Green, D4
  6. Real Time Clock, U7
  7. Standard Clock Oscillators, U5
  8. 64 Kbit I2C EEPROM, U11
  9. CAN Tranceiver, U16
  10. QSPI NOR Flash memory, U13
  11. Standard Clock Oscillators, U14
  12. Low-Quiescent-Current Programmable Delay Supervisory Circuit, U15
  13. Low-Quiescent-Current Programmable Delay Supervisory Circuit, U12
  14. B2B connector , JM2
  15. B2B connector , JM3
  16. B2B connector , JM1

  FPGA (U2), DDR3 SDRAM (U1) and QSPI (U13) can be  varied on other assembly option, for more information contact us. 

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  Scroll Title
  anchor Table_OV_IDS title Initial delivery state of programmable devices on the module
  Scroll Table Layout widths orientation portrait sortDirection ASC repeatTableHeaders default style sortByColumn 1 sortEnabled false cellHighlighting true Storage Device Symbol Content Quad SPI Flash U13 Not Programmed EEPROM U11 Not Programmed

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  Overview of Boot Mode, Reset, Enables,

  Boot Mode

  
  

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  anchor Table_OV_BP title Boot process.
  Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Signal FPGA Bank Pin B2B Signal State Boot Mode Boot_R 500 E4 J2-11 Low QSPI High SD Card

  
  

  Scroll Title
  anchor Table_OV_RST title Reset process.

  Zynq-7020SoC  includes a reset that is driven by the reset system. Hardware resets are driven by the power-on reset signal (Reset) connected to carrier and the system reset signal (PS_SRST_B)  connected to VMIO, it means after power on the PS will be reset.

  Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default sortByColumn 1 sortEnabled false cellHighlighting true Signal
  Scroll Title
  anchor Table_OV_RST title Reset process.
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  orientation	portrait
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  cellHighlighting	true

  Signal	B2B	I/O	Note
  Reset	J2-7	Input	Comes from Carrier
  RST_OUT	J2-9	Output	PS_PROB_B