SPI/S | CSO_B of Spartan3Spartan-3 Output | PD4 Output when
the FPGA is
powerd off by
spi functions (1) | Master SPI Chip Select Output
Active Low.
Connect to the SPI Flash PROM’s
Slave Select input. Chip select: When the S# input
signal is HIGH, the device is deselected
and DQ1 is at HIGH impedance.
Unless an internal PROGRAM, ERASE,
or WRITE STATUS REGISTER cycle
is in progress, the device will be in
the standby power mode (not the
DEEP POWERDOWN mode).
Driving S# LOW enables the device,
placing it in the active power mode.
After power-up, a falling edge on S#
is required prior to the start of any
command. | If HSWAP
or PUDC_B =1, connect this signal
to a 4.7 kΩ pull-up resistor
to 3.3V. | Drive CSO_B High after configuration to disable the SPI Flash and reclaim the MOSI, DIN, and CCLK pins. Optionally, re-use this pin and MOSI, DIN, and CCLK to continue communicating with SPI Flash. |
| SPI/C | CCLK Output | PD5 Output when
the FPGA is
powerd off by
spi functions (1) | Configuration Clock. Generated by
FPGA internal oscillator.
Connect to the SPI Flash PROM’s
Slave Clock input.
Frequency controlled by ConfigRate
bitstream generator option.
If CCLK PCB trace is long or has
multiple connections, terminate this
output to maintain signal integrity. Clock: The C input signal provides the
timing of the serial interface.
Commands, addresses, or data present
at serial data input (DQ0) is latched on
the rising edge of the serial clock (C).
Data on DQ1 changes after the falling
edge of C. | Drives SPI Flash
PROM’s clock input. | User I/O. Drive High or Low if not used. |
| SPI_D | MOSI Output | PD6 Output when
the FPGA is
powerd off by
spi functions (1) | Master SPI Serial Data Output Connect
to the SPI Flash PROM’s Slave
Data Input pin. Serial data: The DQ0 input signal is
used to transfer data serially into the
SPI Flash device.
It receives commands, addresses,
and the data to be programmed.
Values are latched on the rising edge
of the serial clock (C). | FPGA sends
SPI Flash memory
read commands and starting address
to the PROM’s
serial data input. | User I/O |
SPI_Q | DIN Input | PD7 Input, by default (2) | Master SPI Serial Data Input Connect
to the SPI Flash PROM’s Slave Data
Output pin. Serial data: The DQ1 output signal is
used to transfer data serially out of the
SPI Flash device.
Data is shifted out on the falling edge
of the serial clock (C). | FPGA receives serial
data from SPI Falsh
PROM’s serial data
output. | User I/O |