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The Trenz Electronic TE0802 is an evalution modulea development board integrating a Xilinx Zynq UltraScale+ . Other assymbly assembly options for the FPGA and the memory chips are available. Please ask contact us for further information.
Refer to http://trenz.org/te0802-info for the current online version of this manual and other available documentation.
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Note:
'Key Features' description: Important components and connector or other Features of the module
→ please sort and indicate assembly options |
- MPSoC: Xilinx Zynq XCZU2CG-1SBVA484E XCZU2CG - Xilinx Zynq UltraScale+ MPSoC
- RAM/Storages:-3733 256Mx32Storages:
- SPI Flash 256Mb (32M x 8) 133 MHz
- microSD Card
- M.2 SSD PCIe
- EEPROMs 2Kb (256 x 8)
- EEPROMs 4Kb (512 x 8)
- Display Interfaces:
- DisplayPort
- VGA
- 4 Digit 7-Segment LED Display
- 8 LEDs
Audio:- USB JTAG/UART microUSB
- 1GB Ethernet RJ45
- USB 3.0 Host (Type A Connector)
- microSD Card
- M.2 SSD PCIe
- 3.5 mm Earphone Jack (PWM Output)
Input:- Display Port
- VGA
- 4 Digit 7-Segment LED Display
- 8 LEDs
- 5 User Buttons
- 8 Bit Slide Switches
- Reset Button
User I/O:Communication:
- 1GB Ethernet RJ45
- USB 3.0 Host (Type A Connector)
Debug - Power
- Dimension: 100mm x 100mm
Block Diagram
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add drawIO object here.
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| anchor | Figure_OV_BD |
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| title | TE0802 Block Diagram |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| fitWindow | false |
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| diagramDisplayName | |
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| lbox | true |
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| revision | 4 |
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| diagramName | TEMPTE0802_OV_BD |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| diagramWidth | 638 |
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| Scroll Only |
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 Image Added Image Removed
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Main Components
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| Scroll Title |
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| anchor | Table_OV_IDS |
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| title | Initial Delivery State of Programmable Devices on the Module |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Storage device name | Content | Notes |
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SPI Flash (U16) | Not programmed |
| | EEPROM (U2) | Not programmed | Except Ethernet MAC | | EEPROM (U18) | Programmed | FTDI Configuration | | LPDDR4 SDRAM (U13) | Not programmed |
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Configuration Signals
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- Overview of Boot Mode, Reset, Enables.
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Bootmode signals must be set through DIP Switch S1.
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| Scroll Title |
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| anchor | Table_OV_BP |
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| title | Boot Process |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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MODE01MODE12100b101b-110b010 | ON | OFF | QSPI(32 bit) | MODE[ |
111b
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Reset setting is available through Push Button BTN6.
| Scroll Title |
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| anchor | Table_OV_RST |
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| title | Reset Process |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Signal | Connected to | Note |
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POR_B | BTN6, Push Button | Connected to nRESET |
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Signals, Interfaces and Pins
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| anchor | Table_SIP_B2B |
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| title | General I/O to Pin Header and Connectors Information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| FPGA Bank | Connector | I/O Signal Count | Voltage Level | Notes |
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| Bank 503 |
J8Micro USB| over FTDI) | 4 Single Ended | 3.3 V | JTAG | | Bank 500 |
J8Micro USB| over FTDI) | 2 Single Ended | 3.3 V | UART | | Bank 500 |
J9, ()| , J9 | 7 Single Ended | 3.3 V |
| | Bank 502 | ETH RJ45, J4 |
, RJ45| over ETH PHY) | 14 Single Ended | 1.8 V |
| | Bank 505, 502 |
J11, (| USB 3.0, J11 (USB2 over USB PHY) | 2 Differential Pairs |
0.85 V| , 12 Single Ended | -- / 1.8V |
| Bank 505, 501 |
U5, ()0.85 V | Bank 501 | U5 (SSD M.2) 5 Single Ended | -- / 3.3 V |
| | Bank 505, 501 |
J3, ()0.85 V | Bank 26 | J7, (D-Sub Host Socket) | 2 | , 5 Single Ended | --/ 3.3 V |
| | Bank 26, 65, 66, |
J7, (| D-Sub Host Socket (VGA), J7 |
12 | 14 Single Ended | 3.3 V / 1.8 V / 1.8 V |
| | Bank 65 | Earphone, J12 |
, Headphone | 3 Single Ended | 1.8 V |
| | Bank 500 |
J10, ()| , J10 | 2 Single Ended | 3.3 V |
| | Bank 26 |
J5 ()| , J5 | 8 Single Ended | 3.3 V |
| | Bank 26 |
J6 () |
Micro USB 2.0
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Micro SD Card
TEI0802 TE0802 is equipped with a micro SD card connector (J9).
| Scroll Title |
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| anchor | Table_SIP_SD |
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| title | Micro SD Card Connector Information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Schematic | Connected to | Notes |
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| SD_DAT0 | MIO 13, FPGA Bank 500 |
| | SD_DAT1 | MIO 14, FPGA Bank 500 |
| | SD_DAT2 | MIO 15, FPGA Bank 500 |
| | SD_DAT3 | MIO 16, FPGA Bank 500 |
| | SD_CLK | MIO 22, FPGA Bank 500 |
| | SD_CMD | MIO 21, FPGA Bank 500 |
| | SD_CD | MIO 24, FPGA Bank 500 |
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RJ45 Connector
TEI0802 TE0802 is equipped with a RJ45 connector and an Ethernet PHYs. RJ45 connectors connector J4 is connected to Ethernet PHYs U6.
| Scroll Title |
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| anchor | Table_SIP_RJ45 |
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| title | RJ45 Connector Information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Pin | Schematic | ETH Pin | Notes |
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| 2 | PHY_MDI0_P | MDIP[0] |
| | 3 | PHY_MDI0_N | MDIN[0] |
| | 4 | PHY_MDI1_P | MDIP[1] |
| | 5 | PHY_MDI1_N | MDIN[1] |
| | 6 | PHY_MDI2_P | MDIP[2] |
| | 7 | PHY_MDI2_N | MDIN[2] |
| | 8 | PHY_MDI3_P | MDIP[3] |
| | 9 | PHY_MDI3_N | MDIN[3] |
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USBs Sockets
TEI0802 TE0802 is equipped with a USB connector (J11).Micro USB2.0 B connector J8 and a USB3.0 connector J11.
FTDI FT2232 (U17) can be accessed through Micro USB 2.0 B connector (J8) for JTAG (channel A). Channel B is connected to the FPGA and can be used for UART.
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| Scroll Title |
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| anchor | Table_SIP_USBUSB2 |
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| title | USB USB2.0 B Socket Information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Corresponding SignalsUSB0_| USB0_DATA0...7 | MIO 52...63 FPGA Bank 502USB0_USB0_DATA0...7 | MIO 52...63 FPGA Bank 502 |
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| anchor | Table_SIP_USB3 |
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| title | USB3.0 A Socket Information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| USB3.0 Pin | Schematic | Connected to | Notes |
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| D- | USB0_D_N | USB PHY, U22 |
| | D+ | USB0_D_P | USB PHY, U22 |
| | StdA_ |
StdA_- | FPGA Bank 505 |
| | StdA_SSRX+ | USB_RX2_P |
- | U3D2_N | | USB_TX2_N | FPGA Bank 505 |
| | StdA_SSTX+ |
U3D2_P | | USB_TX2_P | FPGA Bank 505 |
| | VBUS | VBUS | USB PHY, U22 |
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SSD M.2 Connector
TEI0802 TE0802 is equipped with a SSD M.2 connector (U5).
| Scroll Title |
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| anchor | Table_SIP_SSD |
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| title | SSD M.2 Connector Information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Pin | Schematic | Connected to | Notes |
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| PERn0/SATA-B+ | SSD_RX3_N | Pin M22, FPGA Bank 505 |
| | PERp0/SATA-B- | SSD_RX3_P | Pin M21, FPGA Bank 505 |
| | PERn0/SATA-A+ | SSD_TXC3_N | Pin K22, FPGA Bank 505 |
| | PERp0/SATA-A- | SSD_TXC3_P | Pin M21, FPGA Bank 505 |
| | REFCLKN | SSD_RCLK_N | Pin 9, Clock Generator U8 |
| | REFCLKP | SSD_RCLK_P | Pin 10, Clock Generator U8 |
| | DAS/DSS# | SSD_DAS | MIO35, FPGA Bank 501 |
| | DEVSLP | SSD_SLEEP | MIO32, FPGA Bank 501 |
| | PERST# | SSD_PERSTn | MIO31, FPGA Bank 501 |
| | CLKREQ# | SSD_CLKRQ | MIO33, FPGA Bank 501 |
| | PEWake# | SSD_WAKE | MIO34, FPGA Bank 501 |
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Display Port Connector
TEI0802 TE0802 is equipped with a Display Port connector (J3).
| Scroll Title |
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| anchor | Table_SIP_DP |
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| title | Display Port Socket Information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Schematic | Corresponding Signals | Connected to | Notes |
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| DP_TX_L0_P/N | DP0_TX_P/N | Pin A19/A20, FPGA Bank 505 |
| | DP_TX_L1_P/N | DP1_TX_P/N | Pin C19/C20, FPGA Bank 505 |
| | DP_TX_AUX_P/N | DP_AUX_TX/RX | MIO27, MIO30, FPGA Bank 501 |
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D-Sub Connector
TEI0802 TE0802 is equipped with a D-Sub connector (J7).
| Scroll Title |
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| anchor | Table_SIP_VGA |
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| title | D-Sub Connector Information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Schematic | Corresponding Signals | Connected to | Notes |
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| VGA_RED | VGA_R0...3 | Bank 65 | Red Channel | | VGA_GREEN | VGA_G0...3 | Bank 65 | Green Channel | | VGA_BLUE | VGA_B0...3 | Bank 66 | Blue Channel | | VGA_RGB_HSYNC | VGA_HS | Bank 26 | Horizontal Sync | | VGA_RGB_VSYNC | VGA_VS | Bank 26 | Vertical Sync |
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Headphone Connector
TEI0802 TE0802 is equipped with a headphone connector (J12).
| Scroll Title |
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| anchor | Table_SIP_HP |
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| title | Headphone Connector Information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Schematic | Connected to | Notes |
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| JACKSNS | Pin F3, FPGA Bank 65 |
| | PWM_R | Pin F4, FPGA Bank 65 |
| | PWM_L | Pin E3, FPGA Bank 65 |
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Grove Connector
TEI0802 TE0802 is equipped with a grove connector (J10).
| Scroll Title |
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| anchor | Table_SIP_Grove |
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| title | Grove Connector Information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Schematic | Connected to | Notes |
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| Grove_SCL0 | MIO18, FPGA Bank 500 |
| | Grove_SDA0 | MIO19, FPGA Bank 500 |
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Pmod Sockets
TEI0802 TE0802 has 2 Pmod 2x6 host sockets which are connected to the FPGA.
| Scroll Title |
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| anchor | Table_SIP_PMOD |
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| title | Pmod SMD Host Socket Information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Designator | Signals | Connected | to Notes | J5 | PMOD_A0...7 | Bank 26 | J6 | PMOD_B0...7 | Bank 26to | Notes |
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| J5 | PMOD_A0...7 | Bank 26 |
| | J6 | PMOD_B0...7 | Bank 26 |
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Test Points
| Scroll Title |
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| anchor | Table_SIP_TestPoint |
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| title | Test Points Information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Test Point | Signals | Notes |
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| TP1 | +1.1V_LPDDR4 |
| | TP2 | +1.8V_MGTRAVTT |
| | TP3 | +1.8V_PL |
| | TP4 | FT_B_TX |
| | TP5 | DP_TX_PWR |
| | TP6 | GND |
| | TP7 | GND |
| | TP8 | PMIC2_SDA |
| | TP9 | PMIC2_TP |
| | TP10 | ONKEY2 |
| | TP11 | PMIC2_SCL |
| | TP12 | DP_TX_HPD |
| | TP13 | DP_TX_PWR |
| | TP14 | INT_SCL1 |
| | TP15 | INT_SDA1 |
| | TP16 | FT_B_RX |
| | TP17 | CLOCKDIST_OE |
| | TP18 | +0.85V_VCCINT |
| | TP19 | +3.3V |
| | TP20 | +1.8V_PS |
| | TP21 | ERR_STATUS |
| | TP22 | +1.2V_PSPLL |
| | TP23 | GND |
| | TP24 | GND |
| | TP25 | PMIC1_SCA |
| | TP26 | PMIC1_SDA |
| | TP27 | ONKEY1 |
| | TP28 | PMIC1_TP |
| | TP29 | POR_B |
| | TP30 | PSBATT |
| | TP31 | SRST_B |
| | TP32 | DONE |
| | TP33 | INIT_B |
| | TP34 | VBUS |
| | TP35 | USB_VBUS |
| | TP36 | PROG_B |
| | TP37 | ERR_OUT |
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On-board Peripherals
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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| Scroll Title |
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| anchor | Table_OBP |
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| title | On-board Peripherals |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Quad SPI Flash Memory
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.assembly options. |
he TE0802 evaluation board has one single QSPI flash connected as x4. Flash size depends on the assembly option, default 32MB
| Scroll Title |
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| anchor | Table_OBP_SPI |
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| title | Quad SPI Interface MIOs and Pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | Schematic | U16 Pin | Notes |
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| MIO0 | MIO0 | B2 | SPI_CLK | | MIO1 | MIO1 | D2 | SPI_DQ1 | | MIO2 | MIO2 | C4 | SPI_DQ2 | | MIO3 | MIO3 | D4 | SPI_DQ3 | | MIO4 | MIO4 | D3 | SPI_DQ0 | | MIO5 | MIO5 | C2 | SPI_CS |
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LPDDR4 SDRAM
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE0802 evaluation board has 1 GByte volatile LPDDR4 SDRAM IC (U13) for storing user application code and data. The details depends on the assembly option.
- Part number: IS43LQ32256A-062BLI
- Supply voltage: 1.06 -1.17 V
- Speed: NOR Flash 1600 MHz
- Temperature: -40 to +85 C
EEPROM
| Scroll Title |
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| anchor | Table_OBP_FPGA_EEP |
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| title | I2C FPGA EEPROM Interface MIOs and Pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | Schematic | U2 Pin | Notes |
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| MIO8 | Int_SCL1 | SCL |
| | MIO9 | Int_SDA1 | SDA |
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| Scroll Title |
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| anchor | Table_OBP_I2C_FPGA_EEP |
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| title | I2C Address for FPGA EEPROM |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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MIO Pin| Type | I2C Address | Designator | Notes | MIO8...9 | 4AA025E48T-I/OT | 0x50 | U2 | EEPROM with MAC |
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| Scroll Title |
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| anchor | Table_OBP_FTDI_EEP |
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| title | I2C FTDI EEPROM Interface Pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Pin | Schematic | U18 Pin | Notes |
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| CS | EECS | 1 | FTDI | | CLK | EECLK | 2 | FTDI | | DIN/DO | EEDATA | 3/4 | FTDI |
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USB ULPI PHY
The TEI0802 TE802 is equipped with a USB ULPI PHY.
| Scroll Title |
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| anchor | Table_OBP_USB |
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| title | USB ULPI PHY Connections and Pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| USB PHY Pin | Signal Schematic Names | Connected to | Note |
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DATA0 | USB0_DATA0 | MIO56, FPGA Bank 502 |
| | DATA1 | USB0_DATA1 | MIO57, FPGA Bank 502 |
| | DATA2 | USB0_DATA2 | MIO54, FPGA Bank 502 |
| | DATA3 | USB0_DATA3 | MIO59, FPGA Bank 502 |
| | DATA4 | USB0_DATA4 | MIO60, FPGA Bank 502 |
| | DATA5 | USB0_DATA5 | MIO61, FPGA Bank 502 |
| | DATA6 | USB0_DATA6 | MIO62, FPGA Bank 502 |
| | DATA7 | USB0_DATA7 | MIO63, FPGA Bank 502 |
| | DIR | USB0_DIR | MIO53, FPGA Bank 502 |
| | NXT | USB0_NXP | MIO55, FPGA Bank 502 |
| | STP | USB0_STP | MIO58, FPGA Bank 502 |
| | RESETB | USB0_RST_N | MIO38, FPGA Bank 501 |
| | CPEN | USB0_VBUS_EN | Pin 1, U21 (Current-limited Power Switch) |
| | VBUS | VBUS | Pin 8, U21 (Current-limited Power Switch). Pin 1, J11 (USB Connector) |
| | ID | USB0_ID | Pulled-down to GND |
| | DP | USB0_D_P | Pin 3, J11 (USB Connector) |
| | DM | USB0_D_N | Pin 2, J11 (USB Connector) |
| | REFCLK | USB0_RCLK | Pin 3, U23 (Oscillator) |
| | CLKOUT | USB0_CLK | MIO52, FPGA Bank 502 |
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Ethernet PHY
The TEI0802 TE0802 is equipped with an Ethernet PHY (U6) which is connected to RJ45 (JJ4) connector.
| Scroll Title |
|---|
| anchor | Table_OBP_ETH |
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| title | Ethernet PHY Connections and Pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Ethernet PHY Pin | Signal Schematic Names | ETH | Note |
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| TXD0 | ETH_TXD0 | MIO65, FPGA Bank 502 |
| | TXD1 | ETH_TXD1 | MIO66, FPGA Bank 502 |
| | TXD2 | ETH_TXD2 | MIO67, FPGA Bank 502 |
| | TXD3 | ETH_TXD3 | MIO68, FPGA Bank 502 |
| | TX_CTRL | ETH_TXCTL | MIO69, FPGA Bank 502 |
| | TX_CLK | ETH_CLK | MIO64, FPGA Bank 502 |
| | MDIO | ETH_MDIO | MIO77, FPGA Bank 502 | Pulled-up to +1.8V_PS. | | MDC | ETH_MDC | MIO76, FPGA Bank 502 |
| | MDIP[0] | PHY_MDI0_P | Pin2, J4 (RJ45) |
| | MDIN[0] | PHY_MDI0_N | Pin3, J4 (RJ45) |
| | MDIP[1] | PHY_MDI1_P | Pin4, J4 (RJ45) |
| | MDIN[1] | PHY_MDI1_N | Pin5, J4 (RJ45) |
| | MDIP[2] | PHY_MDI2_P | Pin6, J4 (RJ45) |
| | MDIN[2] | PHY_MDI2_N | Pin7, J4 (RJ45) |
| | MDIP[3] | PHY_MDI3_P | Pin8, J4 (RJ45) |
| | MDIN[3] | PHY_MDI3_N | Pin9, J4 (RJ45) |
| | LED[0] | PHY_LED0 | LED, J4 (RJ45) |
| | LED[1] | PHY_LED1 | LED, J4 (RJ45) |
| | CONFIG | - | - | Pulled-up to +1.8V_PS. | | XTAL_IN | ETH_XTAL_IN | Pin 3, U7 (Oscillator) |
| | RESETn | ETH_RST | MIO37, FPGA Bank 501 | Pulled-up to +1.8V_PS. | | RX_CLK | ETH_RXCK | MIO70, FPGA Bank 502 |
| | RX_CTRL | ETH_RXCTL | MIO75, FPGA Bank 502 |
| | RXD[0] | ETH_RXD0 | MIO71, FPGA Bank 502 |
| | RXD[1] | ETH_RXD1 | MIO72, FPGA Bank 502 |
| | RXD[2] | ETH_RXD2 | MIO73, FPGA Bank 502 |
| | RXD[3] | ETH_RXD3 | MIO74, FPGA Bank 502 |
|
|
FTDI FT2232H
The FTDI chip U17 converts signals from USB 2.0 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet for more information about the capacity of the FT2232H chip.
Channel A of FTDI FT2232H chip is used in MPPSE mode for JTAG. Channel B is used in UART mode.
...
| Scroll Title |
|---|
| anchor | Table_OBP_FTDI |
|---|
| title | FTDI Chip Interfaces and Pins |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| FTDI Chip Pin | Signal Schematic Name | Connected to | Notes |
|---|
| ADBUS0 | TCK | Pin H13, FPGA Bank 503 | JTAG Interface | | ADBUS1 | TDI | Pin H12, FPGA Bank 503 | JTAG Interface | | ADBUS2 | TDO | Pin J13, FPGA Bank 503 | JTAG Interface | | ADBUS3 | TMS | Pin J12, FPGA Bank 503 | JTAG Interface | | BDBUS0 | FT_B_TX | MIO10, FPGA Bank 500 | UART | | BDBUS1 | FT_B_RX | MIO11, FPGA Bank 500 | UART | | EECS | EECS | Pin 1, U18 (EEPROM) |
| | EECLK | EECLK | Pin 2, U18 (EEPROM) |
| | EEDATA | EEDATA | Pin 3/4, U18 (EEPROM) |
| | OSCI | - | Pin 3, U19 (Oscillator) |
| | DM | D_N | Pin 2, J8 (Micro USB 2.0) |
| | DP | D_P | Pin 3, J8 (Micro USB 2.0) |
|
|
Clock Generator
The TEI0802 TE0802 is equipped with a clock generator (U8).
| Scroll Title |
|---|
| anchor | Table_OBP_CLK_GEN |
|---|
| title | Clock Generator Connections and Pins |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Clock Generator Pin | Signal Schematic Names | Connected to | Note |
|---|
| REFP | - | Pin 3, U43 (Oscillator) |
| | REFSEL | REFSEL | - | Pulled-up to +3.3V. | | RESETN/SYNC | CLK_GEN_RESET | Pin B5, FPGA Bank 26 | Pulled-up to +3.3V. | | EEPROMSEL | EEPROMSEL | - | Pulled-up to +3.3V. | | SDA/GPIO2 | CLK_GEN_SDA | - (Default) MIO9, FPGA Bank 500 (R185/196 required) Pin 2, J14 (Pin Header required) | Pulled-up to +3.3V. (Default) Pulled-up to +3.3V. Pulled-up to +3.3V. | | SCL/GPIO3 | CLK_GEN_SCL | - (Default) MIO8, FPGA Bank 500 (R185/196 required) Pin 3, J14 (Pin Header required) | Pulled-up to +3.3V. (Default) Pulled-up to +3.3V. Pulled-up to +3.3V. | | OE/GPIO4 | - | - | Pulled-up to +3.3V. | Y1P | CLK_Y1_P / CLK_DP_P | Pin G19, FPGA Bank 505 | 27 MHz | | Y1N | CLK_Y1_N / CLK_DP_N | Pin G20, FPGA Bank 505 | 27 MHz | Y2P | CLK_Y2_P / CLK_USB_P | Pin J19, FPGA Bank 505 | 26 MHz | | Y2N | CLK_Y2_N / CLK_USB_N | Pin J20, FPGA Bank 505 | 26 MHz | Y3P | CLK_Y3_P / CLK_PCIe_P | Pin L19, FPGA Bank 505 | 100 MHz | | Y3N | CLK_Y3_N / CLK_PCIe_N | Pin L20, FPGA Bank 505 | 100 MHz | Y4P | CLK_Y4_P / SSD_RCLK_P | Pin 55, U5 (M.2) | 100 MHz | | Y4N | CLK_Y4_N / SSD_RCLK_N | Pin 53, U5 (M.2) | 100 MHz |
|
...
Clock Sources
| Scroll Title |
|---|
| anchor | Table_OBP_CLK |
|---|
| title | Oscillators |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Designator | Signal Schematic Names | Connected to | Description | Frequency | Note |
|---|
| U7 | ETH_XTAL_IN | Pin 34, U6 (Ethernet PHY) | Clock for Ethernet | 25 MHz |
| | U15 | PS_CLK | Pin H14, FPGA Bank 503 | Clock for FPGA | 33 MHz |
| | U23 | USB_CLK / USB0_RCLK | Pin 26, U22 (USB PHY) | Clock for USB | 52 MHz |
| | U43 | - | Pin 5, U8 (Clock Generator) | Clock for Clock Generator | 25 MHz |
|
|
7-Segment Display
The TEI0802 TE0802 has a 4-Digit-7-Segment LED display.
| Scroll Title |
|---|
| anchor | Table_OBP_7SEG |
|---|
| title | 7-Segment LED Pins |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Pin | Schematic | Connected to | Notes |
|---|
| A/L1 | CA / SEG_CA | Pin E4, FPGA Bank 65 |
| | B/L2 | CB / SEG_CB | Pin D3, FPGA Bank 65 |
| | C/L3 | CC / SEG_CC | Pin N5, FPGA Bank 65 |
| | D | CD / SEG_CD | Pin P5, FPGA Bank 65 |
| | E | CE / SEG_CE | Pin N4, FPGA Bank 65 |
| | F | CF / SEG_CF | Pin C3, FPGA Bank 65 |
| | G | CG / SEG_CG | Pin R5, FPGA Bank 65 |
| | DP | CDP / SEG_CDP | Pin N3, FPGA Bank 65 |
| | A1 | SEG_AN1 | Pin A9, FPGA Bank 26 |
| | A2 | SEG_AN2 | Pin B9, FPGA Bank 26 |
| | A3 | SEG_AN3 | Pin A7, FPGA Bank 26 |
| | A4 | SEG_AN4 | Pin B6, FPGA Bank 26 |
| | L1-L3 | SEG_AN | Pin A8, FPGA Bank 26 |
|
|
User LED
| Scroll Title |
|---|
| anchor | Table_OBP_LED |
|---|
| title | On-board LEDs |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Schematic | Color | Connected to | Active Level | Note |
|---|
| LED0...7 | Red | Bank 65 | High |
| | D12 | Green | U9, PMIC | High | POWER_OK |
|
Push Button
| Scroll Title |
|---|
| anchor | Table_OBP_PBTN |
|---|
| title | On-board Push Buttons |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Designator | Schematic | Connected to | Functionality | Note |
|---|
| BTN_1 | USER_BTN_UP | Pin U2, FPGA Bank 65 | User Push Button | Pulled-up to +1.8V_PL. | | BTN_2 | USER_BTN_LEFT | Pin R1, FPGA Bank 65 | User Push Button | Pulled-up to +1.8V_PL. | | BTN_3 | USER_BTN_OK | Pin T1, FPGA Bank 65 | User Push Button | Pulled-up to +1.8V_PL. | | BTN_4 | USER_BTN_RIGHT | Pin U1, FPGA Bank 65 | User Push Button | Pulled-up to +1.8V_PL. | | BTN_5 | USER_BTN_DOWN | Pin T2, FPGA Bank 65 | User Push Button | Pulled-up to +1.8V_PL. | | BTN_6 | POR_B | Pin 38, U1 (PMIC), Pin 38, U9 (PMIC), Pin K12, FPGA Bank 503 | Reset Button | Pulled-up to +3.3V. |
|
DIP Switch
| Scroll Title |
|---|
| anchor | Table_OBP_DIP_SWITCH |
|---|
| title | DIP Switches |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Designator | Schematic | Connected to | Functionality | Note | S1A
|---|
| S1-1(A) | MODE0 | Pin J16, FPGA Bank 503 | DIP | Pulled-down to GND. | S1B| S1-2(B) | MODE1 | Pin H15, FPGA Bank 503 | DIP | Pulled-down to GND. | S1C | S1-3(C) | USER_CFG0 | Pin A4, FPGA Bank 66 | DIP | Pulled-down to GND. | S1D| S1-4(D) | USER_CFG1 | Pin B4, FPGA Bank 66 | DIP | Pulled-down to GND. | S7A | S7-1(A) | USER_SW7 | Pin M5, FPGA Bank 65 | DIP | Pulled-up to +1.8V_PL. | S7B| S7-2(B) | USER_SW6 | Pin M4, FPGA Bank 65 | DIP | Pulled-up to +1.8V_PL. | S7C| S7-3(C) | USER_SW5 | Pin J2, FPGA Bank 65 | DIP | Pulled-up to +1.8V_PL. | S7D| S7-4(D) | USER_SW4 | Pin K1, FPGA Bank 65 | DIP | Pulled-up to +1.8V_PL. | S8A| S8-1(A) | USER_SW3 | Pin L1, FPGA Bank 65 | DIP | Pulled-up to +1.8V_PL. | S8B| S8-2(B) | USER_SW2 | Pin M1, FPGA Bank 65 | DIP | Pulled-up to +1.8V_PL. | S8C| S8-3(C) | USER_SW1 | Pin P2, FPGA Bank 65 | DIP | Pulled-up to +1.8V_PL. | S8D| S8-4(D) | USER_SW0 | Pin P3, FPGA Bank 65 | DIP | Pulled-up to +1.8V_PL. |
|
Power and Power-On Sequence
...
| Scroll Title |
|---|
| anchor | Figure_PWR_PD |
|---|
| title | Power Distribution |
|---|
|
| Scroll Ignore |
|---|
| draw.io Diagram |
|---|
| border | false |
|---|
| viewerToolbar | true |
|---|
| |
|---|
| fitWindow | false |
|---|
| diagramDisplayName | |
|---|
| lbox | true |
|---|
| revision | 24 |
|---|
| diagramName | TE0802_PWR_PD |
|---|
| simpleViewer | truefalse |
|---|
| width | |
|---|
| links | auto |
|---|
| tbstyle | hidden |
|---|
| diagramWidth | 561641 |
|---|
|
|
| Scroll Only |
|---|
 Image Modified
|
|
Power-On Sequence
...
| anchor | Figure_PWR_PS |
|---|
| title | Power Sequency |
|---|
...
PMICs will be reset after pressing Push Button BTN6 (POR_B).
Power Rails
| Scroll Title |
|---|
| anchor | Table_PWR_PR |
|---|
| title | Module Power Rails |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Power Rail Name | Direction | Notes |
|---|
| VIN | InIN | Supply Voltage | | +5V | Out | J1...2 | | +3.3V | Out | J14, J10 |
|
Bank Voltages
| Scroll Title |
|---|
| anchor | Table_PWR_BV |
|---|
| title | SoC Bank Voltages |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Schematic Name | | Notes |
|---|
| Bank 26 | +3.3V | 3.3 V |
| | Bank 65 | +1.8V_PL | 1.8 V |
| | Bank 66 | +1.8V_PL | 1.8 V |
| | Bank 500 | +3.3V | 3.3 V |
| | Bank 501 | +3.3V | 3.3 V |
| | Bank 502 | +1.8V_PS | 1.8 V |
| | Bank 503 | +3.3V | 3.3 V |
| | Bank 504 | +1.1V_LPDDR4 | 1.1 V |
| | Bank 505 | +0.85V_MGTRAVCC | 0.85 V |
|
|
Technical Specifications
Absolute Maximum Ratings
| Scroll Title |
|---|
| anchor | Table_TS_AMR |
|---|
| title | Absolute Maximum Ratings |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Symbols | Description | Min | Max | Unit |
|---|
| VIN | Input Supply Voltage (J13) | -3.5 | 7 | V | | T_STG | Storage Temperature | -40 |
50V
|
Recommended Operating Conditions
...
| Scroll Title |
|---|
| anchor | Table_TS_ROC |
|---|
| title | Recommended Operating Conditions |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Parameter | Min | Max | Units | Reference Document |
|---|
| VIN | 4 | 5.5 | V | Schematic "POWER" (Component: LTC4365ITS8) | | T_STG | 0 | 85 | °C | Zynq Ultrascale+ Data sheet |
|
Physical Dimensions
Module size: 100 mm × 100 mm. Please download the assembly diagram for exact numbers.
PCB thickness: 1,.48 mm
| Page properties |
|---|
|
In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM. For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below: https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF
|
...
| Scroll Title |
|---|
| anchor | Table_VCP_SO |
|---|
| title | Trenz Electronic Shop Overview |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
|
Revision History
Hardware Revision History
...
| Scroll Title |
|---|
| anchor | Table_RH_HRH |
|---|
| title | Hardware Revision History |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Date | Revision | Changes | Documentation Link |
|---|
| 2019-04-29 | 02 | - Added suppressor 1SMA5.0AT3G on power input
- Changed OV and UV protection range
- Changed VGA schematic
- USB page: VBUS resistor changed on 1KThe revision has been renamed as TE0802-02-2AEV2-A
| REV02 | | 2018-10-17 | 01 | Release | REV01 |
|
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
...
| Scroll Title |
|---|
| anchor | Table_RH_DCH |
|---|
| title | Document Change History |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Date | Revision | Contributor | Description |
|---|
| Page info |
|---|
| infoType | Modified date |
|---|
| dateFormat | yyyy-MM-dd |
|---|
| type | Flat |
|---|
|
| | Page info |
|---|
| infoType | Current version |
|---|
| prefix | v. |
|---|
| type | Flat |
|---|
| showVersions | false |
|---|
|
| | Page info |
|---|
| infoType | Modified by |
|---|
| type | Flat |
|---|
| showVersions | false |
|---|
|
Initial Release | | | 2020-11-19 | v.65 | Pedram Babakhani | | -- | all | | Page info |
|---|
| infoType | Modified users |
|---|
| type | Flat |
|---|
| showVersions | false |
|---|
|
| |
|
...