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Table of Contents |
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Trenz Electronic TE0728 is an automotive-grade FPGA module integrating an Automotive Xilinx Zynq-7 FPGA, two Ethernet transceivers (PHY) , DDR3L SDRAMDDR3 SDRAM, QSPI Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips.
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- Xilinx
XA7Z020- XC7Z020-1CLG484Q (Automotive) [XA7Z014S is available on other assembly options]
- Rugged for shock and high vibration
- Dimensions: 6 x 6 cm
Temperature range: Automotive- Package: CL/CLG484
- Speed Grade: -1
- Temperature Grade: Expanded (-40 to +128 °C)
- Dual-Core ARM Cortex-A9 MPCore
- 2 x 100 MBit Ethernet transceiver (PHY)
DDR3L SDRAM, 16-bit-width - DDR3 SDRAM, up to 512MB, up to 1066 Mb/s, connected to PS [different size is available on other assembly options]
- QSPI Flash memory (with XiP support) [different size is available on other assembly options]
- Programmable SIT8918A , PS clock generator
- 2 Kbit serial EEPROM
- Three user LEDs
- CAN transceiver (PHY)
- Temperature compensated RTC (real-time clock)
- 2 x 100 MBit Ethernet transceiver (PHY)
- Board to Board (B2B)
- Plug-on module with 3 x 80-pin Samtec Micro Tiger Eye(TM) high-speed connectors
76 single ended - I/O
, 24 LVDS pairs (48 I/O) and 42 MIO available on board-to-board connectors- Interface
- 42x MIO
- 200x HR
- 128x PS IO
- 0x GTP Transceiver
- 0x GTX Transceiver
- CAN transceiver (PHY)
- Power Supply
- 12 V power supply with watchdog
- Others:
- Dimensions: 6 x 6 cm
- Rugged for shock and high vibration
- On-board high-efficiency DC-DC converters
- System management and power sequencing
- eFUSE bit-stream encryption
- AES bit-stream encryption
- Temperature compensated RTC (real-time clock)
Three user LEDs- Evenly-spread supply pins for good signal integrity
Block Diagram
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![](/download/attachments/33489442/TE0728_OV_BD.png?version=25&modificationDate=1549903430442&api=v2)
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Main Components
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Notes : - |Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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title | TE0728 main components |
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| ![](/download/attachments/33489442/TE0728_MC2.png?version=50&modificationDate=1549884988013&api=v2)
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title | Initial delivery state of programmable devices on the module |
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Storage Device | Symbol | Content |
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Quad SPI Flash | U13 | Not Programmed | EEPROM | U11 | Not Programmed |
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title | Boot process. |
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Signal | FPGA Bank | Pin | B2B | Signal State | Boot Mode |
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Boot_R | 500 | E4 | J2-11 | Low | QSPI | High | SD Card |
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title | Reset process. |
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Signal | B2B | I/O | Note |
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Reset | J2-7 | Input | Comes from Carrier | RST_OUT | J2-9 | Output | PS_PROB_B |
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Board to Board (B2B) I/Os
TE0728 Module has 3 B2B connectors and every connector has 80 pins (2 row, 40 pins).
FPGA bank number and number of I/O signals connected to the B2B connector:
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FPGA Bank | Type | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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13 | HR | J1 | 48 Single ended (24 Diff) | VCCO_13 | variable from carrier | 500 | MIO | J1 | 4 Singel ended | 3.3V |
| 501 | MIO | J2 | 38 Singel ended | VMIO1 | variable from carrier | 33 | HR | J3 | 34 Single ended (17 Diff) | 3.3V |
| 35 | HR | J3 J2 | 20 Single ended (10 Diff) 22 Single ended (11 Diff) | 3.3V |
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Ethernet PHY
Ethernet pins connections to Board to Board (B2B). Ethernet components ETH1 and ETH2 are connected to B2B connector J3.
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title | Ethernet PHY B2B connectors. |
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Schematic | ETH1 | ETH2 | Direction | Notes |
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CTREF | J3-57 | J3-25 | In | Magnetics center tap voltage | TD+ | J3-58 | J3-28 | Out | Transfer | TD- | J3-56 | J3-26 | Out |
| RD+ | J3-52 | J3-22 | In | RecieveReceive | RD- | J3-50 | J3-20 | In |
| LED1 | J3-55 | J3-23 | Out | LED Yellow on carrier, multiple usage-ACK | LED2 | J3-53 | J3-21 | Out |
| LED3 | J3-51 | J3-19 | Out | LED Green on carrier, multiple usage-Link | POWERDOWN/INT | L21 | R20 | In |
| RESET_N | M15 | R16 | In | Active low PHY Reset |
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title | CAN B2B connectors. |
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Schematic | B2B | Direction | Notes |
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CANH/CANL | J1-2/J1-4 | Inout/Inout |
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JTAG Signal | B2B Pin |
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TMS | J2-12 | TDI | J2-10 | TDO | J2-8 | TCK | J2-6 |
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MIO Pin | Connected to | B2B | Notes |
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MIO0 | MIO0 | - | RTC interrupt | MIO1...MIO6 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | - | SPI Flash | MIO7 | LED RED | - | LED | MIO8/MIO9 | Tx/Rx | - | CAN Transceiver | MIO10...MIO13 | IO_0 ... IO_3 | J1 | GPIO | MIO14/MIO15 | SCL/SDA | - | I2C | MIO16...MIO27MIO39 | - | J2 | GPIO | MIO28MIO40...MIO39MIO48 | CLK, Cmd, Data0Tx_clk, Txd0...Txd3, Tx_ctl Rx_clk, Rxd0...Rxd3, Rx_ctl | J2 | ETH | MIO40...MIO48 | CLK, Cmd, Data0...Data3, wp, cd | J2 | Data3, wp, cd | J2 | SD | MIO48 | PS_MIO48_501 | J2 | LED Red on Carrier | MIO49 | PS_MIO49_501 | J2 | LED Yellow on Carrier | MIO50 | PS_MIO49_501 | J2 | LED Green on Carrier | MIO51 | PS_MIO51_501 | J2 | GPIO | MIO52/MIO53 | UART_Txd / UART_Rxd | J2 | UART transfer/recieve |
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever Transceiver PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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title | On board peripherals |
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Quad SPI Flash Memory
On-board QSPI flash memory is used to store initial FPGA configuration. Datasheet is provided in Texas Instruments. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency.
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title | Quad SPI interface MIOs and pins |
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MIO Pin | Schematic | Notes |
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MIO1 | SPI_CS |
| MIO2 | SPI_DQ0/M0 |
| MIO3 | SPI_DQ1/M1 |
| MIO4 | SPI_DQ2/M2 |
| MIO5 | SPI_DQ3/M3 |
| MIO6 | SPI_SCK/M4 |
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The RTC has an I2C Bus (2-wire SerialInterface) and offers temperature compensated time. The STC-Smart Temperature Compensation is calibrated in the factory and leads to a very high time-accuracy.
RTC intruppt interrupt is connected to MIO0 connected to Bank 500 through pin G6.
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title | I2C Address for RTC |
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MIO Pin | I2C Address | Designator | Notes |
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MIO14...15 | 0xAD / 0xAC0x56 | U7 | Read/ WriteSlave address |
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EEPROM
The Microchip Technology Inc. 24xx64 is a 64 Kbit Electrically Erasable PROM. The device is organized as a single block of 8K x 8-bit memory with a 2-wire serial interface. The 24xx64 also has a page write capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for up to 512 Kbits address space.
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title | I2C address for EEPROM |
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MIO Pin | I2C Address | Designator | Notes |
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MIO14...15 | 0xA1/0xA00x50 | U11 | Read/WriteSlave address |
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LEDs
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Designator | Color | Connected to | Active Level |
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D9 | Green | DONE | Low | D8 | RED | MIO7 | High | D4 | Green | Bank 33 - V18 | High |
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DDR3 SDRAM can be varied on demand for other assembly options. DDR3 can have density of maximum 512MB due to available addressing. The maximum possible speed for DDR3 SDRAM is 1066 Mb/s.
Ethernet
There are two 100 MBit Extreme Temperature Ethernet provided by Texas Instrumen on the board. Datasheet is provided at TI website. Both PHY's are connected with all I/O Pins to FPGA Bank 34 (VCCIO = 3.3V). PHY Clock 25 MHz source sources is provided from MEMS Oscillator. There is no sharing of signals for the two PHY's.
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title | Ethernet PHY to Zynq SoC connections |
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Bank | Signal Name | ETH1 | ETH2 | Signal Description |
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34 | ETH-RST | M15 | R16 | Ethernet reset, active-low. | 34 | ETH_COL | L16 | P20 |
| 34 | MDC | P16 | T17 | Ethernet management clock. | 34 | MDIO | M16 | T16 | Ethernet management data. | 34 | ETH_TX_D0 | J22 | N22 | Ethernet transmit data 0. Output to Ethernet PHY. | 34 | ETH_TX_D1 | M17 | P21 | Ethernet transmit data 1. Output to Ethernet PHY. | 34 | ETH_TX_D2 | K21 | P22 | Ethernet transmit data 2. Output to Ethernet PHY. | 34 | ETH_TX_D3 | M22 | R21 | Ethernet transmit data 3. Output to Ethernet PHY. | 34 | ETH_TX_EN | J21 | M21 | Ethernet transmit enable. | 34 | ETH_RX_D0 | L17 | R18 | Ethernet receive data 0. Input from Ethernet PHY. | 34 | ETH_RX_D1 | K18 | R19 | Ethernet receive data 1. Input from Ethernet PHY. | 34 | ETH_RX_D2 | J18 | T18 | Ethernet receive data 2. Input from Ethernet PHY. | 34 | ETH_RX_D3 | J20 | T19 | Ethernet receive data 3. Input from Ethernet PHY. | 34 | ETH_RX_DV | N17 | P15 | Ethernet receive data valid. |
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CAN Transceiver
Controller Area Network (CAN) transceivers are designed for use with the Texas Instruments TMS320Lx240x 3.3-V DSPs with CAN controllers. The datasheet is available in TI website. Each CAN transceiver is designed to provide differential transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1 Mbps.
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title | CAN Tranciever interface MIOs |
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Bank | Signal name | Notes |
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500 | D - Tx | Driver Input | 500 | R - Rx | Reciever Output |
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Oscillators
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Designator | Description | Frequency | Used as |
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U14 | MEMS Oscillator | 50 MHz | PS_CLK | U5 | MEMS Oscillator | 25 MHz | Ethernet PHY Clock | U7 | RTC (internal oscillator) | 32.768 KHz | CLKOUT of RTC is not connected |
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title | Power Consumption |
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Power Input Pin | Typical Current |
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VIN | TBD* |
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Power on Sequence
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Voltage Monitor Circuit
The microprocessor supervisory circuits monitor system voltages asserting an open-drain RESET signal when the SENSE voltage drops below a preset threshold or when the manual reset (MR) pin drops to a logic low. The RESET output remains low for the user adjustable delay time after the SENSE voltage and MR return above their thresholds. Datasheet is available in Texas Instruments website.
Power Rails
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title | Module power rails.Voltage Monitor Circuit |
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cellHighlightingB2B NameB2BJM1 Pin
B2B JM2 Pin | B2B JM3 Pin | Direction | Notes |
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VIN | 1,3 | - | - | Input | Supply voltage from carrier board. |
VCCO_13 | 39 | - | - | I/O | VBATT | - | 1 | - | Output | RTC Supply voltage |
3.3V | 19 | 4 | 25,57 | Output | Internal 3.3V voltage level. |
VMIO | - | 2 | Input | 3.3V from carrier | 1.8V | - | 5 | - | Output | Internal 1.8V voltage level. |
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Power Rails
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title | Zynq SoC bank voltagesModule power rails. |
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| Schematic Name | | I/O Type | Notes |
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| 500 | VCCO_MIO0_500 | 3.3V | MIO |
501 | VCCO_MIO1_501 | 2.5V or 3.3V | MIO | supplied by 3.3V from carrier. |
502 | VCCO_DDR_502 | 1.5V | DDR3 | 13 | VCCO_13 | 1.8V or 3.3V | HR | Supplied by the carrier board. J1 |
33 | 3.3V | 3.3V | HR | Supplied by carrier board. J3 |
34 | 3.3V | 3.3V | HR | 35 | 3.3V | 3.3V | HR | Supplied by the carrier board. J2, J3 |
Board to Board Connectors
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Power Signal | B2B JM1 Pin | B2B JM2 Pin | B2B JM3 Pin | Direction | Notes |
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VIN | 1,3 | - | - | Input | Supply voltage from carrier board. | VCCO_13 | 39 | - | - | Input |
| VBATT | - | 1 | - | Output | RTC Supply voltage | 3.3V | 19 | 4 | 25,57 | Output | Internal 3.3V voltage level. | VMIO | - | 2 |
| Input | Variable and supplied by carrier | 1.8V | - | 5 | - | Output | Internal 1.8V voltage level. |
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Bank Voltages
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title | Zynq SoC bank voltages. |
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| Schematic Name | | I/O Type | Notes |
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500 | VCCO_MIO0_500 | 3.3V | MIO |
| 501 | VCCO_MIO1_501 | 2.5V or 3.3V | MIO | supplied by carrier. | 502 | VCCO_DDR_502 | 1.5V | DDR3 |
| 13 | VCCO_13 | 1.8V or 3.3V | HR | Supplied by the carrier board. J1 | 33 | 3.3V | 3.3V | HR | Supplied by carrier board. J3 | 34 | 3.3V | 3.3V | HR |
| 35 | 3.3V | 3.3V | HR | Supplied by the carrier board. J2, J3 |
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Board to Board Connectors
Include Page |
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| 6 x 6 SoM TEM and SEM B2B Connectors |
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| 6 x 6 SoM TEM and SEM B2B Connectors |
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Technical Specifications
Absolute Maximum Ratings
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Symbols | Min | Max | Unit | Description |
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VIN supply voltage | -0.3 | 65 | V | TPS54260-Q1 datasheets. | VMIO | -0.5 | 3.6 | V | PS MIO I/O supply |
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6 x 6 modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.
3 x REF-189018-01 (compatible to SEM-140-02-03.0-H-D-A), (80 pins, "40" per row)
Technical Specifications
Absolute Maximum Ratings
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anchor | Table_TS_AMR |
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title | Absolute maximum ratings |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Symbols | Min | Max | Unit | Description |
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VCCPINT | -0.5 | 1.1 | V | PS internal logic supply voltage |
VCCPAUX | -0.5 | 2.0 | V | PS auxiliary supply voltage |
VCCPLL | -0.5 | 2.0 | V | PS PLL supply |
VCCO_DDR | -0.5 | 2.0 | V | PS DDR I/O supply voltage |
VPREF | -0.5 | 2.0 | V | PS input reference voltage |
VCCO_MIO0 | -0.5 | 3.6 | V | PS MIO I/O supply voltage for HR I/O banks |
VCCO_MIO1 | 1.71 | 3.45 | V | PS MIO I/O supply voltage for HR I/O banks |
VCCINT | -0.5 | 1.1 | V | PL internal logic supply voltage |
VCCPAUX | -0.5 | 2.0 | V | PL auxiliary supply voltage |
VCCPLL | -0.5 | 1.1 | V | PL PLL supply |
VPREF | -0.5 | 2.0 | V | PL input reference voltage |
VCCO | -0.5 | 3.6 | V | PL supply voltage for HR I/O banks | VIN |
Storage Temperature | -40 | +85 | °C | 1.71 | 3.45 | V | I/O input voltage for HR I/O banks |
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Recommended Operating Conditionse
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anchor | Table_TS_ROC |
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title | Recommended operating conditions |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Symbol | Min | Max | Units | Reference Document |
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VIN supply voltage | 3.5 | 60 | V | TPS54260-Q1 datasheets. | VMIO | 1.71 | Parameter | Min | Max | Units | Reference Document |
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VIN supply voltage | 3.5 | 60 | V | TPS54260-Q1 datasheets. | Supply voltage for PS MIO banks | 1.71 | 3.465 | V | See Xilinx DS187 datasheet. | I/O input voltage for PS MIO banks | -0.2 | VCCO_MIO + 0.20 | V | See Xilinx DS187 datasheet. | Supply voltage for PS DDR | 1.14 | 1.89 | V | See Xilinx DS187 datasheet. | I/O input voltage for PS DDR | -0.20 | VCCO_DDR + 0.20 | V | See Xilinx DS187 datasheet. | Supply voltage for HR I/Os banks | 1.14 | 3.465 | V | See Xilinx DS187 datasheetdata sheet. | I/O input voltage for HR I/O banks | VCCO | 1.14 | 3.465 | -0.20 | VCCIO + 0.20 | V | See Xilinx DS187 datasheet. | Storage Temperature | -40 | +85 | °Cdatasheet. | Operating Temperature | -40 | +105 | °C |
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anchor | Figure_TS_PD |
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title | Physical Dimension |
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Scroll Ignore |
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draw.io Diagram |
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border | false |
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viewerToolbar | true |
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fitWindow | false | diagramDisplayName |
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lbox | false |
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revision | 21 |
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diagramName | TE0728_MC1 |
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simpleViewer | true | width | 640 |
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links | auto |
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tbstyle | hidden |
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lbox | false |
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diagramWidth | 632 |
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revision | 172122 |
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Scroll Only |
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scroll-pdf | true |
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scroll-office | true |
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scroll-chm | true |
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scroll-docbook | true |
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scroll-eclipsehelp | true |
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scroll-epub | true |
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scroll-html | true |
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| ![](/download/attachments/33489442/TE0728_MC1.png?version=22&modificationDate=1549543245743&api=v2)
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Currently
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Offered Variants
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anchor | Table_VCP_SO |
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title | Trenz Electronic Shop Overview |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default | style | widths |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Hardware Revision History
Product changes can be seen in PCN page.
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anchor | Table_RH_HRH |
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title | Hardware Revision History |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default | style |
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widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Date | Revision | Note | PCN | Documentation Link |
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| 04 | Product Release | PCN | TE0728-04-1Q | Changes |
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| 04 | - U1 DDR3 IC changed from NT5CB256M16CP-DIH to NT5CC256M16CP-DIH
- Net DDR3-ODT0: added series resistor R55
- Added Traceability pad
- Net PS-POR-B: added pull-down resistor R56
| 2015-12-01 | 03 | | 2015-06-12 | 02 | | 2015-03-03 | 01 | | 03 | - | TE0728-03-1Q |
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Hardware revision number is printed on the PCB board next to the module model number separated by the dash.
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Page properties |
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- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf PDF export template - Metadata is only used of compatibility of older exports
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anchor | Table_RH_DCH |
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title | Document change history. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default | style |
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widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Date | Revision | Contributor | Description |
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Page info |
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infoType | Modified date |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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| Page info |
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infoType | Current version |
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prefix | v. |
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type | Flat |
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showVersions | false |
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| Page info |
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infoType | Modified by |
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type | Flat |
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showVersions | false |
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| change list | | 2019-05-16 | v. 367 | Pedram Babakhani | | -- | all | Page info |
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infoType | Modified users |
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type | Flat |
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showVersions | false |
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