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Note for Download Link of the Scroll ignore macro: |
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Table of Contents |
Overview
The Trenz Electronic TEF0003 is a FPGA Mezzanine Card (FMC) integrated with an Artix 7 FPGA, 512 Mb Flash Memory.
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Key Features
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Note:
'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options Key Features' must be split into 6 main groups: - FPGA/Module
- Package:
- Speed:
- Temperature:
- RAM/Storage
- On Board
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
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- FPGA: Xilinx Artix 7 (XC7A100T)
- Package: FGG484 (Compatible with
- Speed: -1 (Slowest)
- Temperature: Industrial Grade (–40°C to +100°C)
- RAM/Storage:
- 1x NOR SPI FLASH (128M x 4)
- 1x EEPROM (16K x 8)
- On Board:
- 4x Deserializer IC (3.12 Gbps)
- 4x I2C and SMBus I/O Expander
- 1x Programable Clock Generator
- 1x Clock Generator
- Interface:
- 2x VITA 57 SEAM/SEAF Series
- 4x Coaxial Connectors
- Power:
- 4x Voltage Regulators
- 3.3 Supply Voltage
- Dimension:
Block Diagram
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add drawIO object here.
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| anchor | Figure_OV_BD |
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| title | TEF0003 block diagram |
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| fitWindow | false |
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| diagramDisplayName | |
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| lbox | true |
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| revision | 912 |
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| diagramName | TEF0003_OV_BD |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| diagramWidth | 641 |
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Main Components
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Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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| Scroll Title |
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| anchor | Figure_OV_MC |
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| title | TEF0003 main components |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| fitWindow | false |
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| diagramDisplayName | |
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| lbox | true |
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| revision | 7 |
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| diagramName | TEF0003_OV_MC |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| diagramWidth | 641 |
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- Coaxial Connectors, J2-5
- SPI Flash, U9
- Xilinx Artix 7 FPGA, U1
- Lattice MachXO FPGA, U15
- FMC Adapter, J1
- EEPROM, U4
- I2C Switches, U2, U17-20
- Jumper, J7
- Serializer, U5-8
- Connector Header, J8
- Oscillator 25MHz, U11
- Programmable Clock Generator, U10
- FMC Adapter, J6
Initial Delivery State
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Notes : Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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| Scroll Title |
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| anchor | Table_OV_IDS |
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| title | Initial delivery state of programmable devices on the module |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Storage device name | Content | Notes |
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SPI Flash | Not programmed |
| | EEPROM | Not Programmed |
| | Clock Generator | Programmed |
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Configuration Signals
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- Overview of Boot Mode, Reset, Enables.
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| Scroll Title |
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| anchor | Table_OV_RST |
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| title | Reset Process. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Signal | Description | Note |
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PRSNT_TOP | Lattice MachXO Configuration Pin |
| | PROG_B | Artix 7 Configuration Pin | , Connected Pulled up to 1.8 |
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Signals, Interfaces and Pins
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Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
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FMC Connectors
FPGA bank number and number of I/O signals connected to the FMC Connectors J1 and J6 which are located on top and bottom of the board.
| Scroll Title |
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| anchor | Table_SIP_FMC |
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| title | General PL I/O to FMC Connectors information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| FPGA | FPGA Bank | Connector Designator | I/O Signal Count | Voltage Level | Notes |
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| Artix 7, U1 | 16 | J1B | 68 Single Ended, 34 Differential | 1.8V |
| | 35 | J6B | 68 Single Ended, 34 Differential | 1.8V |
| | Lattice MachXO, U | 0 | J1F | 4 Single Ended | 3.3V | CPLD | | 0 | J6F | 4 Single Ended | 3.3V | CPLD |
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Coaxial Connectors
| Scroll Title |
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| anchor | Table_SIP_CPLDJTGCoaxial |
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| title | CPLD JTAG pins connectionCoaxial Connectors information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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JTAG Signal| Designator | Schematic | Connected to | Notes |
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| J2 | GA_OUT | Serializer, U5 |
| | J3 | GB_OUT | Serializer, U6 |
| | J4 | GC_OUT | Serializer, U7 |
| | J5 | GD_OUT | Serializer, U8 |
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JTAG Interface
The Lattice MachXO (U15) is available to meet the requirement of a CPLD, JTAG access to the MachXO is available through FMC Adapter J6. JTAG access to the Artix 7(U1) is available via MachXO, Bank 2.
| Scroll Title |
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| anchor | Table_SIP_CPLDJTG |
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| title | CPLD JTAG pins connection |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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JTAG Signal | B2B Connector | Notes |
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| FMC |
B2B Connector | FMC| _TMS | J6F-TCK |
| | FMC_TDI_TOP | J6F-J1-TDI |
| | FMC_TDO_TOP | J6F-TDO |
| | FMC_TCK | J6F-TCK |
| | JTAGEN |
J7
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| Scroll Title |
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| anchor | Table_SIP_JTG |
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| title | JTAG pins connection |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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JTAG Signal | Connected to | Note |
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| TMS | Lattice MachXO, U15 BankArtix 7 FPGA, U1 | Bank 2 Bank 0 | | TDI | Lattice MachXO, U15 Artix 7 FPGA, U1 | Bank 2 Bank 0 | | TDO | Lattice MachXO, U15 Artix 7 FPGA, U1 | Bank 2 Bank 0 | | TCK | Lattice MachXO, U15 Artix 7 FPGA, U1 | Bank 2 Bank 0 | | INIT | Artix 7 FPGA, U1 | Connected Pulled up to 1.8 |
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On-board Peripherals
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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| Scroll Title |
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| anchor | Table_OBP |
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| title | On board peripherals |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Quad SPI Flash Memory
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
TEF0003 is equipped with a 512Mb Serial NOR Flash (x1/x2/x4) which is provided to store an application on in the SPI Flash memory in order to boot the module. The SPI Flash data is connected to Artix 7 FPGBA via FPGA Bank 14.
| Scroll Title |
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| anchor | Table_OBP_SPI |
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| title | Quad SPI interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Schematic | U9 Pin | Notes |
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| SPI-CS | CS |
| | SPI-CLK | CLK |
| | SPI-DQO | DI/IO0 |
| | SPI_DQ3 | HOLD/IO3 |
| | SPI-DQ2 | WP/IO2 |
| | SPI-DQ1 | DO/IO1 |
| | 1.8V | VCC |
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EEPROM
A Microchip 24LC128-I/LC microchip serial EEPROM (U4) is provided for IPMI data. It is accessible via the LPC FMC connector J1 (SCL, SDA).
| Scroll Title |
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| anchor | Table_OBP_EEP |
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| title | I2C EEPROM interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| U4 Pin | FMC Pcam Adapter | Schematic |
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U4 PinNotesSCLSDAA0 |
| | A2 | - | - | Pulled Low | | WP | - | - | Pulled Low |
A1
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| Scroll Title |
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| anchor | Table_OBP_I2C_EEPROM |
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| title | I2C address for EEPROM |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| I2C Address | Designator | Notes |
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0x50| 0xA0 | U4 | Write operations are enabled |
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Clock Sources
| Scroll Title |
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| anchor | Table_OBP_CLK |
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| title | Osillators |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Designator | Description | Frequency | Note |
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| U4U11 | Oscillator, 25 MHzMHz | 25.00 MHz |
| | U10 | Programmable Clock Generator | MHzVariable |
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Programmable Clock Generator
There is a Silicon Labs I2C programmable clock generator on-board (U10) in order to generate reference clocks for the module. Programming can be done using I2C via PIN header J8. The I2C Address is 0x69.
| Scroll Title |
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| anchor | Table_OBP_PCLK |
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| title | Programmable Clock Generator Inputs and Outputs |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Si5345A Pin
| Signal Name / Description
| Connected To | Direction | Note |
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IN0 | Reference input clock. | U11 | Input | 25.00 MHz oscillator, SiT8008BI | | IN1 | FMCT_GBTCLK0 | J6E | Input | FMC Pcam Adapter | | IN2 | FMCT_GBTCLK1 | J6E | Input | FMC Pcam Adapter | | IN3 | FMCT_CLK0 | J6E | Input | FMC Pcam Adapter | XAXB | - | GND | Input | 54.0000 00 MHz XTAL CX3225SB | | SCLK | PLL_SCL | J8, U20 | Input | EEPROM Programming | | SDA | PLL_SDA | J8, U20 | Input | EEPROM Programming | | OUT0 | GA_PCLK | U5/U1 | Output | FPGA bank 15 | | OUT1 | GB_PCLK | U6/U1 | Output | FPGA bank 15 | | OUT2 | GC_PCLK | U7/U1 | Output | FPGA bank 15 | | OUT3 | GD_PCLK | U8/U1 | Output | FPGA bank 15 | | OUT4 | CLK4_P | U1H | Output |
| | OUT5 | GBTCLK0 | J1E/J6E | Output |
| | OUT6 | GBTCLK1 | J1E/J6E | Output |
| | OUT7 | GBTCLK0 | J1E | Output |
| | OUT8/OUT9 | CLK8/CLK9 | Not ConnetedPulled low | Output | Not Used |
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Power and Power-On Sequence
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
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Power Supply
Power supply with minimum current capability of 3 A for system startup is recommended.
Power Consumption
| Scroll Title |
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| anchor | Table_PWR_PC |
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| title | Power Consumption |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Power Input Pin | Typical Current |
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| VIN3P3V | TBD* |
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* TBD - To Be Determined
Power Distribution Dependencies
| Scroll Title |
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| anchor | Figure_PWR_PD |
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| title | Power Distribution |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| fitWindow | false |
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| diagramDisplayName | |
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| lbox | true |
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| revision | 57 |
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| diagramName | TEF0003_PWR_PD |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| diagramWidth | 641 |
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| Scroll Only |
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 Image Modified
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Power-On Sequence
| Scroll Title |
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| anchor | Figure_PWR_PS |
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| title | Power Sequency |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| fitWindow | false |
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| diagramDisplayName | |
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| lbox | true |
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| revision | 2 |
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| diagramName | TEF0003_PWR_PS |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| diagramWidth | 641 |
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| Scroll Only |
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 Image Modified
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Power Rails
| Scroll Title |
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| anchor | Table_PWR_PR |
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| title | Module power rails. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Power Rail Name | FMC Adapter J1G Pin | FMC Adapter J6G Pin | Direction | Notes |
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| 12V | C35, C37 | C35, C37 | Input |
| | 3P3VAUX | D32 | D32 | Input |
| | 3P3V | D36, D38, D40, C39 | D36, D38, D40, C39 | Input |
| VREFA | H1 | H1 | Input |
| | VREFB | K1 | K1 | Input |
| | VIOB | J39, K40 | J39, K40 | Input |
| | VADJ | H40, G39, F40, E39 | H40, G39, F40, E39 | Input |
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Bank Voltages
| Scroll Title |
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| anchor | Table_PWR_BV |
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| title | Zynq SoC bank voltages. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Schematic Name | | Notes |
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| Bank 13 | VCCO_13 | 1.8 V |
| | Bank 14 | VCCO_14 | 1.8 V |
| | Bank 15 | VCCO_15 | 1.8 V |
| | Bank 16 | VCCO_16 | VADJ | 1.8 V | | Bank 34 | VCCO_34 | 1.8 V |
| | Bank 3435 | VCCO_35 | VADJ | Bank 0 | VCCO_0 | 1 | .8 V
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Board to Board Connectors
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| Page properties |
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| This section is optional and only for modules. use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
| Include Page |
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| PD:6 x 6 SoM LSHM B2B Connectors | PD:6 x 6 SoM LSHM B2B Connectors
Technical Specifications
Absolute Maximum Ratings
| Scroll Title |
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| anchor | Table_TS_AMR |
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| title | PS absolute maximum ratings |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Symbols | Description | Min | Max | Unit |
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| 12V3P3V | Input Supply Voltage | -12120.5 | 3.75 | V | | T_STG | Storage Temperature | -40 | 85 | °C |
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Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
| Scroll Title |
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| anchor | Table_TS_ROC |
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| title | Recommended operating conditions. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Parameter | Min | Max | Units | Reference Document |
|---|
12V12 | 12| 2.375 | 3.465 | V |
| | T_OPR | -40 | 85 | °C | See MT25QU512ABB8E12-0SIT (U9) datasheet. |
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Physical Dimensions
Module size: 84 mm × 65 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 10 mm.
PCB thickness: 1.54 56 mm.
| Page properties |
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In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM. For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below: https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF
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| Scroll Title |
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| anchor | Figure_TS_PD |
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| title | Physical Dimension |
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| |
|---|
| fitWindow | false |
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| diagramDisplayName | |
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| lbox | true |
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| revision | 25 |
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| diagramName | TEF0003_TS_PD |
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| aspect | 5e705185-5827-752c-089d-756568e6698b |
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| simpleViewer | false |
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| width | 639 |
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| aspectHash | 7695f7bc00c98da1082cb1c11a0a6258edf875fc |
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| links | auto |
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| tbstyle | hidden |
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| diagramWidth | 436 |
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| Scroll Only |
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| scroll-pdf | true |
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| scroll-office | true |
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| scroll-chm | true |
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| scroll-docbook | true |
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| scroll-eclipsehelp | true |
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| scroll-epub | true |
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| scroll-html | true |
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|  Image Modified
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Currently Offered Variants
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Set correct link to the shop page overview table of the product on English and German. Example for TE0728: ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/ DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/ For Baseboards or modules, where no overview page is available (and revision number is coded in the direct link) use shop search link, e.g. TE0706: ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706 DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706 |
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| Scroll Title |
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| anchor | Table_VCP_SO |
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| title | Trenz Electronic Shop Overview |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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|
Revision History
Hardware Revision History
...
| Scroll Title |
|---|
| anchor | Table_RH_HRH |
|---|
| title | Hardware Revision History |
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| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Date | Revision | Changes | Documentation Link |
|---|
| 2017-06-27 | REV01 | Initial Release | REV01 |
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
| Scroll Title |
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| anchor | Figure_RV_HRN |
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| title | Board hardware revision number. |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| |
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| fitWindow | false |
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| diagramDisplayName | |
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| lbox | true |
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| revision | 4 |
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| diagramName | TEF0003_RV_HRN |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| diagramWidth | 196 |
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| Scroll Only |
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Document Change History
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- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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...
| Scroll Title |
|---|
| anchor | Table_RH_DCH |
|---|
| title | Document change history. |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Date | Revision | Contributor | Description |
|---|
| Page info |
|---|
| infoType | Modified date |
|---|
| dateFormat | yyyy-MM-dd |
|---|
| type | Flat |
|---|
|
| | Page info |
|---|
| infoType | Current version |
|---|
| prefix | v. |
|---|
| type | Flat |
|---|
| showVersions | false |
|---|
|
| | Page info |
|---|
| infoType | Modified by |
|---|
| type | Flat |
|---|
| showVersions | false |
|---|
|
| | -- | all | | Page info |
|---|
| infoType | Modified users |
|---|
| type | Flat |
|---|
| showVersions | false |
|---|
|
| |
|
Disclaimer
| Include Page |
|---|
| IN:Legal Notices |
|---|
| IN:Legal Notices |
|---|
|
...