Page History

Custom_table_size_100

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Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM"

Template Change history:

Version	Changes	Author
3.12	Version History changed from list to table all changed title-alignment for tables from left to center	ma
3.11	update "Recommended Operating Conditions" section
3.1	New general notes for temperature range to "Recommended Operating Conditions"
3.02	add again fix table of content with workaround to use it for pdf and wiki Export Link for key features examples Notes for different Types (with and without Main FPGA) Export Link for Signals, Interfaces and Pins examples Notes for different Types (Modul, Modul Hypride, Evalboard, Carrier)
3.01	remove fix table of content and page layout ( split page layout make trouble with pdf export) changed and add note to signal and interfaces, to on board periphery section ...(not finished)
3.00	→ separation of Carrier/Module and evaluation kit TRM
2.15	add excerpt macro to key features
2.14	add fix table of content add table size as macro

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Important General Note:

If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

Figure template:

Scroll Title

anchor	Figure_anchorname
title-alignment	center
title	Text

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, objects are only linked.

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Table template:
- Layout macro can be use for landscape of large tables

Scroll Title

anchor	Table_tablename
title-alignment	center
title	Text

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Example	Comment
1	2

The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below
- <type>_<main section>_<name>
  - type: Figure, Table
  - main section:
    - "OV" for Overview
    - "SIP" for Signal Interfaces and Pins,
    - "OBP" for On board Peripherals,
    - "PWR" for Power and Power-On Sequence,
    - "B2B" for Board to Board Connector,
    - "TS" for Technical Specification
    - "VCP" for Variants Currently in Production
    - "RH" for Revision History
  - name: custom, some fix names, see below
- Fix names:
  - "Figure_OV_BD" for Block Diagram
  - "Figure_OV_MC" for Main Components
  - "Table_OV_IDS" for Initial Delivery State
  - "Table_PWR_PC" for Power Consumption
  - "Figure_PWR_PD" for Power Distribution
  - "Figure_PWR_PS" for Power Sequence
  - "Figure_PWR_PM" for Power Monitoring
  - "Table_PWR_PR" for Power Rails
  - "Table_PWR_BV" for Bank Voltages
  - "Table_TS_AMR" for Absolute_Maximum_Ratings
  - "Table_TS_ROC" for Recommended_Operating_Conditions
  - "Figure_TS_PD" for Physical_Dimensions
  - "Table_VCP_SO" for TE_Shop_Overview
  - "Table_RH_HRH" for Hardware_Revision_History
  - "Figure_RH_HRN" for Hardware_Revision_Number
  - "Table_RH_DCH" for Document_Change_History
Use Anchor in the document: add link macro and add "#<anchorname>
Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>

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-----------------------------------------------------------------------

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Note for Download Link of the Scroll ignore macro:

Link to the base folder of the module (remove de/ or en/ from the URL):
Example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5_Carriers/TE0728/

Scroll Ignore
Download PDF version of this document.

Overview

The Trenz Electronic AM0010 module is an industrialgrade module based on AMD Xilinx.

Refer to http://trenz.org/AM0010am0010-info for the current online version of this manual and other available documentation.

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Notes :

short description of the PCB
Short Link of the wiki resources reference:
- Use short link the Wiki Resource page, for example: http://trenz.org/te0728-info
- List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

Key Features

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Note:
'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

→ See examples fro different types <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-KeyFeatures

Excerpt

SoC
- Device: ZU1 / ZU2 / ZU3 / ZU4 / ZU5 ¹⁾
- Engine: CG / EG / EV ¹⁾
- Speedgrade: -1 / -2 ¹⁾
- Temperature Range: Extended / Industrial ¹⁾
- Package: SFVC784
RAM/Storage
- 4 GByte DDR4 SDRAM with ECC ²⁾
- 8 GByte e.MMC ³⁾
- Optional HyperFlash ⁴⁾
- 2 x 64 MByte Serial Flash ⁵⁾
- EEPROM with MAC address
On Board
- Gigabit Ethernet Transceiver
- USB Transceiver
- OPTIGA Trust M
- CryptoAuthentication
- Oscillator
- Analog Multiplexer
Interface
- 2 x B2B Connector (ADM6)
  - up to 204 PL IO
  - up to 22 PS MIO
  - 4 GTR
  - 4 GTH (with ZU4 and higher)
  - ETH, USB, I2C, JTAG, ...
Power
- 5 V ... 12 V power supply via B2B Connector needed.
Dimension
- 56.4 mm x 40 mm
Notes
¹⁾ Please, take care of the possible assembly options. Furthermore, check whether the power supply is powerful enough for your FPGA design.
²⁾ Up to 32 GByte are possible with a maximum bandwidth of 2400 MBit/s.
³⁾ Up to 64 GByte are possible.
⁴⁾ Up to 64 MByte are possible.
⁵⁾ Up to 2 x 256 MByte are possible.

Block Diagram

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add drawIO object in Scroll Ignore section and add reference image in Scroll Only.

Note
For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .

Note

Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name.

Example: TE0812 Block Diagram

Note

All created DrawIOs should be named according to the Module name:

Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD

Scroll Title

anchor	Figure_OV_BD
title-alignment	center
title	AM0010 block diagram

Scroll Ignore

draw.io Diagram

border	true

diagramName	AM0010_OV_BD
simpleViewer	true
width
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tbstyle	top
diagramDisplayName
lbox	true
diagramWidth	691
revision	7

Scroll Only

Main Components

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Notes :

Picture of the PCB (top and bottom side) with labels of important components
Add List below

Note
For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .

Scroll Title

anchor	Figure_OV_MC
title-alignment	center
title	AM0010 main components

Scroll Ignore

draw.io Diagram

border	true

diagramName	Figure_OV_MC
simpleViewer	true
width
links	auto
tbstyle	top
diagramDisplayName
lbox	true
diagramWidth	720
revision	3

Scroll Only

FPGA, U1
DDR4, U2, U3, U9, U12, U14
eMMC, U17
Quad SPI Flash, U6, U7
Connector, J5, J6
Ethernet Transceiver, U8
HyperFlash, U16
EEPROM, U15
OPTIGA Trust M, U27
CryptoAuthentication, U24
USB Transceiver, U10
Oscillator, U13, U14, U30, U31, U32
Analog Multiplexer, U38
Power Supply, U5, U11, U18, U19, U20, U21, U22, U23, U28
Initial Delivery State
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Note
Only components like EEPROM, QSPI flash can be initialized by default at manufacture.
If there is no components which might have initial data ( possible on carrier) you must keep the table empty

Scroll Title
anchor Table_OV_IDS
title-alignment center
title Initial delivery state of programmable devices on the module
Scroll Table Layout
orientation portrait
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cellHighlighting true
Storage device name
Content
Notes
DDR4 SDRAM not programmed
eMMC not programmed
Quad SPI Flash not programmed
HyperFlash
not programmed

EEPROM not programmed besides factory programmed MAC address

Signals, Interfaces and Pins
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For subsection examples see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-Signals,InterfacesandPins
Note
Table with all connectors and Designtor
List of different interfaces per connector
IO CNT (for FPGA IOs where functionality can be changed by customer)

Connectors
Scroll Title
anchor Table_SIP_C
title-alignment center
title Board Connectors
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Connector Type Designator Interface IO CNT ¹⁾ Notes
B2B J5 HP 104 SE / 48 DIFF
B2B J5 MGT PL 4 x MGT (RX/TX)
B2B J5 MGT PL 2 x MGT CLK
B2B J5 HD 24 SE / 12 DIFF
B2B J6 HP 52 SE / 24 DIFF
B2B J6 MGT PS 4 x MGT (RX/TX)
B2B J6 MGT PS 2 x MGT CLK
B2B J6 HD 24 SE / 12 DIFF
B2B J6 MIO 2 x I2C
B2B J6 MIO 2 x UART
B2B J6 MIO 2 x PERST
B2B J6 MIO SDIO
B2B J6 MIO JTAG
B2B J6 MIO 4 x GPIO
B2B J6 ETH

B2B J6 USB

¹⁾ IO CNT depends on assembly variant. E.g. the MGTs are not available for all FPGAs

Test Points
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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.
Example:
Test Point Signal B2B Notes
10 PWR_PL_OK J2-120

Scroll Title
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title-alignment center
title Test Points Information
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Test Point Signal Notes
TP1 PROG_B# pulled-up to V_IO_CFG
TP2 VTT
TP3 VTT
TP4 VREFA
TP5 VREFA
TP6 0.85V
TP7 0.85V
TP8 DDR_1V2
TP9 DDR_1V2
TP10 MGTAVCC
TP11 MGTAVCC
TP12 DDR_2V5
TP13 DDR_2V5
TP14 PL_VCU_0V9
TP15 PL_VCU_0V9
TP16 1.8V
TP17 1.8V
TP18 3.3V_SEQ
TP19 3.3V_SEQ
TP20 3.3V
TP21 3.3V

On-board Peripherals
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Notes :
In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection
Example:
Chip/Interface Designator Connected To Notes
ETH PHY U10
B2B connector J1
SoC MIO
Gigabit ETH PHY

Scroll Title
anchor Table_OBP
title-alignment center
title On board peripherals
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Chip/Interface Designator Connected To Notes
DDR4 SDRAM
U2, U3, U9, U12, U14 SoC - PS
eMMC
U17 SoC - PS
Quad SPI Flash
U6, U7 SoC - PS Booting.
Gigabit Ethernet Transceiver
U8 SoC - PS
HyperFlash
U16 SoC - PL
EEPROM
U15 SoC - PS
OPTIGA Trust M
U27 SoC - PS
CryptoAuthentication
U24 SoC - PS
USB 2 Transceiver
U10 SoC - PS
Oscillator
U13 SoC - PS 135 MHz
Oscillator
U14 SoC - PS 100 MHz
Oscillator
U30 ETH PHY 25 MHz
Oscillator
U31 USB PHY 24 MHz
Oscillator
U32 SoC 33 MHz
Analog Multiplexer
U38 SoC Voltage measuring with Xilinx internal ADC.

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For example subsections see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-On-boardPeripherals

Configuration and System Control Signals
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Overview all Controller signals, like Reset, Boote Mode, JTAG Interface(Connector or USB In case of FTDI)...
In case it's connected to CPLD always link to CPLD description and add not from the current implementation here(in case it's available)

Scroll Title
anchor Table_OV_CNTRL
title-alignment center
title Controller signal.
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Connector.Pin
Signal Name
Direction¹⁾ Description
J6.A59 V_BAT IN Input voltage for VCC_PSBATT ^{2) 3)}.
J6.B58 RST_M2C# OUT Module reset for baseboard peripheral reset.
J6.C53 DONE OUT FPGA Signal PS_DONE -signal ²⁾.
J6.C54 MODE0 IN Boot mode selection / J6.C55 MODE1 IN Boot mode selection / J6.C56 MODE2 IN Boot mode selection / J6.C57 MODE3MODE0..3 IN Boot mode selection ²⁾:
JTAG
QUAD-SPI (32 Bit)
SD1 (2.0)
eMMC (1.8 V)
SD1 LS (3.0)
Supported Modes depends also on used Carrier.
J6.C58 PS_SRST# INFPGA system reset SoC Soft Reset ²⁾.
J6.C59 PS_POR# IN
SoC Power-on-
reset status
reset ²⁾.
PWR_GOOD deasserts module reset.
J6.D56 / J6.D57 DX_P / DX_N IN
Temperature sensing diode pin
J6
.
D57 DX_N IN
When not used, tie to GND.
Temperature sensing diode pin
J6.D58 PWR_EN IN / OUT
Power Enable
(Do not tie "PWR_EN" to VDD directly.
This signal could be tied to GND within
this module.). Controlled module internally. Can be used to delay power on sequencing or disable power. Tie only to GND or leave floating.
J6.D59 PWR_GOOD OUT Power good status
¹⁾ Direction:
IN: Input from the point of view of this board.
OUT: Output from the point of view of this board
.
J6.D51 / J6.D52 / J6.D54 / J6.D55 TDI/TCK/TDO/TMS Signal-dependent
JTAG configuration and debugging interface.
JTAG reference voltage: V_IO_CFG
LED D1 / D2 ERR_STATUS / ERR_OUT --- PS_STATUS_ERROR_OUT / PS_ERROR_OUT ²⁾.
¹⁾ Direction:
IN: Input from the point of view of this board.
OUT: Output from the point of view of this board.
²⁾ See UG1085 for additional information.
³⁾ See Recommended Operating Conditions.
Power and Power-On Sequence
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Enter the default value for power supply and startup of the module here.
Order of power provided Voltages and Reset/Enable signals
Link to Schematics, for power images or more details

Power Rails
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List of all Powerrails which are accessible by the customer
Main Power Rails and Variable Bank Power

Scroll Title
anchor Table_PWR_PR
title-alignment center
title Module power rails.
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orientation portrait
sortDirection ASC
repeatTableHeaders default
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cellHighlighting true

Power Rail Name/ Schematic Name Connector.Pin Direction¹⁾ Notes
V_MOD1 J5.A7 / J5.A15 / J5.A47 / J5.A55 / J5.B5 / J5.B11 / J5.B17 / J5.B45 / J5.B51 / J5.B57 / J6.C5 / J6.C11 / J6.C17 / J6.D7 / J6.D15 IN
1.8V J5.C7 / J5.C15 / J6.B7 / J6.B15 OUT
V_IO_W01 J5.D3 / J5.D17 IN
V_IO_W3 J5.D40 IN
V_IO_W45 J5.D43 / J5.D57 IN
V_IO_X01 J6.A3 / J6.A17 IN
V_BAT J6.A59 IN
V_IO_X3 J6.B35 IN
3.3V J6.B59 OUT
V_IO_CFG J6.C52 IN
¹⁾ Direction:
IN: Input from the point of view of this board.
OUT: Output from the point of view of this board.
Baseboard Design Hints (needs to be updated)

Recommended Power up Sequencing
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List baseboard design hints for final baseboard development.

-
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title Baseboard Design Hints
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Sequence Net name Recommended Voltage Range Pull-up/down Description Notes
0 - - - Configuration signal setup. See Configuration and System Control Signals.
1 ¹⁾ V_BAT 3.3 V
Priority Net name Voltage Range Pull-up/down Description Notes Pin
Preparation TDI/TCK/TDO/TMS V_IO_CFG - JTAG interface. J6.D51, J6.D52, J6.D54, J6.D55
Preparation MODE0...3 V_IO_CFG - Boot mode setup. Do not float.
Hardwiring possible. Consider debug options. Boot Mode options are descriped in AMD Xilinx documentation.
J6.C54, J6.C55, J6.C56, J6.C57
Preparation DX_P / DX_N - -
MPSoC temperature measurement.
When not used, tie to GND.
J6.D56, J6.D57 1 V_BAT
- Battery connection. Battery Power Domain usage. When not used, tie to GND
.Battery Power Domain usage
.
J6.A59
2 V_MOD1
-
12 V - Main Power supply.
Main module power supply.
see table "Module Power Rails"
3 A recommended. Power consumption depends mainly on design and cooling solution.
3 ¹⁾
3
PWR_EN -
PU ²⁾, 3.3 V

(on module)
Power
enable
release.
(Do not tie "PWR_EN" to VDD directly.
This signal could be tied to GND within
this module.)J6.D58
Controlled module internally. Can be used to delay power on sequencing or disable power. Tie only to GND or leave floating.
4
43.3V / 1.8V--Module generated voltages.see table "Module Power Rails"5
PWR_GOOD -
PU ²⁾, 3.3 V

(on module)
Power good status.
J6.D596V_IO_W01 / V_IO_W45 / V_IO_X01 / V_IO_W3 / V_IO_X3 / V_IO_CFG
Module power on sequencing finished. Periphery and variable bank voltages can be enabled on carrier.
5 ¹⁾ 3.3V / 1.8V - -
Module
bank
generated output voltages.
see table "Module Power Rails"
Voltages are available after PWR_GOOD deassertion.
These voltages can be used
to supply bank voltages,
to supply periphery and/or
as power good signal to enable external power regulators.
Important: Consider maximum power consumption.
5
V_IO_W01 / V_IO_W45 / V_IO_X01 / V_IO_W3 / V_IO_X3 /
7DONEV_IO_CFGPU, V_IO_CFG
(on module)PL configuration monitoring.This signal states the PL configuration according to AMD Xilinx documentation.J6.C537PS_SRST#V_IO_CFG
PU, V_IO_CFG
(on module)
Module reset.This signal initiate a system reset according to AMD Xilins documentation.J6.C588PS_POR#V_IO_CFGPU,
V_IO_CFG
(on module
³⁾
Power-on reset.Needs to held at zero until all PS power supplies meet voltage requirements and the PS_CLK reference is within specification. When deasserted the PS begins the boot process.J6.C598RST_M2C#V_IO_CFG
PU, 3.3 V
(on module)
Baseboard peripheral reset.This signals resets module peripheral and can / should be used for baseboard peripheral reset.J6.B58
- Module bank voltages. Enable bank voltages after PWR_GOOD deassertion. To achieve minimum current draw and ensure that the I/Os are 3-stated at power-on it is recommended to enable bank voltages before or at the same time as external logic,
6 ¹⁾ - - - Reset handling.
RST_M2C# delivers external periphery reset. See Configuration and System Control Signals.

¹⁾ (optional)

²⁾ (on module)

³⁾ See DS925 for additional information.

Board to Board Connectors

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This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series,
For example: 6 x 6 SoM LSHM B2B Connectors
Include Page
https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=139253650&moved=true
https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=139253650&moved=true

Include Page

	Andromeda ADM6/ADF6 B2B Connectors
	Andromeda ADM6/ADF6 B2B Connectors

Technical Specifications

**Absolute Maximum Ratings ^*)**

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title	AM0010 absolute maximum ratings

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Power Rail Name/ Schematic Name	Description	Min	Max	Unit
V_MOD1	Main input power supply	-0.3	18	V
V_IO_W01	HP FPGA Bank 65 voltage	-0.500	2.000	V
V_IO_W3	HD FPGA Bank 24 voltage	-0.500	3.400	V
V_IO_W45	HP FPGA Bank 64 voltage	-0.500	2.000	V
V_IO_X01	HP FPGA Bank 66 voltage	-0.500	2.000	V
V_BAT ¹⁾	FPGA Battery Voltage		6	V
V_IO_X3	HD FPGA Bank 24 voltage	-0.500	3.400	V
V_IO_CFG	PS FPGA Bank 501 and 503 Voltage	-0.3	3.630	V

¹⁾ It is possible to use a resistor instead of the LDO but then, consider the different min (-0.500 V) / max (2.000 V) values.

^*) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

Recommended Operating Conditions
This TRM is generic for all variants. Temperature range can be differ depending on the assembly version. Voltage range is mostly the same during variants (exceptions are possible, depending on custom request)

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Variants of modules are described here: Article Number Information
Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C
Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C
The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.

Scroll Title
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Parameter Min Max Units Reference Document
V_MOD1 4.5 16 V See TPS54A24 and FS1406 datasheets.
V_IO_W01 0.950 1.900 V See FPGA datasheet.
V_IO_W3 1.140 3.400 V See FPGA datasheet.
V_IO_W45 0.950 1.900 V See FPGA datasheet.
V_IO_X01 0.950 1.900 V See FPGA datasheet.
V_BAT ¹⁾ 2.0 5.5 V See AP7354D datasheet.
V_IO_X3 1.140 3.400 V See FPGA datasheet.
V_IO_CFG 1.710 3.465 V See FPGA datasheet.
¹⁾ Using a resistor instead of the LDO is possible which leads to different min (1.2 V) / max (1.89 V) values.
Physical Dimensions
Module size: 56.4 mm × 40 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 5 mm.
PCB thickness: 2 mm.
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In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.
For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:
https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF
Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

Scroll Title
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title Physical Dimension

Scroll Ignore

draw.io Diagram
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diagramWidth 626
revision 2

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scroll-eclipsehelp true
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scroll-html true

Currently Offered Variants
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Set correct link to the shop page overview table of the product on English and German.
Example for TE0706:
ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706
DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706

Scroll Title
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title Trenz Electronic Shop Overview
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Trenz shop AM0010 overview page
English page German page

Revision History
Hardware Revision History
Page properties
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id Comments
Set correct links to download Carrier, e.g. TE0706 REV02:
TE0706-02 -> https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents
Note:
Date format: YYYY-MM-DD
Example:
Date Revision Changes Documentation Link
2020-11-25 REV02
Resistors R14 and R15 was replaced by 953R (was 5K1)
Resistor R5 was replaced by 5K1, R8 by 953R (was 9K09 and 1K69 respectively)
REV02

Scroll Title
anchor Figure_RV_HRN
title-alignment center
title Board hardware revision number.

Scroll Ignore

draw.io Diagram
border true
diagramName Figure_RV_HRN
simpleViewer true
width
links auto
tbstyle top
diagramDisplayName
lbox true
diagramWidth 223
revision 1

Scroll Only
scroll-viewport true
scroll-pdf true
scroll-office true
scroll-chm true
scroll-docbook true
scroll-eclipsehelp true
scroll-epub true
scroll-html true

Scroll Title
anchor Table_RH_HRH
title-alignment center
title Hardware Revision History
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orientation portrait
sortDirection ASC
repeatTableHeaders default
style
widths
sortByColumn 1
sortEnabled false
cellHighlighting true
Date Revision Changes Documentation Link
- REV01 First Production Release REV01

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Document Change History
Page properties
hidden true
id Comments
Note this list must be only updated, if the document is online on public doc!
It's semi automatically, so do following
Add new row below first
Copy "Page Information Macro (date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template
Metadata is only used of compatibility of older exports

Scroll Title
anchor Table_RH_DCH
title-alignment center
title Document change history.
Scroll Table Layout
orientation portrait
sortDirection ASC
repeatTableHeaders default
style
widths
sortByColumn 1
sortEnabled false
cellHighlighting true
Date Revision Contributor Description
Page info
infoType Modified date
dateFormat yyyy-MM-dd
type Flat
Page info
infoType Current version
prefix v.
type Flat
showVersions false
Page info
infoType Modified by
type Flat
showVersions false
Recommended Power up Sequencing modified

v.42
ED
Initial Document
--
all
Page info
infoType Modified users
type Flat
showVersions false
--

Disclaimer
Include Page
IN:Legal Notices
IN:Legal Notices

Scroll Only

HTML
<style> .wiki-content .columnLayout .cell.aside { width: 0%; }</style>

Scroll pdf ignore

Custom_fix_page_content

Trenz Electronic Documentation

Versions Compared

Old Version 35

New Version Current

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