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Table of Contents
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| # | FTDI Channel A | FTDI Channel B | Pins A to G | Notes | |
|---|---|---|---|---|---|
| 1 | JTAG/SPI (MPSSE) | UART | JTAG, UART | JTAG compatible to Xilinx, Lattice and open-source software that uses FTDI MPPSE | |
| 2 | JTAG/SPI (MPSSE) | JTAG/SPI (MPSSE) | JTAG, JTAG | Dual JTAG, only Channel A is Xilinx compatible | |
| 3 | UART | UART | UART, UART | Dual UART | |
| 4 | I2C | UART | I2C, UART | ||
| 5 | MPSSE | 8x GPIO | |||
| 6 | UART | 8x GPIO | |||
| 7 | UART | UART | not used | UART to UART loopback | |
| 8 | not used | Fast Serial | FTDI 4-wire fast serial adapter, custom EEPROM is needed to enable this mode | ||
| 9 | CPLD update only | not used | user defined | Standalone Module with CPLD and 8 user programmable I/O |
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| Signal | J2 Pin Name | J2 Pin Name | Signal | ||
|---|---|---|---|---|---|
| GND | 1* | GND | |||
| User Defined | C | A | User Defined | ||
| VIO | VDD 3.3V | ||||
| User Defined | D | B | User Defined | ||
| User Defined | F | E | User Defined | ||
| User Defined | H | G | User Defined / Button (Reset_n) |
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| FTDI | Signal | Pull up/down | J2 Pin Name | J2 Pin Name | Pull up/down | Signal | FTDI | |||
|---|---|---|---|---|---|---|---|---|---|---|
| GND | - | 1* | - | GND | ||||||
| ADBUS0 | TCK (output from adapter) | C | A | up | UART RXD (input to adapter) | BDBUS1 | ||||
| VIO | - | - | VDD 3.3V | |||||||
| ADBUS2 | TDO (input to adapter) | up | D | B | UART TXD (output from adapter) | BDBUS0 | ||||
| ADBUS1 | TDI (output from adapter) | F | E | down | LED | |||||
| ADBUS3 | TMS (output from adapter) | H | G | up | Button (Reset_n) |
Table 4: Pin header J2 signal assignment with standard configuration firmware. *pin 1 on header J2
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| FTDI | Signal | Pull up/down | J2 Pin Name | J2 Pin Name | Pull up/down | Signal | FTDI | |||
|---|---|---|---|---|---|---|---|---|---|---|
| GND | - | 1* | - | GND | ||||||
| ADBUS0 | TCK (output from adapter) | C | A | UART TXD (output from adapter) | BDBUS0 | |||||
| VIO | - | - | VDD 3.3V | |||||||
| ADBUS2 | TDO (input to adapter) | up | D | B | up | UART RXD (input to adapter) | BDBUS1 | |||
| ADBUS1 | TDI (output from adapter) | F | E | down | LED | |||||
| ADBUS3 | TMS (output from adapter) | H | G | up | Button (Reset_n) |
Table 5: Pin header J2 signal assignment with standard, but RXD-TXD swapped configuration firmware. *pin 1 on header J2
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| FTDI | Signal | Pull up/down | J2 Pin Name | J2 Pin Name | Pull up/down | Signal | FTDI | |||
|---|---|---|---|---|---|---|---|---|---|---|
| GND | - | 1* | - | GND | ||||||
| BDBUS1 | UART RXD (input to adapter) | up | C | A | TCK (output from adapter) | ADBUS0 | ||||
| VIO | - | - | VDD 3.3 V | |||||||
| BDBUS0 | UART TXD (output from adapter) | D | B | TMS (output from adapter) | ADBUS3 | |||||
| ADBUS1 | TDI (output from adapter) | F | E | up | TDO (input to adapter) | ADBUS2 | ||||
| not used | H | G | CPLD User LED 'ULED' |
Table 6: Pin header J2 signal assignment with DIPFORTy firmware.
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| S2-3 | S2-4 | 3.3V (VCC) Pin 5 | VIO Pin 6 | Description |
|---|---|---|---|---|
| OFF | OFF | 3.3V from base (input**) | VIO from base (input**) | 3.3V (pin 5) and VIO (pin 6) sourced from base |
| OFF | ON | 3.3V from USB* (output**) | VIO from base (input**) | VIO sourced from base by Pin 6 |
| ON | OFF | 3.3V from base (input**) | 3.3V from base (input**) | VIO and 3.3V source by base (Pin 5 and Pin 6 are shorted and both must be sourced by 3.3V) |
| ON | ON | 3.3V from USB* (output**) | 3.3V from USB* (output**) | 3.3V (pin 5) and VIO (pin 6) sourced USB ( (Pin 5 and Pin 6 are shorted and both are 3.3V) |
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- *max. 100mA for external components (
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- It'
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- s not recommended to supply FPGA Module)
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Attention: Do not use this setting, if base power supply is connected to this pins! For more details see Power supply of the adapter board section.- **view of XMOD
Table 8: DIP-switch S2 power setting description.
User User Push Button
The user push button S1 directly connected to the SC CPLD manipulates pin G of the pin header J2 by driving it to GND.
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Date | Revision | Contributors | Description | ||||||||||||||||||||||||||
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2018-01-18 | v.37 | John Hartfiel |
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| 2017-11-16 | v.34 | Ali Naseri |
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2017-10-26 | v.27 | John Hartfiel |
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| 2017-10-19 | v.26 | Ali Naseri |
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| -- | all |
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Table 15: Document change history.
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| Include Page | ||||
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