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Table of Contents

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#FTDI
Channel A		FTDI
Channel B		Pins A to GNotes
1JTAG/SPI (MPSSE)UARTJTAG, UARTJTAG compatible to Xilinx, Lattice and open-source software that uses FTDI MPPSE
2JTAG/SPI (MPSSE)JTAG/SPI (MPSSE)JTAG, JTAGDual JTAG, only Channel A is Xilinx compatible
3UARTUARTUART, UARTDual UART
4I2CUARTI2C, UART 
5MPSSE 
8x GPIO 
6 
UART8x GPIO 
7UARTUARTnot usedUART to UART loopback
8not usedFast Serial 
FTDI 4-wire fast serial adapter, custom EEPROM is needed to enable this mode
9CPLD update onlynot useduser definedStandalone Module with CPLD and 8 user programmable I/O

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Signal J2 Pin NameJ2 Pin Name Signal
GND
1*GND
User DefinedCAUser Defined
VIO 

VDD 3.3V
User DefinedDBUser Defined
User DefinedFEUser Defined
User DefinedHGUser Defined / Button (Reset_n)

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FTDISignalPull up/down J2 Pin NameJ2 Pin Name Pull up/downSignalFTDI

GND-
1*-GND
ADBUS0TCK (output from adapter)
CAupUART RXD (input to adapter)BDBUS1 

VIO- 

-VDD 3.3V 
ADBUS2TDO (input to adapter)upDB
UART TXD (output from adapter)BDBUS0
ADBUS1TDI (output from adapter)
FEdownLED
ADBUS3TMS (output from adapter)
HGupButton (Reset_n)

Table 4: Pin header J2 signal assignment with standard configuration firmware. *pin 1 on header J2

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FTDISignalPull up/down J2 Pin NameJ2 Pin Name Pull up/downSignalFTDI

GND-
1*-GND
ADBUS0TCK (output from adapter)
CA
UART TXD (output from adapter)BDBUS0 

VIO- 

-VDD 3.3V
ADBUS2TDO (input to adapter)upDB upUART RXD (input to adapter)BDBUS1
ADBUS1TDI (output from adapter)
FEdownLED
ADBUS3TMS (output from adapter) 
HHGupButton (Reset_n)

Table 5: Pin header J2 signal assignment with standard, but RXD-TXD swapped configuration firmware. *pin 1 on header J2

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FTDISignalPull up/down J2 Pin Name J2 Pin NamePull up/downSignalFTDI

GND-
1*-GND
BDBUS1UART RXD (input to adapter)upCA
TCK (output from adapter)ADBUS0 

VIO- 

-VDD 3.3 V
BDBUS0UART TXD (output from adapter)
DB
TMS (output from adapter)ADBUS3
ADBUS1TDI (output from adapter)
FEupTDO (input to adapter)ADBUS2 

not used
HG 
CPLD User LED 'ULED'

Table 6: Pin header J2 signal assignment with DIPFORTy firmware.

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S2-3S2-43.3V (VCC) Pin 5VIO Pin 6Description
OFFOFF3.3V from base (input**)VIO from base (input**)3.3V (pin 5) and VIO (pin 6) sourced from base
OFFON3.3V from USB* (output**)VIO from base (input**)VIO sourced from base by Pin 6
ONOFF3.3V from base (input**)3.3V from base (input**)VIO and 3.3V source by base (Pin 5 and Pin 6 are shorted and both must be sourced by 3.3V)
ONON3.3V from USB* (output**)3.3V from USB* (output**)

3.3V (pin 5) and VIO (pin 6) sourced USB ( (Pin 5 and Pin 6 are shorted and both are 3.3V)

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Date

Revision

Contributors

Description

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modified-date
modified-date
dateFormatyyyy-MM-dd

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infoTypeCurrent version
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infoTypeModified by
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  • update some link and change history

2018-01-18

v.37John HartfielAli Naseri
  • DIP-Switch description
2017-11-16

v.34

Ali Naseri
  • Updated Power supply, DIP-Switch and CPLD section

2017-10-26

v.27

John Hartfiel
  • Update 2x6 Pin Header Figure 3
  • Update Links
2017-10-19

v.26

Ali Naseri
  • Initial document
--all


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Table 15: Document change history.

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