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- FPGA: Xilinx Artix 7 (XC7A100T)
- Package: FGG484 (Compatible with
- Speed: -1 (Slowest)
- Temperature: Industrial Grade (–40°C to +100°C)
- RAM/Storage:
- 1x NOR SPI FLASH (128M x 4)
- 1x EEPROM (16K x 8)
- On Board:
- 4x Deserializer IC (3.12 Gbps)
- 4x I2C and SMBus I/O Expander
- 1x Programable Clock Generator
- 1x Clock Generator
- Interface:
- 2x VITA 57 SEAM/SEAF Series
- 4x Coaxial Connectors
- Power:
- 4x Voltage Regulators
- 3.3 Supply Voltage
- Dimension:
Block Diagram
| Page properties |
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add drawIO object here.
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| Scroll Title |
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| anchor | Figure_OV_BD |
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| title | TEF0003 block diagram |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| fitWindow | false |
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| diagramDisplayName | |
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| lbox | true |
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| revision | 1012 |
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| diagramName | TEF0003_OV_BD |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| diagramWidth | 641 |
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| Scroll Only |
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 Image Modified
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Main Components
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| Scroll Title |
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| anchor | Figure_OV_MC |
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| title | TEF0003 main components |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| fitWindow | false |
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| diagramDisplayName | |
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| lbox | true |
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| revision | 7 |
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| diagramName | TEF0003_OV_MC |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| diagramWidth | 641 |
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| Scroll Only |
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 Image Modified
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- Coaxial Connectors, J2-5
- SPI Flash, U9
- Xilinx Artix 7 FPGA, U1
- Lattice MachXO FPGA, U15
- FMC Adapter, J1
- EEPROM, U4
- I2C Switches, U2, U17-20
- Jumper, J7
- Serializer, U5-8
- Connector Header, J8
- Oscillator 25MHz, U11
- Programmable Clock Generator, U10
- FMC Adapter, J6
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| Scroll Title |
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| anchor | Table_OV_RST |
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| title | Reset Process. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Signal | Description | Note |
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PRSNT_TOP | Lattice MachXO Configuration Pin |
| | PROG_B | Artix 7 Configuration Pin | Connected Pulled up to 1.8 |
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Signals, Interfaces and Pins
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| Scroll Title |
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| anchor | Table_SIP_FMC |
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| title | General PL I/O to FMC Connectors information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| FPGA | FPGA Bank | Connector Designator | I/O Signal Count | Voltage Level | Notes |
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| Artix 7, U1 | 16 | J1B | 68 Single Ended, 34 Differential | 1.8V |
| | 35 | J6B | 68 Single Ended, 34 Differential | 1.8V |
| | Lattice MachXO, U | 0 | J1F | 4 Single Ended | 3.3V | CPLD | | 0 | J6F | 4 Single Ended | 3.3V | CPLD |
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Coaxial Connectors
The Lattice MachXO (U15) is available to meet the requirement of a CPLD, JTAG access to the MachXO is available through FMC Adapter J6. JTAG access to the Artix 7(U1) is available via MachXO, Bank 2.
| Scroll Title |
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| anchor | Table_SIP_CPLDJTGCoaxial |
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| title | CPLD JTAG pins connectionCoaxial Connectors information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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JTAG Signal| Designator | Schematic | Connected to | Notes |
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| J2 | GA_OUT | Serializer, U5 |
| | J3 | GB_OUT | Serializer, U6 |
| | J4 | GC_OUT | Serializer, U7 |
| | J5 | GD_OUT | Serializer, U8 |
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JTAG Interface
The Lattice MachXO (U15) is available to meet the requirement of a CPLD, JTAG access to the MachXO is available through FMC Adapter J6. JTAG access to the Artix 7(U1) is available via MachXO, Bank 2.
| Scroll Title |
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| anchor | Table_SIP_CPLDJTG |
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| title | CPLD JTAG pins connection |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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JTAG Signal | B2B Connector | Notes |
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| FMC |
B2B Connector | FMC| _TMS | J6F-TCK |
| | FMC_TDI_TOP | J6F-J1-TDI |
| | FMC_TDO_TOP | J6F-TDO |
| | FMC_TCK | J6F-TCK |
| | JTAGEN |
J7
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| Scroll Title |
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| anchor | Table_SIP_JTG |
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| title | JTAG pins connection |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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JTAG Signal | Connected to | Note |
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| TMS | Lattice MachXO, U15 BankArtix 7 FPGA, U1 | Bank 2 Bank 0 | | TDI | Lattice MachXO, U15 Artix 7 FPGA, U1 | Bank 2 Bank 0 | | TDO | Lattice MachXO, U15 Artix 7 FPGA, U1 | Bank 2 Bank 0 | | TCK | Lattice MachXO, U15 Artix 7 FPGA, U1 | Bank 2 Bank 0 | | INIT | Artix 7 FPGA, U1 | Connected Pulled up to 1.8 |
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On-board Peripherals
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| Scroll Title |
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| anchor | Table_OBP |
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| title | On board peripherals |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Quad SPI Flash Memory
| Page properties |
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
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| Scroll Title |
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| anchor | Table_OBP_EEP |
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| title | I2C EEPROM interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| U4 Pin | FMC Pcam Adapter | Schematic |
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U4 PinNotesSCLSDA | J1F-GA0 | GA0 | A0 | |
| | A0 | J1F-GA0 | GA0 |
| | A1 | J1F-GA1 | GA1 |
| | A2 | - | - | Pulled Low | | WP | - | - | Pulled Low |
J1F-GA1 | GA1 | A1
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| Scroll Title |
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| anchor | Table_OBP_I2C_EEPROM |
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| title | I2C address for EEPROM |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| I2C Address | Designator | Notes |
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0x50| 0xA0 | U4 | Write operations are enabled |
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Clock Sources
| Scroll Title |
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| anchor | Table_OBP_CLK |
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| title | Osillators |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Designator | Description | Frequency | Note |
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| U4U11 | Oscillator | 25 MHz.00 MHz |
| | U10 | Programmable Clock Generator | Variable |
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There is a Silicon Labs I2C programmable clock generator on-board (U10) in order to generate reference clocks for the module. Programming can be done using I2C via PIN header J8. The I2C Address is 0x69.
| Scroll Title |
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| anchor | Table_OBP_PCLK |
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| title | Programmable Clock Generator Inputs and Outputs |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Si5345A Pin
| Signal Name / Description
| Connected To | Direction | Note |
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IN0 | Reference input clock. | U11 | Input | 25.00 MHz oscillator, SiT8008BI | | IN1 | FMCT_GBTCLK0 | J6E | Input | FMC Pcam Adapter | | IN2 | FMCT_GBTCLK1 | J6E | Input | FMC Pcam Adapter | | IN3 | FMCT_CLK0 | J6E | Input | FMC Pcam Adapter | XAXB | - | GND | Input | 54.0000 00 MHz XTAL CX3225SB | | SCLK | PLL_SCL | J8, U20 | Input | EEPROM Programming | | SDA | PLL_SDA | J8, U20 | Input | EEPROM Programming | | OUT0 | GA_PCLK | U5/U1 | Output | FPGA bank 15 | | OUT1 | GB_PCLK | U6/U1 | Output | FPGA bank 15 | | OUT2 | GC_PCLK | U7/U1 | Output | FPGA bank 15 | | OUT3 | GD_PCLK | U8/U1 | Output | FPGA bank 15 | | OUT4 | CLK4_P | U1H | Output |
| | OUT5 | GBTCLK0 | J1E/J6E | Output |
| | OUT6 | GBTCLK1 | J1E/J6E | Output |
| | OUT7 | GBTCLK0 | J1E | Output |
| | OUT8/OUT9 | CLK8/CLK9 | Pulled low | Output |
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| Scroll Title |
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| anchor | Table_PWR_PC |
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| title | Power Consumption |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Power Input Pin | Typical Current |
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| VIN3P3V | TBD* |
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* TBD - To Be Determined
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| Scroll Title |
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| anchor | Figure_PWR_PD |
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| title | Power Distribution |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| fitWindow | false |
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| diagramDisplayName | |
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| lbox | true |
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| revision | 57 |
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| diagramName | TEF0003_PWR_PD |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| diagramWidth | 641 |
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| Scroll Only |
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 Image Modified
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Power-On Sequence
| Scroll Title |
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| anchor | Figure_PWR_PS |
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| title | Power Sequency |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| fitWindow | false |
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| diagramDisplayName | |
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| lbox | true |
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| revision | 2 |
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| diagramName | TEF0003_PWR_PS |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| diagramWidth | 641 |
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| Scroll Only |
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 Image Modified
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Power Rails
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| Scroll Title |
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| anchor | Table_TS_AMR |
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| title | PS absolute maximum ratings |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Symbols | Description | Min | Max | Unit |
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| 12V3P3V | Input Supply Voltage | -12120.5 | 3.75 | V | | T_STG | Storage Temperature | -40 | 85 | °C |
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Recommended Operating Conditions
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| Scroll Title |
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| anchor | Table_TS_ROC |
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| title | Recommended operating conditions. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Parameter | Min | Max | Units | Reference Document |
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12V12 | 12| 2.375 | 3.465 | V |
| | T_OPR | -40 | 85 | °C | See MT25QU512ABB8E12-0SIT (U9) datasheet. |
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Physical Dimensions
Module size: 84 mm × 65 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 10 mm.
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| Scroll Title |
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| anchor | Figure_TS_PD |
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| title | Physical Dimension |
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| fitWindow | false |
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| diagramDisplayName | |
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| lbox | true |
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| revision | 25 |
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| diagramName | TEF0003_TS_PD |
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| aspect | 5e705185-5827-752c-089d-756568e6698b |
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| simpleViewer | false |
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| width | 639 |
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| aspectHash | 7695f7bc00c98da1082cb1c11a0a6258edf875fc |
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| links | auto |
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| tbstyle | hidden |
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| diagramWidth | 436 |
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| Scroll Only |
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| scroll-pdf | true |
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| scroll-office | true |
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| scroll-chm | true |
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| scroll-docbook | true |
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| scroll-eclipsehelp | true |
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| scroll-epub | true |
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| scroll-html | true |
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|  Image Modified
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Currently Offered Variants
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| Scroll Title |
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| anchor | Table_RH_HRH |
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| title | Hardware Revision History |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Date | Revision | Changes | Documentation Link |
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| 2017-06-27 | REV01 | Initial Release | REV01 |
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
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