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Template Revision 2.12

Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM"
Carrier: TRM Name usually "TEB Series Name" +TRM
Example: "TEB0728 TRM"

HTML

<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
<style>
.wrapped{
  width: 100% !important;
  max-width: 1200px !important;
 }
</style>

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Important General Note:

If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

Figure template:

Scroll Title

anchor	Figure_anchorname
title	Text

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, objects are only linked.

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Table template:
- Layout macro can be use for landscape of large tables
Scroll Title
anchor Table_tablename
title Text
Scroll Table Layout
orientation portrait
sortDirection ASC
repeatTableHeaders default
style
widths
sortByColumn 1
sortEnabled false
cellHighlighting true
Example Comment
1 2

The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below
- <type>_<main section>_<name>
  - type: Figure, Table
  - main section:
    - "OV" for Overview
    - "SIP" for Signal Interfaces and Pins,
    - "OBP" for On board Peripherals,
    - "PWR" for Power and Power-On Sequence,
    - "B2B" for Board to Board Connector,
    - "TS" for Technical Specification
    - "VCP" for Variants Currently in Production
    - "RH" for Revision History
  - name: custom, some fix names, see below
- Fix names:
  - "Figure_OV_BD" for Block Diagram
  - "Figure_OV_MC" for Main Components
  - "Table_OV_IDS" for Initial Delivery State
  - "Table_PWR_PC" for Power Consumption
  - "Figure_PWR_PD" for Power Distribution
  - "Figure_PWR_PS" for Power Sequence
  - "Figure_PWR_PM" for Power Monitoring
  - "Table_PWR_PR" for Power Rails
  - "Table_PWR_BV" for Bank Voltages
  - "Table_TS_AMR" for Absolute_Maximum_Ratings
  - "Table_TS_ROC" for Recommended_Operating_Conditions
  - "Figure_TS_PD" for Physical_Dimensions
  - "Table_VCP_SO" for TE_Shop_Overview
  - "Table_RH_HRH" for Hardware_Revision_History
  - "Figure_RH_HRN" for Hardware_Revision_Number
  - "Table_RH_DCH" for Document_Change_History
Use Anchor in the document: add link macro and add "#<anchorname>
Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>

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Note for Download Link of the Scroll ignore macro:

Link to the base folder of the module (remove de/ or en/ from the URL):
Example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5_Carriers/TE0728/

Scroll Ignore
Download PDF version of this document.

Scroll pdf ignore

Table of Contents

Table of Contents

Overview

The Trenz Electronic TEBA0714 is a carrier for Trenz Electronic module TE0714 which is an industrial grade module integrated with Xilinx Artix 7.

Refer to http://trenz.org/teba0714-info for the current online version of this manual and other available documentation.

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Note:
'description: Important components and connector or other Features of the module
→ please sort and indicate assembly optionsKey Features' must be split into 6 main groups:

FPGA/Module
- Package:
- Speed:
- Temperature:
RAM/Storage
- E.g. SDRAM, SPI
On Board
- E.g. CPLD, PLL
Interface
- E.g. ETH, USB, B2B, Display port
Power
- E.g. Input supply voltage
Dimension

Module:
- Trenz TE0714 ModuleTemperature: -40 to +85 °C
On Board:
- 2 x User LEDs (Red, Green)
- 1 x DONE LED (Red)
Interface:
- 2 x Pin Header 50 Pol. (FPGA Bank I/Os and Power)
- 2x Samtec 100 Pin LSHM Series Connectors
- 1 x XMOD JTAG/UART Adapter (TE0790)
- 1 x Pin Header 16 Pol. (JTAG, MGT-CLK, Boot Mode, XADC, I/O's)
- 1 x Pin Header 10 Pol. (FPGA Bank I/Os and Power)
- 1 x SFP+ Connectors
Power:
- 1 x LDO Regulator
- 3.3V Nominal Power supply
Dimension:
- 46
Dimension: 46
- mm × 75 mm

Block Diagram

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add drawIO object here.

Note
For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .

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Scroll Title

anchor	Figure_OV_BD
title	TEBA0714 block diagram

Scroll Ignore

draw.io Diagram

border	false
viewerToolbar	true

fitWindow	false
diagramDisplayName
lbox	true
revision	912
diagramName	TEBA0714_OV_BD
simpleViewer	false
width
links	auto
tbstyle	hidden
diagramWidth	639

Scroll Only

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SMT pin header, J26
SMT pin header, J27
Board to Board (B2B) Connector, JM1
Board to Board (B2B) Connectorr, JM2
XMOD header, JX1
Voltage Regulator, U1
User Red LED, D2
User Green LED, D1 (Red)
SFP+ Connector, J1
User Red LED, D3
50 - pin header solder pad(Not assembled), J20
16 - pin header solder pad(Not assembled), J3,
10-pin header solder pad(Not assembled), J4
50-pin header solder pad(Not assembled), J17

Initial Delivery State

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Notes :Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.If there is no components which might have initial data ( possible on carrier) you must keep the table empty

Pin headers (not soldered to the board, but included in the package as separate component)

Scroll Title

anchor	Table_OV_IDS
title	Initial delivery state of programmable devices on the module

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
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sortByColumn	1
sortEnabled	false
cellHighlighting	true

Storage device name	Content	Notes
---	---	---

...

Scroll Title

anchor	Table_OV_RST
title	Reset process.

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orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
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sortEnabled	false
cellHighlighting	true

Signal	B2B	Signal State	Note
PROG_B	JM1-94	Active Low	Clear FPGA configuration vand and initiate a new configuration

...

Board to Board (B2B) I/Os

FPGA bank number and number Number of I/O signals and Interfaces connected to the B2B connector:

Scroll Title

anchor	Table_SIP_B2B
title	General PL I/O to B2B connectors information

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
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sortByColumn	1
sortEnabled	false
cellHighlighting	true

B2B Connector	Interface	Number of I/O	Notes
JM1	User I/O	52 Single ended, 27 Differential	-
	MGT lanes	4 Differential, 2 lanes
	MGT reference clock input	2 Single ended, 1 Differential
	JTAG	4 Single ended
	SoM control signals	2 Single ended	'PROG_B', ' DONE'
JM2	User I/O	36 Single ended or 18 differential	-
	SFP+ Interface control signals	8 Single ended
	QSPI interface	6 Single ended
	UART interface	2 Single ended
	User LEDs	2 Single ended	Red, Green
	SoM control signals	1 Single ended	'BOOTMODE'

On-board Pin Header

TEBA0714 is equipped with four pin headers J17, J20, J3 and J4 which are not assembled on the board, in case of need customer can solder the pins and have access to the signals in the following table.

Scroll Title

anchor	Table_SIP_PinHeader
title	General PL I/O to Pin headers information

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
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sortByColumn	1
sortEnabled	false
cellHighlighting	true

Pin Header	Interface	Number of I/O	Notes
J17	User I/O	36 Single ended, 18 Differential	Module FPGA Bank 14
	SPI interface	6 Single ended	-
	Power	4 Single ended	3.3V, V_CFG
J20	User I/O	42 Single ended or 21 differential	Module FPGA Bank 34
	Power	4 Single ended	3.3V, V_CFG
	User LEDs	2 Single ended	Red, Green
	SoM control signals	1 Single ended	'BOOTMODE'
J3	JTAG	4 Single ended
	UART	2 Single ended	B14_L25, B14_L0
	ADC	2 Single ended
	Clock	2 Single ended, 1 Differential
	Power	4 Single ended	3.3V, V_CFG
	Control Signals	2 Single ended	BOOTMODE, PROG_B
J4	User I/O	6 Single ended or 3 differential
J4	Power	2 Single ended	3.3V, 3.3V_OUT

...

V_CFG

Scroll Title

anchor	Table_SIP_JTG
title	JTAG pins connection

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orientation	portrait
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XMOD Header Pin	Schematic	B2B Connector

Connected to

Pin Header	Note
A	B14_L25	JM2-97

B14_L25

J3-4	UART Transfer
B	B14_L0	JM2-99

B14_L0

J3-7	UART Receive
E	BOOTMODE	JM2-100

BOOTMODE

J3-9
G	PROG_B	JM1-94

PROG_B

J3-11
C	TCK	JM1-90

TCK

J3-4
D	TDI	JM1-86

TDI

J3-10
F	TDO	JM1-88

TDO

J3-8
H	TMS	JM1-92

TMS

J3-12
3.3V	3.3V	JM1-97

,99

3.3V

VIO

JM2-53

,99	J3,J4,J17,J20	Nominal Input Voltage
VIO	V_CFG	-	J17-45	Configuration Voltage

Pin Header J17	Pin Header J20	Pin Header J3	Pin Header J4	Direction	Notes
3.3V	99,97	-	5, 46	5, 46	5	5	Input
1.8V	-	18	-	-	-	-	Input

Comes from Module
3.3V_OUT	83	54	-	-	-	6	Output
VCCIO34	61	-

Trenz Electronic Documentation

Versions Compared

Old Version 39

New Version Current

Key

Overview

Block Diagram

Initial Delivery State

Board to Board (B2B) I/Os

On-board Pin Header

SFP+ Connector

SMT Pin

Headers

On-board Peripherals

Power and Power-On Sequence

Power Distribution Dependencies

Board to Board Connectors

Recommended Operating Conditions