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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

      • Figure template:

        Scroll Title
        anchorFigure_anchorname
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables


      • Scroll Title
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        titleText

        Scroll Table Layout
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        ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:

        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages

        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview

        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>


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Note for Download Link of the Scroll ignore macro:


Scroll Ignore

Download PDF version of this document.


Scroll pdf ignore

Table of Contents

Table of Contents

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The Trenz Electronic TE0802 is an evalution modulea development board integrating a Xilinx Zynq UltraScale+ . Other assembly options for the FPGA and the memory chips are available. Please contact us for further information.

Refer to http://trenz.org/te0802-info for the current online version of this manual and other available documentation.

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Notes :

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Note:
 'Key Features' description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

  • MPSoC: Xilinx Zynq   XCZU2CG -1SBVA484E
  • SDRAM: LPDDR4-3733 8Gb 256Mx32 
  •  Xilinx Zynq UltraScale+ MPSoC
    • Package: 1SBVA484E
    • Speed Grade: -1 (Slowest)

    • Temperature Grade: Extended (0 to +100 °C)

  • RAM/Storages:
    • SDRAM: LPDDR4 8Gb 256Mx16x 2 
    • SPI Flash 
    Storages:
    • SPI Flash 256Mb (32M x 8) 133MHz
    • microSD Card
    • M.2 SSD PCIe
    •  133 MHz
    • EEPROMs 2Kb (256 x 8)
    • EEPROMs 4Kb (512 x 8)
  • Display Interfaces: 
    • DisplayPort
    • VGA
    • 4 Digit 7-Segment LED
    • 8 LEDs
  • Audio:
    • 3.5mm Jack (PWM Output)
    • USB JTAG/UART microUSB
    • 1GB Ethernet RJ45
    • USB 3.0 Host (Type A Connector)
    • microSD Card
    • M.2 SSD PCIe
    • 3.5 mm Earphone Jack (PWM Output)
    • Display Port
    • VGA
    • 4 Digit 7-Segment LED Display
    • 8 LEDs
    Input:
    • 5 User Buttons
    • 8 Bit Slide Switches
    • Reset Button
  • User I/O:
    • 2x PMOD Connectors
  • Communication:
    • 1GB Ethernet RJ45
    • USB 3.0 Host (Type A Connector)
  • Debug
    • USB JTAG/UART microUSB2x Pmod Connector
  • Power
    • 5V 5 V +/- 10%
    • ~3.5W5 W
  • Dimension: 100mm x 100mm

Block Diagram

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Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


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Scroll Title
anchorFigure_OV_BD
titleTE0802 Block Diagram


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Main Components

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Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


Note

For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .


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Scroll Title
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titleTExxxx main componentsTE0802 Main Components (Picture shows Revision 01)


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  1. Power Jack, J13
  2. RJ45 Socket, J4
  3. VGA, J7
  4. Push Button (Reset), BTN6
  5. Grove Connector, J5
  6. Undervoltage/Overvoltage Protector, U9
  7. 7-Segment LED, D11
  8. 1x6 Pin Header, J4
  9. 1x8 Pin Header, J2...3
  10. 8x User LEDs (Red), D2...9
  11. 5x User LEDs (Red), D13...17
  12. 5x User Push Buttons, S1 - S3...6
  13. Red LED (CONF_DONE), D10
  14. PSRAM Memory, U3
  15. SDRAM Memory, U10
  16. Voltage Regulator, U4 - U7
  17. AD/DA Converter, U2
  18. 6x Pmod Host Socket, P1...6
  19. Xilinx Zynq UltraScale+ MPSoc, U14
  20. Serial Configuration Memory, U5
  21. 1x10 Pin Header, J1
  22. EEPROM, U15 - U18 - U20
  23. FTDI USB 2 to JTAG/UART Converter, U14
  24. Micro USB 2.0, J10
  25. Push Button (RST_GPIO), S2
  26. Oscillator, U22
  27. Ethernet PHY, U17 - U19
  28. QSPI Flash Memory, U12
  1. Xilinx Zynq UltraScale+ MPSoc, U14
  2. Oscillator, U15, U7, U23, U19, U43
  3. Slide Switch, S1
  4. Headphone Jack, J12
  5. SPI Flash Memory, U16
  6. EEPROM, U2, U18
  7. LPDDR4 SDRAM, U13
  8. DisplayPort, J3
  9. M.2 Key M PCIe x1, U5
  10. Ethernet PHY, U6
  11. RJ45 Socket, J4
  12. Grove Connector, J10
  13. Pmod Host Socket, J5...6
  14. D-Sub Connector, J7
  15. DIP Switch, S7...8
  16. Push Button, BTN1...5
  17. USB Type A, J11
  18. USB 2.0 PHY, U22
  19. microSD Card, J9
  20. FTDI USB 2.0 to JTAG/UART Converter, U17
  21. Micro USB 2.0 Type B, J8
  22. Clock Generator, U8
  23. Clock Generator Programming Connector, J14
  24. 4 Digit 7-Segment LED Display, D9
  25. 8x LEDs (Red), LED0...7
  26. Power Jack, J13
  27. Overvoltage/Undervoltage/Reverse Supply Protector, U12
  28. Power Management Integrated Circuit (PMIC), U1, U9
  29. Power Good LED (Green), D12

Initial Delivery State

...

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Notes :

Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

Image Added


  1. Xilinx Zynq UltraScale+ MPSoc, U14
  2. LPDDR4 SDRAM, U13
  3. M.2 Key M PCIe x1, U5
  4. SPI Flash Memory, U16
  5. EEPROM, U2, U18
  6. Oscillator, U15, U7, U19, U23, U43
  7. Clock Generator, U8
  8. Clock Generator Programming Connector, J14
  9. Grove Connector, J10
  10. Pmod Host Socket, J5...6
  11. Headphone Jack, J12
  12. D-Sub Connector, J7
  13. DisplayPort, J3
  14. RJ45 Socket, J4
  15. Ethernet PHY, U6
  16. USB Type A, J11
  17. USB 2.0 PHY, U22
  18. Micro USB 2.0 Type B, J8
  19. FTDI USB 2.0 to JTAG/UART Converter, U17
  20. microSD Card, J9
  21. Slide Switch, S1
  22. Push Button, BTN1...5
  23. DIP Switch, S7...8
  24. 4 Digit 7-Segment LED Display, D9
  25. 8x LEDs (Red), LED0...7
  26. Power Jack, J13
  27. Overvoltage/Undervoltage/Reverse Supply Protector, U12
  28. Power Management Integrated Circuit (PMIC), U1, U9
  29. Power Good LED (Green), D12

Initial Delivery State

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Notes :

Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty


Scroll Title
anchorTable_OV_IDS
titleInitial Delivery State of Programmable Devices on the Module

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Storage device name

Content

Notes

SPI Flash (U16)

Not programmed


EEPROM (U2)Not programmedExcept Ethernet MAC
EEPROM (U18)Programmed

FTDI Configuration

LPDDR4 SDRAM (U13)Not programmed


Configuration Signals

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  • Overview of Boot Mode, Reset, Enables.

Bootmode signals must be set through DIP Switch S1. 

...

Scroll Title
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titleInitial delivery state of programmable devices on the moduleBoot Process

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Storage device name

Content

Notes

Quad SPI Flash

EEPROMDDR3 SDRAMSystem Controller CPLD

Configuration Signals

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  • Overview of Boot Mode, Reset, Enables.

MODE Signal State

MODE1

S1-2(B)

MODE0

S1-1(A)

Boot Mode

MODE[2:0]=000

OFFOFF

JTAG

MODE[2:0]=001

OFFONnot supported

MODE[2:0]=010

ONOFFQSPI(32 bit)

MODE[2:0]=011

ONONSD0(2.0)


Reset setting is available through Push Button BTN6.

scroll-scroll-title
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titleBoot process.Reset Process

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MODE

Signal

State

Boot Mode
Scroll Title
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titleReset process.
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Signal

B2BI/ONote
Connected toNote

POR_B

BTN6, Push ButtonConnected to nRESET


Signals, Interfaces and Pins

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Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

...

I/Os on Pin Headers and Connectors

FPGA bank number and number of I/O signals connected to the B2B connectorconnectors:

Scroll Title
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FPGA Bank
B2B Connector
Connector I/O Signal CountVoltage LevelNotes

...

JTAG access to the TExxxx SoM through B2B connector JMX.

...

anchorTable_SIP_JTG
titleJTAG pins connection
Bank 503Micro USB, J8 (over FTDI)4 Single Ended3.3 VJTAG
Bank 500Micro USB, J8 (over FTDI)2 Single Ended3.3 VUART
Bank 500Micro SD Card, J97 Single Ended3.3 V
Bank 502ETH RJ45, J4 (over ETH PHY)14 Single Ended1.8 V
Bank 505, 502USB 3.0, J11 (USB2 over USB PHY)2 Differential Pairs, 12 Single Ended-- / 1.8V

Bank 505, 501

SSD M.2, U5

2 Differential Pairs, 5 Single Ended

-- / 3.3 V


Bank 505, 501Display Port Connector, J32 Differential Pairs, 5 Single Ended--/ 3.3 V
Bank 26, 65, 66,D-Sub Host Socket (VGA), J714 Single Ended3.3 V / 1.8 V / 1.8 V
Bank 65Earphone, J123 Single Ended1.8 V
Bank 500Grove Connector, J102 Single Ended3.3 V
Bank 26Pmod Host Socket, J58 Single Ended3.3 V
Bank 26Pmod Host Socket, J6 8 Single Ended3.3 V


Micro SD Card

TE0802 is equipped with a micro SD card connector (J9).

Scroll Title
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titleMicro SD Card Connector Information

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JTAG Signal

...

B2B Connector

...

MIO Pins

you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

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MIO PinConnected toB2BNotes
MIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

J2QSPI
Scroll Title
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titleMIOs pins

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MIO Pin
SchematicConnected to
B2B
Notes

...

SD_DAT0

MIO 13, FPGA Bank 500


SD_DAT1MIO 14, FPGA Bank 500
SD_DAT2MIO 15, FPGA Bank 500
SD_DAT3MIO 16, FPGA Bank 500
SD_CLKMIO 22, FPGA Bank 500
SD_CMDMIO 21, FPGA Bank 500
SD_CDMIO 24, FPGA Bank 500


RJ45 Connector

TE0802 is equipped with a RJ45 connector and an Ethernet PHYs. RJ45 connector J4 is connected to Ethernet PHYs U6.

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titleRJ45 Connector Information
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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs
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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

Designator
Scroll Title
anchorTable_OBP
titleOn board peripherals

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Pin
Chip/Interface
SchematicETH PinNotes

Quad SPI Flash Memory

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

...

anchorTable_OBP_SPI
titleQuad SPI interface MIOs and pins
2PHY_MDI0_PMDIP[0]
3PHY_MDI0_NMDIN[0]
4PHY_MDI1_PMDIP[1]
5PHY_MDI1_NMDIN[1]
6PHY_MDI2_PMDIP[2]
7PHY_MDI2_NMDIN[2]
8PHY_MDI3_PMDIP[3]
9PHY_MDI3_NMDIN[3]


USBs Sockets

TE0802 is equipped with a Micro USB2.0 B connector J8 and a USB3.0 connector J11.

FTDI FT2232 (U17) can be accessed through Micro USB 2.0 B connector (J8) for JTAG (channel A). Channel B is connected to the FPGA and can be used for UART.

Scroll Title
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titleUSB2.0 B Socket Information

Scroll Table Layout

...

scrolltitle
Scroll Title
anchorTable_OBP_RTC
titleI2C interface MIOs and pins

Scroll Table Layout
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MIO
USB2.0 PinSchematic
U? Pin
Connected toNotes
D-
anchorTable_OBP_I2C_RTC
titleI2C Address for RTC
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MIO PinI2C AddressDesignatorNotes

...

D_N

FTDI, U17


D+D_PFTDI, U17
VbusUSB_VBUSGND



Scroll Title
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titleI2C EEPROM interface MIOs and pinsUSB3.0 A Socket Information

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MIO
USB3.0 PinSchematic
U?? Pin
Connected toNotes
scroll
D-
title
anchorTable
USB0_
OBP
D_
I2C_EEPROMtitleI2C address for EEPROM Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueMIO PinI2C AddressDesignatorNotes

...

NUSB PHY, U22
D+USB0_D_PUSB PHY, U22
StdA_SSRX-USB_RX2_NFPGA Bank 505
StdA_SSRX+USB_RX2_PFPGA Bank 505
StdA_SSTX-USB_TX2_NFPGA Bank 505
StdA_SSTX+USB_TX2_PFPGA Bank 505
VBUSVBUSUSB PHY, U22


SSD M.2 Connector

TE0802 is equipped with a SSD M.2 connector (U5).

Scroll Title
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titleOn-board LEDsSSD M.2 Connector Information

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PinSchematic
Color
Connected to
Active LevelNote

DDR3 SDRAM

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Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.

  • Part number: 
  • Supply voltage:
  • Speed: 
  • NOR Flash
  • Temperature: 

Ethernet

Notes
PERn0/SATA-B+

SSD_RX3_N

Pin M22, FPGA Bank 505
PERp0/SATA-B-SSD_RX3_PPin M21, FPGA Bank 505
PERn0/SATA-A+

SSD_TXC3_N

Pin K22, FPGA Bank 505
PERp0/SATA-A-SSD_TXC3_PPin M21, FPGA Bank 505
REFCLKN

SSD_RCLK_N

Pin 9, Clock Generator U8
REFCLKPSSD_RCLK_PPin 10, Clock Generator U8
DAS/DSS#SSD_DASMIO35, FPGA Bank 501
DEVSLPSSD_SLEEPMIO32, FPGA Bank 501
PERST#SSD_PERSTnMIO31, FPGA Bank 501
CLKREQ#SSD_CLKRQMIO33, FPGA Bank 501
PEWake#SSD_WAKEMIO34, FPGA Bank 501


Display Port Connector

TE0802 is equipped with a Display Port connector (J3).

Scroll Title
anchorTable_SIP_DP
titleDisplay Port Socket Information
Scroll Title
anchorTable_OBP_ETH
titleEthernet PHY to Zynq SoC connections

Scroll Table Layout
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Bank
Schematic
Signal NameETH1ETH2Signal Description

CAN Transceiver

...

anchorTable_OBP_CAN
titleCAN Tranciever interface MIOs
Corresponding SignalsConnected toNotes
DP_TX_L0_P/NDP0_TX_P/NPin A19/A20, FPGA Bank 505
DP_TX_L1_P/NDP1_TX_P/NPin C19/C20, FPGA Bank 505
DP_TX_AUX_P/NDP_AUX_TX/RXMIO27, MIO30, FPGA Bank 501


D-Sub Connector

TE0802 is equipped with a D-Sub connector (J7).

...

Scroll Title
anchorTable_OBPSIP_CLKVGA
titleOsillatorsD-Sub Connector Information

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Designator
Schematic
Description
Corresponding Signals
Frequency
Connected to
Note
Notes
MHzMHzKHz

Power and Power-On Sequence

...

hiddentrue
idComments

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit
Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

VGA_REDVGA_R0...3Bank 65Red Channel
VGA_GREENVGA_G0...3Bank 65Green Channel
VGA_BLUEVGA_B0...3Bank 66Blue Channel
VGA_RGB_HSYNCVGA_HSBank 26Horizontal Sync
VGA_RGB_VSYNCVGA_VSBank 26Vertical Sync


Headphone Connector

TE0802 is equipped with a headphone connector (J12).

Power Supply

Power supply with minimum current capability of xx A for system startup is recommended.

...

Scroll Title
anchorTable_PWRSIP_PCHP
titlePower ConsumptionHeadphone Connector Information

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Power Input PinTypical Current
VINTBD*

* TBD - To Be Determined

...

SchematicConnected toNotes
JACKSNSPin F3, FPGA Bank 65
PWM_RPin F4, FPGA Bank 65
PWM_LPin E3, FPGA Bank 65


Grove Connector

TE0802 is equipped with a grove connector (J10).

Scroll Title
anchorFigureTable_PWRSIP_PDGrove
titlePower DistributionGrove Connector Information

scroll-

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Power-On Sequence

...

anchorFigure_PWR_PS
titlePower Sequency
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SchematicConnected toNotes
Grove_SCL0MIO18, FPGA Bank 500
Grove_SDA0MIO19, FPGA Bank 500


Pmod Sockets

TE0802 has 2 Pmod 2x6 host sockets which are connected to the FPGA.

...

Scroll Title
anchorFigureTable_PWRSIP_VMCPMOD
titleVoltage Monitor CircuitPmod SMD Host Socket Information

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Power Rails

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titleModule power rails.

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Power Rail Name

B2B Connector

JM1 Pin

B2B Connector

JM2 Pin

B2B Connector

JM3 Pin

DirectionNotes

...

DesignatorSignalsConnected to Notes
J5PMOD_A0...7Bank 26
J6PMOD_B0...7Bank 26


Test Points

Scroll Title
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titleZynq SoC bank voltages.Test Points Information

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Bank          

Test Point

Schematic Name
Signals
Voltage
Notes
Notes

...

hiddentrue
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...

use "include page" macro and link to the general B2B connector page of the module series,

...

? x ? modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.

3 x REF-??????? (compatible to ????????), (?? pins, ?? per row)

TP1+1.1V_LPDDR4
TP2+1.8V_MGTRAVTT
TP3+1.8V_PL
TP4FT_B_TX
TP5DP_TX_PWR
TP6GND
TP7GND
TP8PMIC2_SDA
TP9PMIC2_TP
TP10ONKEY2
TP11PMIC2_SCL
TP12DP_TX_HPD
TP13DP_TX_PWR
TP14INT_SCL1
TP15INT_SDA1
TP16FT_B_RX
TP17CLOCKDIST_OE
TP18+0.85V_VCCINT
TP19+3.3V
TP20+1.8V_PS
TP21ERR_STATUS
TP22+1.2V_PSPLL
TP23GND
TP24GND
TP25PMIC1_SCA
TP26PMIC1_SDA
TP27ONKEY1
TP28PMIC1_TP
TP29POR_B
TP30PSBATT
TP31SRST_B
TP32DONE
TP33INIT_B
TP34VBUS
TP35USB_VBUS
TP36PROG_B
TP37ERR_OUT


On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection


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titleOn-board Peripherals

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Chip/InterfaceDesignatorNotes
81199613U16
81199613U13
81199613U2, U18
81199613U22
81199613U6
81199613U17
81199613U8
OscillatorsU7, U15, U19, U23, U43
81199613D9
81199613LED0...7
81199613BTN1...5
81199613S1, S7/S.8


Quad SPI Flash Memory

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

he TE0802 evaluation board has  one single QSPI flash connected as x4. Flash size depends on the assembly option, default 32MB

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titleQuad SPI Interface MIOs and Pins

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MIO PinSchematicU16 PinNotes
MIO0MIO0B2SPI_CLK
MIO1MIO1D2SPI_DQ1
MIO2MIO2C4SPI_DQ2
MIO3MIO3D4SPI_DQ3
MIO4MIO4D3SPI_DQ0
MIO5MIO5C2SPI_CS


LPDDR4 SDRAM

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Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE0802 evaluation board has 1 GByte volatile LPDDR4 SDRAM IC (U13) for storing user application code and data. The details depends on the assembly option.

  • Part number: IS43LQ32256A-062BLI
  • Supply voltage: 1.06 -1.17 V
  • Speed: 1600 MHz 
  • Temperature: -40 to +85 C

EEPROM


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titleI2C FPGA EEPROM Interface MIOs and Pins

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MIO PinSchematicU2 PinNotes
MIO8Int_SCL1SCL
MIO9Int_SDA1SDA



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titleI2C Address for FPGA EEPROM

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TypeI2C AddressDesignatorNotes
4AA025E48T-I/OT0x50U2EEPROM with MAC



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titleI2C FTDI EEPROM Interface Pins

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PinSchematicU18 PinNotes
CSEECS1FTDI
CLKEECLK2FTDI
DIN/DOEEDATA3/4FTDI


USB ULPI PHY

The TE802 is equipped with a USB ULPI PHY. 

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titleUSB ULPI PHY Connections and Pins

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USB PHY PinSignal Schematic NamesConnected toNote

DATA0

USB0_DATA0

MIO56, FPGA Bank 502
DATA1USB0_DATA1MIO57, FPGA Bank 502
DATA2USB0_DATA2MIO54, FPGA Bank 502
DATA3USB0_DATA3MIO59, FPGA Bank 502
DATA4USB0_DATA4MIO60, FPGA Bank 502
DATA5USB0_DATA5MIO61, FPGA Bank 502
DATA6USB0_DATA6MIO62, FPGA Bank 502
DATA7USB0_DATA7MIO63, FPGA Bank 502
DIRUSB0_DIRMIO53, FPGA Bank 502
NXTUSB0_NXPMIO55, FPGA Bank 502
STPUSB0_STPMIO58, FPGA Bank 502
RESETBUSB0_RST_NMIO38, FPGA Bank 501
CPENUSB0_VBUS_ENPin 1, U21 (Current-limited Power Switch)
VBUSVBUS

Pin 8, U21 (Current-limited Power Switch).

Pin 1, J11 (USB Connector)


IDUSB0_IDPulled-down to GND
DPUSB0_D_PPin 3, J11 (USB Connector)
DMUSB0_D_NPin 2, J11 (USB Connector)
REFCLKUSB0_RCLKPin 3, U23 (Oscillator)
CLKOUTUSB0_CLKMIO52, FPGA Bank 502


Ethernet PHY

The TE0802 is equipped with an Ethernet PHY (U6) which is connected to RJ45 (J4) connector. 

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Ethernet PHY PinSignal Schematic NamesETHNote
TXD0ETH_TXD0MIO65, FPGA Bank 502
TXD1ETH_TXD1MIO66, FPGA Bank 502
TXD2ETH_TXD2MIO67, FPGA Bank 502
TXD3ETH_TXD3MIO68, FPGA Bank 502
TX_CTRLETH_TXCTLMIO69, FPGA Bank 502
TX_CLKETH_CLKMIO64, FPGA Bank 502
MDIOETH_MDIOMIO77, FPGA Bank 502Pulled-up to +1.8V_PS.
MDCETH_MDCMIO76, FPGA Bank 502
MDIP[0]

PHY_MDI0_P

Pin2, J4 (RJ45)
MDIN[0]PHY_MDI0_NPin3, J4 (RJ45)
MDIP[1]

PHY_MDI1_P

Pin4, J4 (RJ45)
MDIN[1]PHY_MDI1_NPin5, J4 (RJ45)
MDIP[2]

PHY_MDI2_P

Pin6, J4 (RJ45)
MDIN[2]PHY_MDI2_NPin7, J4 (RJ45)
MDIP[3]

PHY_MDI3_P

Pin8, J4 (RJ45)
MDIN[3]PHY_MDI3_NPin9, J4 (RJ45)
LED[0]PHY_LED0LED, J4 (RJ45)
LED[1]PHY_LED1LED, J4 (RJ45)
CONFIG--Pulled-up to +1.8V_PS.
XTAL_INETH_XTAL_INPin 3, U7 (Oscillator)
RESETnETH_RSTMIO37, FPGA Bank 501Pulled-up to +1.8V_PS.
RX_CLKETH_RXCKMIO70, FPGA Bank 502
RX_CTRLETH_RXCTLMIO75, FPGA Bank 502
RXD[0]ETH_RXD0MIO71, FPGA Bank 502
RXD[1]ETH_RXD1MIO72, FPGA Bank 502
RXD[2]ETH_RXD2MIO73, FPGA Bank 502
RXD[3]ETH_RXD3MIO74, FPGA Bank 502


FTDI FT2232H

The FTDI chip U17 converts signals from USB 2.0 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet for more information about the capacity of the FT2232H chip.
Channel A of FTDI FT2232H chip is used in MPPSE mode for JTAG. Channel B is used in UART mode.

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U18.

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titleFTDI Chip Interfaces and Pins

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FTDI Chip PinSignal Schematic NameConnected toNotes
ADBUS0TCKPin H13, FPGA Bank 503JTAG Interface
ADBUS1TDIPin H12, FPGA Bank 503JTAG Interface
ADBUS2TDOPin J13, FPGA Bank 503JTAG Interface
ADBUS3TMS

Pin J12, FPGA Bank 503

JTAG Interface

BDBUS0FT_B_TXMIO10, FPGA Bank 500UART
BDBUS1FT_B_RXMIO11, FPGA Bank 500UART
EECSEECSPin 1, U18 (EEPROM)
EECLKEECLKPin 2, U18 (EEPROM)
EEDATAEEDATAPin 3/4, U18 (EEPROM)
OSCI-Pin 3, U19 (Oscillator)
DMD_NPin 2, J8 (Micro USB 2.0)
DPD_PPin 3, J8 (Micro USB 2.0)


Clock Generator

The TE0802 is equipped with a clock generator (U8). 

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titleClock Generator Connections and Pins

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Clock Generator PinSignal Schematic NamesConnected toNote
REFP-Pin 3, U43 (Oscillator)
REFSELREFSEL-Pulled-up to +3.3V.
RESETN/SYNCCLK_GEN_RESETPin B5, FPGA Bank 26Pulled-up to +3.3V.
EEPROMSELEEPROMSEL-Pulled-up to +3.3V.
SDA/GPIO2CLK_GEN_SDA

- (Default)

MIO9, FPGA Bank 500 (R185/196 required)

Pin 2, J14 (Pin Header required)

Pulled-up to +3.3V. (Default)

Pulled-up to +3.3V.

Pulled-up to +3.3V.

SCL/GPIO3CLK_GEN_SCL

- (Default)

MIO8, FPGA Bank 500 (R185/196 required)

Pin 3, J14 (Pin Header required)

Pulled-up to +3.3V. (Default)

Pulled-up to +3.3V.

Pulled-up to +3.3V.

OE/GPIO4--Pulled-up to +3.3V.

Y1P

CLK_Y1_P / CLK_DP_PPin G19, FPGA Bank 50527 MHz
Y1NCLK_Y1_N / CLK_DP_NPin G20, FPGA Bank 50527 MHz

Y2P

CLK_Y2_P / CLK_USB_PPin J19, FPGA Bank 50526 MHz
Y2NCLK_Y2_N / CLK_USB_NPin J20, FPGA Bank 50526 MHz

Y3P

CLK_Y3_P / CLK_PCIe_PPin L19, FPGA Bank 505100 MHz
Y3NCLK_Y3_N / CLK_PCIe_NPin L20, FPGA Bank 505100 MHz

Y4P

CLK_Y4_P / SSD_RCLK_PPin 55, U5 (M.2)100 MHz
Y4NCLK_Y4_N / SSD_RCLK_NPin 53, U5 (M.2)100 MHz


Clock Sources

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titleOscillators

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DesignatorSignal Schematic NamesConnected toDescriptionFrequencyNote
U7ETH_XTAL_INPin 34, U6 (Ethernet PHY)Clock for Ethernet25 MHz
U15PS_CLKPin H14, FPGA Bank 503Clock for FPGA33 MHz
U23USB_CLK / USB0_RCLKPin 26, U22 (USB PHY)Clock for USB52 MHz
U43-Pin 5, U8 (Clock Generator)Clock for Clock Generator25 MHz


7-Segment Display

The TE0802 has a 4-Digit-7-Segment LED display.

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title7-Segment LED Pins

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PinSchematicConnected to Notes
A/L1CA / SEG_CAPin E4, FPGA Bank 65
B/L2CB / SEG_CBPin D3, FPGA Bank 65
C/L3CC / SEG_CCPin N5, FPGA Bank 65
DCD / SEG_CDPin P5, FPGA Bank 65
ECE / SEG_CEPin N4, FPGA Bank 65
FCF / SEG_CFPin C3, FPGA Bank 65
GCG / SEG_CGPin R5, FPGA Bank 65
DPCDP / SEG_CDPPin N3, FPGA Bank 65
A1SEG_AN1Pin A9, FPGA Bank 26
A2SEG_AN2Pin B9, FPGA Bank 26
A3SEG_AN3Pin A7, FPGA Bank 26
A4SEG_AN4Pin B6, FPGA Bank 26
L1-L3SEG_ANPin A8, FPGA Bank 26


User LED

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titleOn-board LEDs

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SchematicColorConnected toActive LevelNote
LED0...7RedBank 65High
D12GreenU9, PMICHighPOWER_OK


Push Button

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titleOn-board Push Buttons

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Designator SchematicConnected toFunctionalityNote
BTN_1USER_BTN_UPPin U2, FPGA Bank 65User Push ButtonPulled-up to +1.8V_PL.
BTN_2USER_BTN_LEFTPin R1, FPGA Bank 65User Push ButtonPulled-up to +1.8V_PL.
BTN_3USER_BTN_OKPin T1, FPGA Bank 65User Push ButtonPulled-up to +1.8V_PL.
BTN_4USER_BTN_RIGHTPin U1, FPGA Bank 65User Push ButtonPulled-up to +1.8V_PL.
BTN_5USER_BTN_DOWNPin T2, FPGA Bank 65User Push ButtonPulled-up to +1.8V_PL.
BTN_6POR_B

Pin 38, U1 (PMIC),

Pin 38, U9 (PMIC),

Pin K12, FPGA Bank 503

Reset ButtonPulled-up to +3.3V.


DIP Switch

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titleDIP Switches

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DesignatorSchematicConnected toFunctionalityNote
S1-1(A)MODE0Pin J16, FPGA Bank 503DIPPulled-down to GND.
S1-2(B)MODE1Pin H15, FPGA Bank 503DIPPulled-down to GND.
S1-3(C)USER_CFG0Pin A4, FPGA Bank 66DIPPulled-down to GND.
S1-4(D)USER_CFG1Pin B4, FPGA Bank 66DIPPulled-down to GND.
S7-1(A)USER_SW7Pin M5, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S7-2(B)USER_SW6Pin M4, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S7-3(C)USER_SW5Pin J2, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S7-4(D)USER_SW4Pin K1, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S8-1(A)USER_SW3Pin L1, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S8-2(B)USER_SW2Pin M1, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S8-3(C)USER_SW1Pin P2, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S8-4(D)USER_SW0Pin P3, FPGA Bank 65DIPPulled-up to +1.8V_PL.


Power and Power-On Sequence

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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

Power supply with minimum current capability of 3 A for system startup is recommended.

Power Consumption

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titlePower Consumption

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Power Input PinTypical Current
VINTBD*


* TBD - To Be Determined

Power Distribution Dependencies

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titlePower Distribution


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Power-On Sequence

PMICs will be reset after pressing Push Button BTN6 (POR_B).

Power Rails

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Power Rail NameDirectionNotes
VININSupply Voltage
+5VOutJ1...2
+3.3VOutJ14, J10


Bank Voltages

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Bank          

Schematic Name

Voltage

Notes
Bank 26+3.3V3.3 V
Bank 65+1.8V_PL1.8 V
Bank 66+1.8V_PL1.8 V
Bank 500+3.3V3.3 V
Bank 501+3.3V3.3 V
Bank 502+1.8V_PS1.8 V


Bank 503+3.3V3.3 V
Bank 504+1.1V_LPDDR41.1 V


Bank 505

+0.85V_MGTRAVCC

0.85 V

...



Technical Specifications

Absolute Maximum Ratings

V
Scroll Title
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titlePS absolute maximum ratingsAbsolute Maximum Ratings

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SymbolsDescriptionMinMaxUnit
VINInput Supply Voltage (J13)-3.57
V
V
V
T_STGStorage Temperature-4085°C
VVVV