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Refer to httpshttp://wiki.trenz-electronic.de/display/PD/<name>org/te0724-info for the current online version of this manual and other available documentation.

The Trenz Electronic TE0724 is an industrial-grade SoC module based on Xilinx Zynq -70107010/7020, which provides a dual core ARM Cortex A9 and a 7-series FPGA logic. It provides a gigabit ethernet transceiver, 1GByte 1 GByte of DDR3L SDRAM, 32 64 MByte Flash memory as configration and data storage. it It includes strong pwerregulators power regulators for all needed voltages and a robust high-speed connector for in- and outputs. It has a 6 x 4 cm form factor.

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• Xilinx Zynq XC7Z010-1CLG400I or XC7Z020-1CLG400I
• Dual-core ARM Cortex-A9 MPCore
• Max. 667 MHz
• Shock proof an and vibration resistant
• Size 6 x 4 cm
• Plug-On-Modul with 1 × 160 Pin High-Speed connector
• 1 GByte DDR3L SDRAM
• 32 64 MByte QSPI Flash Speicher
• 1 x GBit Ethernet PHY
• 1 x MAC-Address EEPROM
• 128 KBit EEPROM
• 1 x CAN Transceiver
• On-Board DC/DC-regulators
• Excellent signal integrity due to well dirstributed evenly-spread supply pins

Additional assembly options are available for cost or performance optimization upon request.

Main Components

Put top and bottom pics with labels of the real PCB here...

Table 1: TE0xxx-xx main components.

Add description list of PCB labels here...

Initial Delivery State

...

Storage device name

...

Content

...

Notes

...

..

...

..

...

Table 1: Initial delivery state of programmable devices on the module.

Boot Process

By default the ... supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B connector JM..

...

MODE Signal State

...

High or open

...

SD Card

...

Low or ground

...

QSPI Interface

Table 2: Selecting power-on boot device.

Signals, Interfaces and Pins

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Connections and Interfaces or B2B Pin's which are accessible by User
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Board to Board (B2B) I/Os

I/O signals connected to the SoCs I/O bank and B2B connector: 

...

Table x: General overview of PL I/O signals connected to the B2B connectors.

All PS MIO banks are powered by on-module DC-DC power rail. All PL I/O banks have separate VCCO input pins in the B2B connectors, valid VCCO should be supplied from the carrier board.

For detailed information about the pin out, please refer to the Pin-out Tables. 

The configuration of the PS I/Os MIOx, MIOx ... MIOx, ... depend on the carrier board peripherals connected to these pins.

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TO-DO (future):
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MGT Lanes

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MGT lanes should be listed separately, as they are more specific than just general I/Os.  
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MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

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• MGT_RX0_P
• MGT_RX0_N
• MGT_TX0_P
• MGT_TX0_N

...

• JM3-8
• JM3-10
• JM3-7
• JM3-9

...

• MGTHRXP0_225, Y2
• MGTHRXN0_225, Y1
• MGTHTXP0_225, AA4
• MGTHTXN0_225, AA3

...

• MGT_RX1_P
• MGT_RX1_N
• MGT_TX1_P
• MGT_TX1_N

...

• JM3-14
• JM3-16
• JM3-13
• JM3-15

...

• MGTHRXP1_225, V2
• MGTHRXN1_225, V1
• MGTHTXP1_225, W4
• MGTHTXN1_225, W3

...

• MGT_RX4_P
• MGT_RX4_N
• MGT_TX4_P
• MGT_TX4_N

...

• JM1-12
• JM1-10
• JM1-6
• JM1-4

...

• MGTHRXP0_224, AH2
• MGTHRXN0_224, AH1
• MGTHTXP0_224, AG4
• MGTHTXN0_224, AG3

...

• MGT_RX5_P
• MGT_RX5_N
• MGT_TX5_P
• MGT_TX5_N

...

• JM1-24
• JM1-22
• JM1-18
• JM1-16

...

• MGTHRXP1_224, AF2
• MGTHRXN1_224, AF1
• MGTHTXP1_224, AF6
• MGTHTXN1_224, AF5

...

Table x: MGT lanes.

Below are listed MGT banks reference clock sources.

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Block Diagramm

Main Components

Scroll Title
title Figure 2: TE0724 main components
Scroll Ignore draw.io Diagram border false viewerToolbar true fitWindow false diagramName TE0724-02_Top simpleViewer true width links auto tbstyle top lbox true diagramWidth 641 revision 3 draw.io Diagram border false viewerToolbar true fitWindow false diagramName TE0724-02_Bottom simpleViewer true width links auto tbstyle top lbox true diagramWidth 641 Scroll Only Image Added Image Added

1. XILINX ZYNQ XC7Z020-2CLG400C, U1
2. Gigabit Ethernet Transceiver Alaska 88E1512, U7
3. Power Manager Dialog DA9062, U4
4. 1GByte - 2x 4Gbit DDR3L RAM, U3, U5
5. 64MByte ISSI SPI Flash IS25LP512M, U13
6. 128KByte Serial EEPROM Microchip 24AA, U10
7.  CAN Transceiver MCP2542FDT, U2
8.  160 Pin Samtec B2B Connector ST5-80-1.50-L-D-P-TR, J1

Initial Delivery State

Table 1: Initial delivery state of programmable devices on the module.

Boot Process

Boot mode is selected via two Mode pins at B2B connector J2. By default the TE0724 supports JTAG and SPI Boot Mode. Connecting a SD Card via B2B connector to MIO Pins (See SD Card Interface) gives the possibility to boot from SD Card. The Mode pins are pulled up at the module.

Table 2: Boot mode selection.

Signals, Interfaces and Pins

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Connections and Interfaces or B2B Pin's which are accessible by User
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Board to Board (B2B) I/Os

I/O signals connected to the SoCs I/O bank and B2B connector: 

Table 3: General overview of PL I/O signals connected to the B2B connectors.

All PS MIO banks as well as PL bank 34 are powered by on-module DC-DC power rails. Valid VCCO_35 for PL bank 35 should be supplied via the B2B connector.

For detailed information about the pin out, please refer to the Pin-out Tables. 

The configuration of the PS I/Os MIO40 to MIO51 depend on the carrier board peripherals connected to these pins.

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TO-DO (future):
If Vivado board part files are available for this module, the standard configuration of the MIO pins by using this board part files should be mentioned here. This standard configuration of those pins are also apparent of the on-board peripherals of base-boards related to the module.
  -->

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MGT lanes should be listed separately, as they are more specific than just general I/Os.  
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JTAG Interface

Table x: MGT reference clock sources.

JTAG Interface

JTAG access to the ... is provided through B2B connector .... JTAG access to the ZYNQ SoC is provided through B2B connector J1 and testpoints.

Table 54: JTAG interface signals.

System Controller

...

Pins

Special purpose pins are connected to smaller available for System Controller CPLD and have functions and are routed to the Power Management IC (U4) with the following default configuration:

Table 5Table x: System Controller CPLD I/O pins.

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For the detailed function of the pins and signals, the internal signal assignment and implemented logic, look to the Wiki reference page SC CPLD of this module or into the bitstream file of the SC CPLD.
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Quad SPI Interface

Following line is just an example, change it to your needs.

Quad SPI Flash (U14) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6.

Note that table column says "Signal Name", it should match the name used on the schematic.

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Table x: Quad SPI interface signals and connections.

SD Card Interface

Describe SD Card interface  shortly here if the module has one...

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Table x: SD Card interface signals and connections.

Ethernet Interface

On board Gigabit Ethernet PHY is provided with ...

Ethernet PHY connection

...

Table x: ...

USB Interface

USB PHY is provided with ...

...

Table x: ...

The schematic for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.

I2C Interface

On-board I²C devices are connected to MIO.. and MIO.. which are configured as I²C... by default. I²C addresses for on-board devices are listed in the table below:

...

Table x: I²C slave device addresses.

On-board Peripherals

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Components on the Module, like Flash, PLL, PHY...
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System Controller CPLD

The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I²C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

For detailed information, refer to the reference page of the SC CPLD firmware of this module.

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DDR Memory

By default TE0xxx module has ... DDRx SDRAM chips arranged into 32-bit wide memory bus providing total of 1 GBytes of on-board RAM. Different memory sizes are available optionally.

Quad SPI Flash Memory

On-board QSPI flash memory (U14) on the TE0745-02 is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin J2-150 of B2B connector J2.

High-speed USB ULPI PHY

...

.
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Quad SPI Interface

Quad SPI Flash (U13) is connected to the Zynq PS QSPI_0 interface via PS MIO bank 500, pins MIO1 ... MIO6.

Table 6: Quad SPI interface signals and connections.

SD Card Interface

There is no physical SD Card slot on the module. Three different interface options are possible at a carrier via the PS MIO 10 to 15 or 40 to 45 or 46 to 51 plus additional MIOs for SD Card Detect and Write Protect as well as SD Card Power Controls. For details compare Xilinx UG585-Zynq-7000-TRM Table 2-4.

Ethernet Interface PHY

The TE0724 is equipped with a Marvell Alaska 88E1512 Gigabit Ethernet PHY (U7) connected to PS Ethernet GEM0. The I/O Voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the PL IO_L11P_T1_SRCC_34.

Table 7: Ethernet PHY connections.

CAN PHY

A felxible data rate CAN Transceiver is provided by a Microchip MCP2542FDT.

Table 8: CAN PHY connections.

I2C Interface

On-board I²C devices are connected to PS MIO28 (SCL) and MIO29 (SDA). I²C addresses for on-board devices are listed in the table below:

Table 9: I²C slave device addresses.

On-board Peripherals

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Power Management IC

The power management IC (U4) is provided by dialog Semiconductors (DA9062). It controls the power-on sequencing of the various power rails. It is preprogrammed and accessible via I²C address 0x58 /  0x59. For a detailed description of the configurable power management IC please refer to the datasheet of  dialog semicondutor DA9062.

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DDR Memory

By default TE0724 module has 2 DDR3L SDRAM chips arranged into 32-bit wide memory bus providing total of 1 GBytes of on-board RAM. Different memory sizes are available optionally.

Quad SPI Flash Memory

On-board QSPI flash memory (U13) on the TE0724-04 is a ISSI IS25LP512M with 512 Mbit (64 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

MAC Address EEPROM

A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I²C bus with slave device address 0x53.

RTC - Real Time Clock

An temperature compensated Intersil ISL...

Programmable Clock Generator

There is a Silicon Labs I²C programmable quad PLL clock generator on-board (Si5338A, U2) to generate various reference clocks for the module.

...

IN1

...

-

...

Not used.

...

IN3

...

Reference input clock.

...

IN4

...

IN5

...

-

...

CLK0A

...

CLK1_P

...

FPGA bank 45.

...

CLK0_P

...

FPGA bank 45.

...

available for application use. It is accessible over I²C bus with slave device address 0x53.

USER EEPROM

A Microchip 24AA128T serial EEPROM (U10) is available for e.g. module identification and user Data. The device has 128Kbit memory with max 64 bytes page write capability. It is accessible over I²C bus with slave device address 0x50.

Oscillators

The module has following reference clock signals provided by on-board oscillators and external source from carrier board:

Table10 : Reference clock signals.

On-board LEDs

Table 11: On-board LEDs.

Pin Header

Optional assembled Pin Header J2 can be used for PMIC In-System Programming.

Table 12: Optional assembled Pin Header

 Table : Programmable quad PLL clock generator inputs and outputs.

Oscillators

The module has following reference clock signals provided by on-board oscillators and external source from carrier board:

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Table : Reference clock signals.

On-board LEDs

...

Table : On-board LEDs.

Power and Power-On Sequence

...

Table 13: Typical power consumption.

 * TBD - To Be Determined soon with reference design setup.

Power supply with minimum current capability of ...A for system startup is recommended.For the lowest power consumption and highest efficiency of the on-board DC-DC regulators it is recommended to power the module from one single 3.3V supply. All input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneouslyminimum current capability of ...A for system startup is recommended.

The on-board voltages of the TE07xx SoC module will be powered-up in order of a determined sequence after the external voltages '...', '...' and '...' are available. All those power-rails can be powered up, with 3.3V power sources, also shared. <-- What?TE0724 SoC module will be powered-up in order of a determined sequence after the external voltages VIN  is available and nONKEY is asserted.

Power Distribution Dependencies

Regulator dependencies and max. current.

Put power distribution diagram here...

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Power Distribution Dependencies

DCDC U8 component is either TPS82140 (2 A) or MUN12A (3 A) depending on the variant.

See Xilinx data sheet ... for additional information. User should also check related base board documentation when intending base board design for TE07xx TE0724 module.

Power-On Sequence

The TE07xx TE0724 SoM meets the recommended criteria to power up the Xilinx Zynq MPSoC properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages. For a detailed description of the configurable Power Management IC please refer to the datasheet of dialog semicondutor DA9062.

Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending ascending order as listed in the blocks of the diagram:

Put power-on diagram here...

...

...

Voltage Monitor Circuit

If the module has one, describe it here...

Power Rails

...

Power Rails

Table : Module power rails.

Different modules (not just 4 x 5 cm ones) have different type of connectors with different specifications. Following note is for Samtec Razor Beam™ LSHM connectors only, but we should consider adding such note into included file in Board to Board Connectors section instead of here.

Bank Voltages

Table 14: Module power rails.

Current rating of theSamtec connector is 1.6A per pin (1 pin powered per row).

Bank Voltages

Table 15: Module PL I/O bank voltages.

Board to Board Connectors

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Page properties
hidden true id Comments
This section is optional and only for modules. use "include page" macro and link to the general B2B connector page of the module series, for example: 4 x 5 SoM LSHM B2B Connectors

Include Page
4 x 6 SoM SS5/ST5 B2B Connectors 4 x 6 SoM SS5/ST5
Include Page
4 x 5 SoMs - LSHM B2B Connectors 4 x 5 SoMs - LSHM B2B Connectors

Variants Currently In Production

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Technical Specifications

Absolute Maximum Ratings

Table 18: Module absolute maximum ratings.

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Recommended Operating Conditions

Table 19: Module recommended operating conditions.

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Physical Dimensions

• Module size: ... 60 mm × ... 40 mm.  Please download the assembly diagram for exact numbers.

• Mating height with standard connectors: 5... 0 mm.

• PCB thickness: 1... 6 mm.

• Highest part on PCB: approx. 1... 6 mm. Please download the step model for exact numbers.

All dimensions are given in millimeters.Put mechanical drawings here...

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5: TE0724 Mechanical Dimensions.

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Revision History

Hardware Revision HistoryHistory

Table 20: Module hardware revision history.

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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Put picture of actual PCB showing model and hardware revision number here...

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Document Change History

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v.58

Table 21Table : Document change history.

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