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Table of Contents

Table of Contents

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Note:
 'Key Features' description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

  • 2x Non-isolated power connectors
  • 2x  RJ45 Transceivers
  • 3x Board to Board (B2B) Connectors
  • 2x XMOD JTAG/UART Adaptor
  • 4x SMA Coaxial Connectors
  • DIP Switch
  • 3 x Samtec ASP-122953-01 160-pin stackable, compatible with TE078x
  • 2 mm MC LB2-A Soldered Connector for power supply (12V input)
  • 4 SMA connectors for MGT
  • 2 x 12 pin headers for XMOD
  • 1 x DIP switch for modules CPLD Access
  • 2 x RJ45 Connector
  • USB A Stacked Connector 
  • Equipped with two TE0790 XMOD FTDI JTAG adapters
  • Voltage regulators
  • Dimension: 115 x 115 mm

Block Diagram

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Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


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Scroll Title
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titleTExxxx TEBT0782 block diagram


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Main Components

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titleTExxxx TEBT0782 main components


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  1. RJ45 Transceivers, J1-J2
  2. USB A Stacked, U7
  3. XMOD JTAG/UART BaseAdapter, J7
  4. JTAG CPLD Adapter -J8
  5. 2 Line Common Mode Choke, J10
  6. Non-isolated power jack (VIN), J9-J11
  7. DIP Switch, S1
  8. SMA Coxial Connectors (MGT_TX), J3-J4
  9. SMA Coxial Connectors (MGT_RX), J5-, J3...J6
  10. Board to Board ConnectorsConnector, JB1...JB3
  11. Board to Board Connector, JB3
  12. Board to Board Connector, JB2

Initial Delivery State

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Notes :

Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

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titleInitial delivery state of programmable devices on the module

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Storage device name

Content

Notes

-

-

-


Configuration Signals

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  • Overview of Boot Mode, Reset, Enables.

The general Reset is provided through button S1 on TE0790 XMOD J7.

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titleBoot Reset process.

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MODE

Signal

State

Boot Mode
Scroll Title
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titleReset process.
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Signal

B2BI/ONote

Signals, Interfaces and Pins

B2BNote

RESIN

JBC3-130Board Reset


Signals, Interfaces and Pins

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Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator Designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

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titleGeneral PL I/O to B2B connectors information

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FPGA Bank
B2B ConnectorInterfaceNumber of I/O
Signal Count
Voltage Level
Notes
Notes

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JTAG access to the TExxxx SoM through B2B connector JMX.

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anchorTable_SIP_JTG
titleJTAG pins connection

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JTAG Signal

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B2B Connector

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MIO Pins

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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

JB1








RJ45, J1B-J1C1 Differential pair, 2 Single EndedYellow, Green LEDs
RJ45, J1A4 Differential pair, 8 Single EndedPHY1 MDIO
RJ45, J2B-J2C1 Differential pair, 2 Single EndedYellow, Green LEDs
RJ45, J2A4 Differential pair, 8 Single EndedPHY2 MDIO
TE0790 Base, J84 Single Ended
TE0790 Base, J71 Single Ended
USB A Stacked, U72 Single EndedUSB
Power Switch, U12 Single Ended
SMD Line Filter, L61 Differential pair, 2 Single EndedUSB1_D
SMD Line Filter, L71 Differential pair, 2 Single EndedUSB2_D
ESD protection diode, U51 Single EndedUSB1_VBUS
ESD protection diode, U81 Single EndedUSB2_VBUS
JB2

Module TE078x FPGA, Bank 111-11216 Differential pair, 32 Single EndedMGT_RX8...15, MGT_TX8...15
Module TE078x FPGA, Bank 341 Differential pair, 2 Single Ended

J1_B34_VRP, J1_B34_VRN

Module TE078x FPGA, Bank 341 Differential pair, 2 Single EndedJ1_B33_VRP, J1_B33_VRN
JB3



TE0790 Base, J84 Single EndedM_TCK, M_TMS, M_TDO, M_TDI
TE0790 Base, J7

4 Single Ended

2 Single Ended

1 Single Ended

TCK, TMS, TDO, TDI

UART RX/TX

RESIN

DIP Switch, S1-A1 Single EndedJTAGENB
SMA Coaxial, J3...62 Differential pair, 4 Single EndedMGT_RX0, MGT_TX0
Module TE0782...4 FPGA, Bank 109-11016 Differential pair, 32 Single EndedMGT_RX1...7, MGT_TX0...7


XMOD Pin Header

JTAG/UART to Module SoC/FPGA

JTAG access to the TE078x SoM is available through B2B connector JB3.  JTAG access is provided by TE0790 XMOD Adapter on Pin Header J7.

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titleJTAG pins connection

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JTAG Interface Pins

Signal Name

B2B Connector

Notes
AXMOD_AJB3C-129UART
BXMOD_BJB3C-135UART
CTCKJB3C-141JTAG
DTDOJB3C-148JTAG
ECPLD_GPIO4JB1A-18
FTDIJB3C-147JTAG
GRESINJB3C-130General Reset
HTMSJB3C-142JTAG
3.3V3.3V_MJB1- JB3
VIO3.3V_MJB1- JB33.3V


JTAG/ GPIO to Module CPLD

JTAG access to the System Controller CPLD is provided through B2B connector J3. JTAG access to CPLD is provided by TE0790 XMOD Adapter on Pin Header J8.

Pin 'JTAGENB' must be set high, using DIP Switch S1-A in order to program the System Controller CPLD via JTAG interaface.

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SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

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anchorTable_OBP_MIOs
titleMIOs pins

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs
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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

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anchorTable_OBP
titleOn board peripherals

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Quad SPI Flash Memory

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

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anchorTable_OBP_SPI
titleQuad SPI interface MIOs and pins

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U? Pin
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titleI2C interface MIOs and pinsCPLD JTAG pins connection

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JTAG Interface Pins

Signal Name

B2B Connector

MIO PinSchematic

Notes
Scroll Title
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titleI2C Address for RTC
Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueMIO PinI2C AddressDesignatorNotes

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ACPLD_GPIO0JB1A-10
BCPLD_GPIO1JB1A-12
CM_TCKJB3B-81
DM_TDOJB3B-88
ECPLD_GPIO2JB1A-14
FM_TDIJB3B-87
GCPLD_GPIO3JB1A-16
HM_TMSJB3B-82
3.3V3.3V_CPLDJB1- JB3
VIO3.3V_CPLDJB1- JB33.3V


DIP Switch S2 on TE0790 must be set and fixed like the following table.

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titleI2C EEPROM interface MIOs and pins
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MIO PinSchematicU?? PinNotes
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titleI2C address for EEPROMXMOD DIP Switch Setting

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MIO PinI2C AddressDesignatorNotes

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DIP Switch

SettingNotes
S2-1ONJTAGENB (Enable/Disable module JTAG CPLD IOs)
S2-2OFFNC
S2-3OFFNC
S2-4OFFNC


RJ45 Connectors

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titleOn-board LEDsRJ45s Connections to B2B Connectors

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SchematicColorConnected toActive LevelNote

DDR3 SDRAM

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Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.

  • Part number: 
  • Supply voltage:
  • Speed: 
  • NOR Flash
  • Temperature: 

Ethernet

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anchorTable_OBP_ETH
titleEthernet PHY to Zynq SoC connections
Signal NameRJ45-J1 PinRJ45-J2 PinNotes
B2B
PHY_MDI0_PJB1A-23JB1A-39
PHY_MDI0_NJB1A-21JB1A-37
PHY_MDI1_PJB1A-19JB1A-35
PHY_MDI1_NJB1A-17JB1A-33
PHY_MDI2_PJB1A-15JB1A-31
PHY_MDI2_NJB1A-13JB1A-29
PHY_MDI3_PJB1A-11JB1A-27
PHY_MDI3_NJB1A-9JB1A-25
J2_TX9_PJB1A-95-LED Green/Yellow
J2_TX9_NJB1A-97-LED Green/Yellow
J2_RX9_N-JB1A-96LED Green/Yellow
J2_RX9_P-JB1A-98LED Green/Yellow


USB A Stacked Socket

The USB A Stacked (U7) is a dual port USB Socket which provides two USB ports.

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CAN Transceiver

Scroll Title
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titleCAN Tranciever interface MIOsDual Port USB Connections

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Signal Name
Bank
Port A
SchematicU?? PinNotesD-TxDriver InputR-RxReciever Output

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anchorTable_OBP_CLK
titleOsillators

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Power and Power-On Sequence

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hiddentrue
idComments

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit
Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

Port BNotes
B2BConnected to B2BConnected to 
USB_D_PJB1A-28SMD Line Filter, L7JB1A-40SMD Line Filter, L6
USB_D_NJB1A-26SMD Line Filter, L7JB1A-38SMD Line Filter, L6
USB_VBUSJB1A-24SMD Line Filter, L7JB1A-36SMD Line Filter, L6
VBUS_V_ENJB1A-30Power Switch, U1 JB1A-32Power Switch, U1 


SMA Coaxial 

The TEBT0782 carrier is equipped with 4x SMA Coaxial straight connectors.

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titleSMAs Connections

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Designator SchematicB2BNotes
J3MGT_TX0_NJB3A-29Transfer
J4MGT_TX0_PJB3A-31Transfer
J5MGT_RX0_NJB3A-30Receive
J6MGT_RX0_PJB3A-32Receive


Test Points

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titleTest Points Information

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Power Supply

Power supply with minimum current capability of xx A for system startup is recommended.

Power Consumption

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titlePower Consumption

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Power Input PinTypical Current
VINTBD*

* TBD - To Be Determined

Power Distribution Dependencies

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anchorFigure_PWR_PD
titlePower Distribution
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Test Point

Signals

B2B Connector

Notes
TP 1VBAT_IJB3-124
TP 2OTG2_IDJB1-22
TP 3OTG1_IDJB1-34
TP 4USB1_VBUSJB1-36
TP 5USB2_VBUSJB1-24
TP 6M_TCKJB3-81
TP 7M_TDOJB3-88
TP 8M_TDIJB3-87
TP 9M_TMSJB3-82
TP 10TCKJB3-141
TP 11TDOJB3-148
TP 12TDIJB3-147
TP 13TMSJB3-142
TP 14VINJB1-165...168
TP 155V-
TP 163.3V_CPLDJB1-147...148
TP 17-18GND-


On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

Power-On Sequence

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anchorFigure_PWR_PS
titlePower Sequency
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Voltage Monitor Circuit

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anchorFigure_PWR_VMC
titleVoltage Monitor Circuit
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Power Rails

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anchorTable_PWR_PR
titleModule power rails.

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B2B Connector

JM1 Pin

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B2B Connector

JM2 Pin

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B2B Connector

JM3 Pin

...


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titleZynq SoC bank voltages.On board peripherals

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Chip/InterfaceDesignatorNotes
DIP SwitchS1


DIP Switch

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titleDIP Switch Connections

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SwitchConnected to B2BNotes
S1-AJTABENBJB3C-136
S1-B...D--Not connected


Power and Power-On Sequence

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idComments

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

Power supply with minimum current capability of 3A for system startup is recommended.

Power Consumption

Scroll Title
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titlePower Consumption

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Power Input PinTypical Current
VINTBD*


* TBD - To Be Determined

Power Distribution Dependencies

12V power supply (VIN) on J9/J11 (2 mm MC LB2-A solder-in) or on J10 (TE1.5/2-3.5H).

Scroll Title
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titlePower Distribution


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Power-On Sequence

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titlePower Sequency


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Power Rails

Notes
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titleModule power rails.

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Power Rail Name

B2B JB1 Pin

B2B JB2 Pin

B2B JB3 Pin

DirectionNotes
VIN165, 166, 167, 168--Input/OutputDirectly to module
3.3V_M99, 100, 111,112, 123, 124, 135, 136, 159, 160, 169, 170, 171, 172-99, 100, 159, 160Input/Output160, 169, 170, 171, 172 are output other ones input for IO Banks
3.3V_CPLD147,148--OutputDirectly to module
1.8V_M-99,100, 159, 160, 169, 170, 171, 172124Input/Output169, 170, 171, 172 are output other ones input for IO Banks
VBAT_IN

Bank          

Schematic Name

Voltage