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nearly the same like TEBB0714: TEBB0714 TRM

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Template Revision 2.12

  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"
  • Carrier: TRM Name usually "TEB Series Name" +TRM
    Example: "TEB0728 TRM"

...

The Trenz Electronic TEBA0714 is a carrier for Trenz Electronic module TE0714 which is an industrial - grade ... module ... based on Xilinx ...module integrated with Xilinx Artix 7. 

Refer to http://trenz.org/teba0714-info for the current online version of this manual and other available documentation.

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Notes :

Key Features

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Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly optionsKey optionsKey Features'  must be split into 6 main groups:
  • FPGA/Module
    • Package:
    • Speed:
    • Temperature:
  • RAM/Storage
    • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension
  • Module:
    • Trenz TE0714 Modulsockel (2x Samtec 100 Pin LSHM-Serienstecker)
    • Speed:
    • Temperature:
  • On Board:
    • 2 x User LEDs (rot/grünRed, Green)
    • 1 x PROG_ DONE LED (rotRed)
  • Interface:
    • 2 x Pin - Header 50 polig 50 Pol. (FPGA Bank Ein- und Ausgänge und StromversorgungI/Os and Power)
    • 2x Samtec 100 Pin LSHM Series Connectors
    • 1 x XMOD JTAG/UART Adapter (TE0790)
    • 1 x Pin -Header für FPGA Bank Stromversorgung VCCIO34 (1.8 VOUT, 2.5V, 3.3 VOUTHeader 16 Pol. (JTAG, MGT-CLK, Boot Mode, XADC, I/O's)
    • 1 x Pin - Header für FPGA Bank Stromversorgungr V_CFG (1.8 VOUT, 2.5V, 3.3 VOUT)
    • 1 x XMOD (TE0790) Pin-Header
    • 1 x Pin-Header 16 polig (JTAG, MGT-CLK, Boot Mode, XADC, I/O's)
    • 1 x Pin-Header 10 polig (Ein-/ und Ausgänge)
    • 10 Pol. (FPGA Bank I/Os and Power)
    • 1 x SFP+ Connectors1 x SFP-Anschluss
  • Power:
    • 1 x LDO Spannungsregler Regulator
    • 3.3 V auf 2.5 V3V  Nominal Power supply
  • Dimension: 30 mm x 40  
    • 46 mm × 75 mm

Block Diagram

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add drawIO object here.

Note
For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .



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titleTEBA0714 block diagram


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Main Components

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Notes :
  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


Note
For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .



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titleTEBA0714 main components


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  1. SMT pin header

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  1. , J26
  2. SMT pin header, J27

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  1. Board to Board  (B2B) Connector, JM1
  2. Board to Board  (B2B) Connectorr

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  1. , JM2
  2. XMOD header, JX1

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  1. Voltage Regulator, U1
  2. User Red LED, D2
  3. User Green LED, D1 (Red)
  4. SFP+ Connector, J1
  5. User Red LED, D3
  6. 50 pin header (Not assembled),  J20
  7. 16 pin header (Not assembled),  J3,
  8. 10-pin header (Not assembled), J4 
  9. 50-pin header (Not assembled), J17

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Initial Delivery State

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Notes :Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.If there is no components which might have initial data ( possible on carrier) you must keep the table empty

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titleInitial delivery state of programmable devices on the module

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Storage device nameContentNotes
---------


Configuration Signals

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  • Overview of Boot Mode, Reset, Enables.

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titleBoot process.

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SignalMODE Signal StateBoot ModeNote
BOOTMODE0Slave SelectMAP
1Master SPI



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titleReset process.

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SignalB2B
I/O
Signal StateNote
PROG_BJM1-94Active LowClear FPGA configuration  and initiate a new configuration
Note


Signals, Interfaces and Pins

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Notes :
  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

Board to Board (B2B) I/Os

FPGA bank number and number Number of I/O signals and Interfaces connected to the B2B connector:

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titleGeneral PL I/O to B2B connectors information

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FPGA BankB2B ConnectorInterfaceNumber of I/O Signal CountVoltage LevelNotesNotes

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JTAG access to the TExxxx SoM through B2B connector JMX.

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titleJTAG pins connection

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JTAG Signal

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B2B Connector

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JM1



User I/O52 Single ended, 27 Differential-
MGT lanes4 Differential, 2 lanes
MGT reference clock input2 Single ended, 1 Differential
JTAG4 Single ended
SoM control signals2 Single endedPROG_B, DONE
JM2User I/O36 Single ended or 18 differential-
SFP+ Interface control signals8 Single ended
QSPI interface6 Single ended
UART interface2 Single ended
User LEDs2 Single endedRed, Green
SoM control signals1 Single endedBOOTMODE


On-board Pin Header

TEBA0714 is equipped with four pin headers J17, J20, J3 and J4 which are not assembled on the board, in case of need customer can solder the pins and have access to the signals in the following table.

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titleGeneral I/O to Pin headers information

MIO Pins

you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

B2B
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MIO PinConnected toB2BNotes
MIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

J2QSPI
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titleMIOs pins

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MIO
Pin Header
Connected to
InterfaceNumber of I/ONotes

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J17



User I/O36 Single ended, 18 DifferentialModule FPGA Bank 14
SPI interface6 Single ended-
Power4 Single ended3.3V, V_CFG
J20User I/O42 Single ended or 21 differentialModule FPGA Bank 34
Power4 Single ended3.3V, V_CFG
User LEDs2 Single endedRed, Green
SoM control signals1 Single ended'BOOTMODE'
J3JTAG 4 Single ended
UART2 Single endedB14_L25, B14_L0
ADC2 Single ended
Clock2 Single ended, 1 Differential
Power4 Single ended3.3V, V_CFG
Control Signals2 Single endedBOOTMODE, PROG_B
J4User I/O6 Single ended or 3 differential
Power2 Single ended3.3V, 3.3V_OUT


JTAG Interface Base

JTAG access to the mounted SoM is provided through B2B connector JM1 and JM2 and is also routed to the XMOD JTAG/UART header JX1.

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titleJTAG pins connection
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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs
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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

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titleOn board peripherals

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Quad SPI Flash Memory

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

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titleQuad SPI interface MIOs and pins
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MIO
XMOD Header PinSchematicB2B Connector
U??
Pin Header
Notes

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titleI2C interface MIOs and pins
Note
AB14_L25JM2-97J3-4UART Transfer
BB14_L0JM2-99J3-7UART Receive
EBOOTMODEJM2-100J3-9
GPROG_BJM1-94J3-11
CTCKJM1-90J3-4
DTDIJM1-86J3-10
FTDOJM1-88J3-8
HTMSJM1-92J3-12
3.3V3.3VJM1-97,99J3,J4,J17,J20Nominal Input Voltage
VIOV_CFG-J17-45Configuration Voltage


The DIP-switch S2 on XMOD Adapter TE0790 must be set as the following table.

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anchorTable_OBP_I2C_RTC
titleI2C Address for RTC

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titleI2C EEPROM interface MIOs and JTAG pins connection

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MIO Pin
S2SchematicU?? PinNotes
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titleI2C address for EEPROM
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MIO PinI2C AddressDesignatorNotes

LEDs

StatusDescriptionNotes      
1ONUpdate Mode JTAG access to SC CPLD only
2OFFMust be in OFF state always
3OFF3.3V  is inputsupplied from pin headers externally
4OFFVIO is inputsupplied from pin header externally


SFP+ Connector

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titleSFP+ Connector Information
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titleOn-board LEDs

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Schematic
Pin
Color
Connected to
Active Level
Notes
Note