Page History
HTML |
---|
<!--
Template Revision 1.0
Basic Notes
- export PDF to download, if vivado revision is changed!
- Template is for different design and SDSoC and examples, remove unused or wrong description!
--> |
Scroll Only (inline) |
---|
Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation |
Scroll pdf ignore | ||||
---|---|---|---|---|
Table of contents
|
Overview
HTML |
---|
<!--
General Design description
--> |
Key Features
HTML |
---|
<!--
Add Basic Key Features of the design (should be tested)
--> |
Excerpt |
---|
|
Revision History
HTML |
---|
<!--
- Add changes from design
- Export PDF to download, if vivado revision is changed!
--> |
...
Release Notes and Know Issues
HTML |
---|
<!--
- add known Design issues and general Notes for the current revision
--> |
...
Requirements
Software
HTML |
---|
<!--
Add needed external Software
--> |
...
Hardware
HTML |
---|
<!--
Hardware Support
--> |
Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
...
Design supports following carriers:
...
Additional HW Requirements:
...
Content
HTML |
---|
<!--
Remove unused content
--> |
For general structure and of the reference design, see Project Delivery
Design Sources
...
Additional Sources
...
Prebuilt
HTML |
---|
<!--
<table width="100%">
<tr> <th>File </th> <th>File-Extension</th> <th>Description </th> </tr>
<tr> <td>BIF-File </td> <td>*.bif </td> <td>File with description to generate Bin-File </td> </tr>
<tr> <td>BIN-File </td> <td>*.bin </td> <td>Flash Configuration File with Boot-Image (Zynq-FPGAs) </td> </tr>
<tr> <td>BIT-File </td> <td>*.bit </td> <td>FPGA Configuration File </td> </tr>
<tr> <td>DebugProbes-File </td> <td>*.ltx </td> <td>Definition File for Vivado/Vivado Labtools Debugging Interface </td> </tr>
<tr> <td>Debian SD-Image </td> <td>*.img </td> <td>Debian Image for SD-Card </td> </tr>
<tr> <td>Diverse Reports </td> <td> --- </td> <td>Report files in different formats </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf </td> <td>Exported Vivado Hardware Specification for SDK/HSI </td> </tr>
<tr> <td>LabTools Project-File </td> <td>*.lpr </td> <td>Vivado Labtools Project File </td> </tr>
<tr> <td>MCS-File </td> <td>*.mcs </td> <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) </td> </tr>
<tr> <td>MMI-File </td> <td>*.mmi </td> <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image </td> <td>*.ub </td> <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) </td> </tr>
<tr> <td>Software-Application-File </td> <td>*.elf </td> <td>Software Application for Zynq or MicroBlaze Processor Systems </td> </tr>
<tr> <td>SREC-File </td> <td>*.srec </td> <td>Converted Software Application for MicroBlaze Processor Systems </td> </tr>
</table>
-->
|
...
File
...
File-Extension
...
Description
...
Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
HTML |
---|
<!--
Add correct path:https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/TE0803/Reference_Design/2017.1/Starterkit
--> |
Reference Design is available on:
Design Flow
HTML |
---|
<!--
Basic Design Steps
Add/ Remove project specific
--> |
Note |
---|
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter for minimum setup
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project
- Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
- Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
- Create HDF and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
- Create Linux (uboot.elf and image.ub) with exported HDF
- HDF is exported to "prebuilt\hardware\<short name>"
Note: HW Export from Vivado GUI create another path as default workspace. - Create Linux images on VM, see PetaLinux KICKstart
- Use TE Template from /os/petalinux
Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
- Use TE Template from /os/petalinux
- HDF is exported to "prebuilt\hardware\<short name>"
- Add Linux files (uboot.elf and image.ub) to prebuilt folder
- "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
- "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
- Generate Programming Files with HSI/SDK
- Run on Vivado TCL: TE::sw_run_hsi
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
Note: See SDK Projects
- Run on Vivado TCL: TE::sw_run_hsi
Launch
Programming
HTML |
---|
<!--
Description of Block Design, Constrains...
BD Pictures from Export...
--> |
Note |
---|
Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
QSPI
Not used on this Example.
HTML |
---|
<!--
Example:
Connect JTAG and power on PCB
(if not done) Select
correct device and Xilinx install path on "design_basic_settings.cmd"
and create Vivado project with "vivado_create_project_guimode.cmd" or
open with "vivado_open_project_guimode.cmd", if generated.
Type on Vivado Console: TE::pr_program_flash_mcsfile -swapp u-boot
Note: Alternative use SDK or setup Flash on Vivado manually
Reboot (if not done automatically)
--> |
SD
- Copy image.ub and Boot.bin on SD-Card.
- For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
- Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
- Select SD Card as Boot Mode
Note: See TRM of the Carrier and Module. - Power On PCB
Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
- COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
- Linux Console:
Note: Wait until Linux boot finished For Linux Login use:- User Name: root
- Password: root
- You can use Linux shell now.
- I2C 0 Bus type: i2cdetect -y -r 0
- RTC check: dmesg | grep rtc
- ETH0 works with udhcpc
- USB type "lsusb" or connect USB2.0 device
...
SI5338_CLK0 Counter:
- Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
- Set radix from VIO signals to unsigned integer.
Note: Frequency Counter is inaccurate and displayed unit is Hz
- Set radix from VIO signals to unsigned integer.
SI5338 CLK is configured to 125MHz by default.
System Design - Vivado
HTML |
---|
<!--
Description of Block Design, Constrains...
BD Pictures from Export...
--> |
Block Design
PS Interfaces
...
Constrains
Basic module constrains
Code Block | ||||
---|---|---|---|---|
| ||||
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CFGBVS GND [current_design] |
Design specific constrain
No additional constrains.
Software Design - SDK/HSI
HTML |
---|
<!--
optional chapter
separate sections for different apps
--> |
For SDK project creation, follow instructions from:
Application
FSBL
TE modified 2017.2 FSBL
Changes:
- Si5338 Configuration see fsbl_hooks.c
- Add register_map.h, si5338.c, si5338.h
U-Boot
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
Software Design - PetaLinux
HTML |
---|
<!--
optional chapter
Add "No changes." or "Activate: -->List"
--> |
For PetaLinux installation and project creation, follow instructions from:
Config
No changes.
U-Boot
No changes.
Device Tree
Code Block | ||
---|---|---|
| ||
/include/ "system-conf.dtsi"
/ {
};
/* ethernet */
&gem0 {
phy-handle = <&phy0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: phy@1 {
compatible = "marvell,88e1510";
device_type = "ethernet-phy";
reg = <1>;
} ;
} ;
};
/* usb */
/{
usb_phy0: usb_phy@0 {
compatible = "ulpi-phy";
#phy-cells = <0>;
reg = <0xe0002000 0x1000>;
view-port = <0x0170>;
drv-vbus;
};
};
&usb0 {
dr_mode = "host";
//dr_mode = "peripheral";
usb-phy = <&usb_phy0>;
};
/* flash */
&flash0 {
compatible = "micron,n25q256a";
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <10000000>;
};
/* I2C */
&i2c0 {
#address-cells = <1>;
#size-cells = <0>;
rtc0: rtc@6F {
compatible = "isl12022";
reg = <0x6F>;
};
i2cmux_SFP: i2cmux@72 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x72>;
SFP@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
SFP@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
SFP@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
SFP@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
SFP@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
SFP@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
SFP@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
};
SFP@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
};
|
Kernel
Activate:
- USB_ULPI_BUS
- RTC_DRV_ISL12022
Rootfs
Activate:
- i2c-tools
Applications
startup
Script App to load init.sh from SD Card if available.
See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files
Additional Software
HTML |
---|
<!--
Add Description for other Software, for example SI CLK Builder ...
--> |
SI5338
Download ClockBuilder Desktop for SI5338
- Install and start ClockBuilder
- Select SI5338
- Options → Open register map file
Note: File location <design name>/misc/Si5338/RegisterMap.txt - Modify settings
- Options → save C code header files
- Replace Header files from FSBL template with generated file
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
HTML |
---|
<!--
Generate new entry:
1:add new row below first
2:Copy Page Information Macro(date+user) Preview, Page Information Macro Preview
3.Update Metadate =Page Information Macro Preview+1
--> |
...
...
...