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The Trenz Electronic TE0723 is a Arduino compatible FPGA module Zynq board with numerous on-board peripherals based on the Xilinx Zynq XC7Z010 SoC.

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Table 2: Overview of the Zynq SoC's PS/PL banks I/O signals

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Table 3: General overview of Zynq SoC PL/PS I/O bank

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Table 7: SD Card socket signals

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USB2 Interface

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Table 8: USB interface signals

ESP Wi-Fi Interface

Interface for the ESP8266 Wi-Fi module is provided through connector J5.

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High-speed USB2 interface is provided by USB3320 from Microchip (U18). The USB2 PHY is connected via ULPI interface to the Zynq SoC PS USB0, bank 501 and pins MIO28 ... MIO39.

The USB2 interface is accessible through the micro-USB2 B connector J8 and enables device, host or OTG modes. For host mode, the on-board USB2 interface provides the USB-VBUS supply voltage with nominal 4.75V to 5.25V on micro-USB2 connector pin J8-1. To configure host mode on this interface, the board has to be supplied with 5V through pin header J12 or with the USB-VBUS supply voltage of micro-USB2 connector J9, which is connected to the FTDI FT2232H chip.

The USB-VBUS supply voltage enabling the host mode on USB2 interface J8 is switched by the on-board power distribution switch AP2152SG-13 from Diodes Incorporated. The voltage is switched on with the signal 'VBUS_V_EN' which is controlled by the USB2 PHY U18. If the output load exceeds the current-limit threshold, the AP2152SG-13 limits the output current and pulls the over-current low-active logic output signal 'USB_OC' low, which is routed to the Zynq PL bank 35, pin F15.

An extra 100µF decoupling capacitor (in addition to 4.7µF) can be activated on-board to stabilize the USB-VBUS host supply voltage furthermore. This can be done by fitting and closing jumper J7, fitting 0-Ohm-resistor R53 or MOSFET transistor Q1. The transistor Q1 allows to enable and disable this 100µF extra capacitor by the signal 'HOST_MODE_EN' routed to the Zynq PL bank 34, pin L13.

Following table shows the signal assignment of the USB PHY U18 with the Zynq PS MIO bank 501:

Table 8: USB interface signals

ESP8266 Wi-Fi Interface

Interface for the ESP8266 Wi-Fi module is provided through connector J5.

Table 9: ESP8266 Wi-Fi module interface

I²C Interface

I²C interface pins SCL and SDA from the Zynq SoC PL bank 34 are connected to the connector J1. There are no on-board I²C slave devices. The two I²C bus lines 'SDA' and 'SCL' can be optionally pulled up to 3.3V on-board by fitting the 0-Ohm-resistors R35 ('SDA') and R42 ('SCL').

Table 10: Zynq SoC I²C interface

Analog Input Interface

The TE0723 board provides up to 7 muxed analog input pins to the XADC unit of the Zynq device. 6 pins are exposed to female pin header J4, 1 to male pin header J11. The pins are muxed by the TI High Speed CMOS 8-Channel Analog Multiplexer CD74HC4051 (U10). There is between the analog output of the multiplexer IC and the differential analog input of the Zynq device an operational amplifier (U11) configured in voltage-follower circuit transforming the single analog output signal of the multiplexer IC to the differential analog signal, which is connected to the differential XADC input pins of the Zynq device, pin G7, H7.

The analog input channels can be selected by the pins 'AMUX_SO', 'AMUX_S1' and 'AMUX_S2', which are connected to the Zynq PL bank 34, pin G12, H12, G11:

Table 11: Selecting multiplexer analog input channels

Another feature of the analog interface capacities of the XADC units of the Zynq device are the Auxiliary Analog Inputs of the Zynq device's PL bank 35 (see Xilinx document UG480, section 'Auxiliary Analog Inputs'). With 6 pins of female pin header J4 3 analog differential pairs can be created:

Table 12: Auxiliary Analog Inputs of the Zynq device

Note: These 6 auxiliary analog inputs pins are analog inputs are shared with PL bank pins and can be used as regular digital I/O's.

On-board Peripherals

DDR Memory

TE0723 module has up to 512-MBytes of DDR3L SDRAM arranged into 32-bit wide memory bus providing total of 1 GBytes of on-board RAM. Different memory sizes are available optionally.

Quad SPI Flash Memory

On-board quad SPI Flash memory S25FL127S (U5) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application storage. All four SPI data lines are connected to the Zynq SoC's PS, allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the bus width and clock frequency used.

FTDI FT2232H IC

The FTDI chip U3 converts signals from USB2.0 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip.
FTDI FT2232H chip is used in MPPSE mode for JTAG, 14 I/O's of Channel B are routed to PL bank 34 of the Zynq SoC and are usable for example as UART interface.

The configuration of FTDI FT2232H chip is stored with Xllinx License on EEPROM U6. Please note the warning in section "USB2 to JTAG/UART Adapter" to not overwrite or delete the Xilinx License on the EEPROM U6.

Microwire Serial EEPROM

There is a 2-Kbit (128 x 16-bit organization) Microwire compatible serial EEPROM 93AA56B (U6) connected to the FTDI FT2232H dual high-speed USB2 to multipurpose UART/FIFO (U3). This external EEPROM allows each of the FTDI FT2232H chip’s channels to be independently configured as a serial UART (RS232 mode), parallel FIFO (245) mode or fast serial (optical isolation). The external EEPROM can also be used to customize the USB VID, PID, serial number, product description strings and power descriptor value of the FT2232H for OEM applications. Other parameters controlled by the EEPROM include remote wake up, soft pull down on power-off and I/O pin drive strength.

High-speed USB2 ULPI PHY

Hi-speed USB2 ULPI PHY (U18) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq SoC's PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 3.3V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U14).

Oscillators

The module has following reference clock signals provided by on-board oscillators:

Table 13: Reference clock signals

On-board LEDs

There are three LEDs on-board TE0723:

Table 14: On-board LEDs

Push Buttons

The TE0723 board is equipped with one push buttons S1:

Table 15: Push buttons of the module

Power and Power-On Sequence

To power-up a module, power supply with minimum current capability of 1A is recommended.

Power Supply

5V power can be supplied by the external power supply through connector J12 or via USB connection to the host system through USB connector J8 or J9. Minimum current capability of 1A for external power supply is recommended.

Following diagram shows the dependencies of the power supply:

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Figure 3: Module power supply dependencies

Power Consumption

Power consumption is to be determined by the user and depends on SoC's FPGA design and connected hardware.

Table 16: Module power consumption

Power-On Sequence

There is no specific power-on sequence, system will power-up automatically when 5V is present either through J8, J9 or J12.

Voltage Monitor Circuit

The voltages 1.0V (core voltage) and 3.3V are monitored by the voltage monitor circuit U23, which generates the POR_B reset signal at power-on. A manual reset is also possible by driving the connector pin J3-3 ('EXT_RST') to GND (leave this pin unconnected or connect to VDD (3.3V) when unused) or press switch button S1, which is assigned to the signal 'NRST'.

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Figure 4: Voltage monitor circuit

Power Rails

The voltage direction of the power rails is directed at on-board connectors' view:

Table 17: Main power pin header description

Table 18: Power pin description of I/O pin header  

Table 19: Power pin description of peripheral connector

Bank Voltages

Table 20: Board bank voltages

Variants Currently in Production

Table 21: Board variants

Technical Specifications

Absolute Maximum Rating

Table 22: Board absolute maximum ratings

Recommended Operating Conditions

Table 23: Board recommended operating conditions

Table 6: ESP8266 Wi-Fi module interface

I²C Interface

I²C interface pins SCL and SDA from the Zynq SoC PL bank 34 are connected to the connector J1. There are no on-board I2C slave devices.

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Table 7: Zynq SoC I²C interface

On-board Peripherals

DDR Memory

TE0723 module has up to 512-MBytes of DDR3L SDRAM arranged into 32-bit wide memory bus providing total of 1 GBytes of on-board RAM. Different memory sizes are available optionally.

Quad SPI Flash Memory

On-board quad SPI Flash memory S25FL127S (U5) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application storage. All four SPI data lines are connected to the Zynq SoC's PS, allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the bus width and clock frequency used.

Dual High-speed USB to Multipurpose UART/FIFO

FT2232H... U3.

High-speed USB ULPI PHY

Hi-speed USB ULPI PHY (U18) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq SoC's PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 3.3V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U14).

Microwire Serial EEPROM

There is a 2-Kbit (128 x 16-bit organization) Microwire compatible serial EEPROM 93AA56B (U6) connected to the FTDI FT2232H dual high-speed USB to multipurpose UART/FIFO (U3). This external EEPROM allows each of the FTDI FT2232H chip’s channels to be independently configured as a serial UART (RS232 mode), parallel FIFO (245) mode or fast serial (optical isolation). The external EEPROM can also be used to customize the USB VID, PID, serial number, product description strings and power descriptor value of the FT2232H for OEM applications. Other parameters controlled by the EEPROM include remote wake up, soft pull down on power-off and I/O pin drive strength.

High-Speed Analog Multiplexer

TE0723 module has a on-board TI CD74HC4051 high-speed CMOS logic analog multiplexer (U10) with 8 analog inputs from connectors J4 and J11, and single analog output connected to the operational amplifier (see next section).

Low-power Operational Amplifier

8-input analog multiplexer output is connected to the on-board Microchip Technology MCP6001 operational amplifier (U11). Amplifier output is connected to the Zynq SoC's PS bank 0, XADC dedicated differential analog input pins VP_0 and VN_0.

Oscillators

The module has following reference clock signals provided by on-board oscillators:

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PS_CLK

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52.000000 MHz

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U1

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PS_CLK_500

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Zynq SoC PS subsystem main clock.

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OTG-RCLK

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52.000000 MHz

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REFCLK

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USB3320C PHY reference clock.

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FT2232H oscillator input.

Table 8: Reference clock signals.

On-board LEDs

There are three LEDs on-board TE0723:

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Green

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Green

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3.3V

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Table 9: On-board LEDs.

Power and Power-On Sequence

Power Supply

5V power can be supplied by the external power supply through connector J12 or via USB connection to the host system through USB connector J8 or J9. Minimum current capability of 1A for external power supply is recommended.

Power Consumption

Power consumption is to be determined by the user and depends on SoC's FPGA design and connected hardware.

Power-On Sequence

There is no specific power-on sequence, system will power-up automatically when 5V is present either through J8, J9 or J12.

Variants Currently in Production

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DDR3L

SDRAM

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ARM

Cores

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PL

Cells

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Block

RAM

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DSP

Slices

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Table 10: Module variants.

Technical Specifications

Absolute Maximum Ratings

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Parameter

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Units

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Reference Document

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VIN supply voltage

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V

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Storage temperature

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-40

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+85

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°C

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Table 11: TE0723 module absolute maximum ratings.

Recommended Operating Conditions

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Table 12: TE0723 module recommended operating conditions.

Physical Dimensions

• Module size: 68.58 mm × 53.34 mm.  Please download the assembly diagram for exact numbers.

• PCB thickness: 1.6 mm.

• Highest part on PCB: approx. 4 mm. Please download the step model for exact numbers.

Please note that two different units are used on the figures below, SI system millimeters (mm) and imperial system thousandths of an inch(mil). To convert mils to millimeters and vice versa use formula 100mil's = 2,54mm.

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Figure 3: TE0723 module physical dimensions.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.5: Board physical dimensions

Revision History

Hardware Revision History

Table 1324: TE0723 Board hardware revision history.

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Figure 6: TE0723 board hardware revision number

Document Change History

Table 1425: Document change history.

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