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The Trenz Electronic TE0821 is a powerful 4 x 5 cm MPSoC module integrated with a Xilinx Zynq UltraScale+ MPSoC. In addition, the module is equipped with a 2 2x 1 GB DDR4 SDRAM chip, 4Gb up to 128 Gb eMMC chip, 2x 64 MB flash memory for configuration and data storage, as well as powerful switching power supplies for all required voltages. The module is equipped with a Lattice Mach XO2 CPLD for system controlling. 3x Robust high-speed connectors provide a large number of inputs and outputs.
This module is pin compatible with Trenz Electronic TE0820 MPSoC modules (JM2 pin 100 is not connected).
The highly integrated modules are smaller than a credit card and are offered in several variants at an affordable price-performance ratio. Modules with a 4 x 5 cm form factor are completely mechanically and largely electrically compatible with each other.
All components cover at least the industrial temperature range from -40 ° C to + 85 ° C. The temperature range in which the module can be used depends on the customer design and the selected cooling. Please contact us for special solutions.
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- SoC/FPGA
- Package: SFVC784
- Device: ZU2 ...ZU5, *
- Engine: EG, CG, EV, *
- Speed: -1, -1L, -2, -2L, 3, *, **
- Temperature: I, E, *, **
- RAM/Storage
- 2x DDR4 SDRAM,
- Data Width: 16 Bit
- Size: 8 Gb, *
- Speed: 2400 Mbps, ***
- 2x QSPI boot Flash in dual parallel mode
- Data Width: 8 Bit
- Size: 512 Mb Gb, *
- 1x e.MMC Memory
- Data Width: 16 Bit
- Size: 8 Gb, *
- MAC address serial EEPROM
- On Board
- Lattice MachXO2 CPLD
- Programmable Clock Generator
- Hi-speed USB2 ULPI Transceiver
- 4x LEDS
- Interface
- 1 GB/s serial GMII Gbps RGMII Ethernet interface
- Hi-speed USB2 ULPI transceiver with full OTG support
- Graphic Processor Mali-400 MP2, *
- 156 34 x High Performance (HP) und 96 x High Density PL I/Os
- 14 x PS MIOs (6 of the MIOs intended for SD card interface in default configuration)
- 4 x serial PS GTR transceivers
- Power
- All power regulators on board
- Dimension
- Note
- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used U+ Zynq and DDR4 combination
- Rugged for shock and high vibration
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anchor | Figure_OV_BD |
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title | TE0821 block diagram |
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Main Components
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title | TE0821 main components |
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- Xilinx Zynq ZYNQ UltraScale+ XCZU3EGMPSoC, U1
- Red LED (ERR_OUT), D3
- Green LED (ERR_STATUS), D4
- Red LED (DONE), D1
- 10/100/1000 Mbps energy efficient ethernet transceiverEnergy Efficient Ethernet Transceiver, U8
- 8Gb DDR4, U2-U3
- 512 Mbit QSPI flash memory, U7-U17
- Green User LED, D2
- B2B connector Samtec Razor Beam, JM1
- Programmable clock generator, U10
- USB2.0 Transceiver, U18
- B2B connector Samtec Razor Beam, JM3
- B2B connector Samtec Razor Beam, JM2
- 8 GByte eMMC memory, U6
- Lattice Semiconductor MachXO2 System Controller CPLD, U21
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title | Initial delivery state of programmable devices on the module |
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Storage device name | Content | Notes |
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Dual QSPI Flash Memory | Not programmed |
| eMMC Memory | Not programmed |
| DDR4 SDRAM | Not programmed |
| Programmable Clock Generator | Not programmed |
| CPLD (LCMXO2-256HC) | Programmed | TE0821 CPLD |
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title | Boot process. |
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MODE Pin | Boot Mode |
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LowHigh | QSPI* | HighLow | SD Card* |
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*changable also with other CPLD Firmware: Please refer to the TE0821 CPLD.
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title | Reset process. |
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Signal | B2B | I/O | Note |
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EN | JM1-28 | Input | CPLD Enable Pin |
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title | General PL I/O to B2B connectors information |
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FPGA Bank | Type | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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24 | HD | JM2 | 24x I/O, 12x LVDS Pairs | Variable | Max voltage 3.3V | 25 | HD | JM1 | 24x I/O, 12x LVDS Pairs | Variable | Max voltage 3.3V | 26 | HD | JM1 | 24x I/O, 12x LVDS Pairs | Variable | Max voltage 3.3V | 44 | HD | JM2 | 24x I/O, 12x LVDS Pairs | Variable | Max voltage 3.3V | 65 | HP | JM2 | 18x I/O, 9x LVDS Pairs | Variable | Max voltage 1.8V | 65 | HP | JM3 | 16x I/O, 8x LVDS Pairs | Variable | Max voltage 1.8V | 505 | GTR | JM3 | 16x I/O, 8x LVDS Pairs | - | 4x lanes | 505 | GTR CLK | JM3 | 1x Diff Clock | - |
| 501 | MIO | JM1 | 15 I/O | 3.3V |
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Test Point | Signal | Connected to | Notes |
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1 | I2C_SCL | EEPROM, U25 |
| 2 | I2C_SDA | EEPROM, U25 |
| 3 | SRST_B | FPGA Bank 503 | PSCONFIG | 4 | PS_CLK | FPGA Bank 503 | PSCONFIG | 5 | PROG_B | FPGA Bank 503 | PSCONFIG | 6 | INIT_B | FPGA Bank 503 | PSCONFIG | 7 | DONE | Red LED, D1 |
| 8 | PS_LP0V85 | Voltage Regulator, U12 |
| 9 | DDR_2V5 | Voltage Regulator, U4 |
| 10 | PS_AVCC | Voltage Regulator, U9 |
| 11 | DDR_1V2 | Voltage Regulator, U15 |
| 12 | PS_AVTT | Voltage Regulator, U3U13 |
| 13 | PS_FP0V85 | Voltage Regulator, U26 |
| 14 | POR_B | Voltage Translator, U19 |
| 15 | PS_PLL | Voltage Regulator, U23 |
| 16 | PL_VCCINT | Voltage Regulator, U5 |
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anchor | Table_PWR_BV |
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title | Zynq SoC bank voltages. |
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FPGA Bank | Schematic | Voltage | Note |
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Bank 24 HD | VCCO_HD24_2444 | Variable | Max voltage 3.3V | Bank 25 HD | VCCO_HD25_26 | Variable | Max voltage 3.3V | Bank 26 HD | VCCO_HD25_26 | Variable | Max voltage 3.3V | Bank 44 HD | VCCO_HD24_44 | Variable | Max voltage 3.3V | Bank 64 HP | VCCO_64 | N.C | Not Connected | Bank 65 HP | VCCO_65 | Variable | Max voltage 1.8V | Bank 66 HP | VCCO_66 | 1.8V |
| Bank 500 PSMIO | VCCO_PSIO0_500 | 1.8V |
| Bank 501 PSMIO | VCCO_PSIO1_501 | 3.3V |
| Bank 502 PSMIO | VCCO_PSIO2_502 | 1.8V |
| Bank 503 PSCONFIG | VCCO_PSIO3_503 | 1.8V |
| Bank 504 PSDDR | DDR_1V2 | 1.2V |
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- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
Include Page |
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| PD:6 x 6 SoM LSHM B2B ConnectorsPD: |
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| 6 x 6 SoM LSHM B2B Connectors |
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Include Page |
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| PD:4 x 5 SoM LSHM B2B ConnectorsPD: |
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| 4 x 5 SoM LSHM B2B Connectors |
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Description | Min | Max | Unit | Notes |
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VIN supply voltage | -0.3 | 7 | V | See EN6347QI and TPS82085SIL datasheets | 3.3VIN supply voltage | -0.1 | 3.630 | V | Xilinx DS925 and TPS27082L datasheet | PS I/O supply voltage, VCCO_PSIO | -0.5 | 3.630 | V | Xilinx document DS925 | PS I/O input voltage | -0.5 | VCCO_PSIO + 0.55 | V | Xilinx document DS925 | HP I/O bank supply voltage, VCCO | -0.5 | 2.0 | V | Xilinx document DS925 | HP I/O bank input voltage | -0.55 | VCCO + 0.55 | V | Xilinx document DS925 | HD I/O bank supply voltage, VCCO | -0.5 | 3.4 | V | Xilinx document DS925 | HD I/O bank input voltage | -0.55 | VCCO + 0.55 | V | Xilinx document DS925 | PS GTR reference clocks absolute input voltage | -0.5 | 1.1 | V | Xilinx document DS925 | PS GTR absolute input voltage | -0.5 | 1.1 | V | Xilinx document DS925 | Voltage on SC CPLD pins | -0.5 | 3.75 | V | Lattice Semiconductor MachXO2 datasheet | Storage temperature | -40 | +85 | °C | See eMMC datasheet |
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Document Change History
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Date | Revision | Contributor | Description |
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dateFormat | yyyy-MM-dd |
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| | 2021-07-05 | v.61 | John Hartfiel | Update download Link - Update Change history
| 2021-06-07 | v.59 | Vadim Yunitski | | 2020-07-15 | v.50 | Pedram Babakhani | | -- | all | Page info |
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