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Scroll Title
anchorTable_SIP_B2B
titleGeneral overview of PL I/O signals and SoM's interfaces connected to the B2B connectors

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B2B ConnectorInterfacesI/O Signal CountNotes
J1User IO72 single ended or 36 differential9x Pmod
6 LEDred
2 Push Button-
7 MIOJ7 (not assembled), TE0724: 3.3V
2 MIOJ9 (not assembled), TE0724: 1.8V
1 MIO LEDgreen
1 MIO Push Button-
I²C21x Pmod
SD IO7-
UART2-
CAN2-
GbE PHY_MDIO + PHY_LEDs10-
JTAG4-
Power GPIO2-
Power/Reset/Fuse programming3-
Bootmode2-



microUSB JTAG/UART Interface

There is no device with JTAG port on the baseboard. The microUSB connector provides JTAG access to the module is provided through B2B connector J1. This is routed to the carriers USB to JTAG/UART bridge, routed to B2B connector J1. The UART is routed via a levelshifter. There is no device with JTAG port on the baseboard.

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titleJTAG pins connection

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JTAG Signal

B2B Connector Pin

TCKJ1-147
TDIJ1-151
TDOJ1-145
TMSJ1-149
UART RXJ1-36
UART TXJ1-38


SD Card Interface

Scroll Title
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titleSD Card interface signals and connections

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Connected ToSignal NameNotes
J1-34SD-CDCard detect switch, pulled up, low if card inserted.
J1-24SD-D0
J1-22SD-CMD
J1-20SD-CCLK
J1-26SD-D1
J1-28SD-D2
J1-30SD-D3


...

There are no I2C devices on the base board. Pullup resistors have to be provided by the module.

On-board Peripherals

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Pmods

Pmods

The GPIOs of the 10 Pmods (J10 The GPIOs of the 10 Pmods (J10 to J17, J20, J21) are connected with 100 Ohm differential routing to the B2B connector. J21 is a pure I2C compatible Pmod, without additional signals. The other 9 are GPIO Pmods where despite J20 all others can be used as dual Pmods.

Via dip switsches switches S6-1 to S6-3the variable bank power B_VCCIO_35 for the Pmods J10, J11, J12, J13, J14, J16 can be selected. Respect power regulator limits!

Scroll Title
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titlePmod connections.

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J10J11J12J13J14
PINSignalB2BSignalB2BSignalB2BSignalB2BSignalB2B
1PA0_PJ1-56PB2_NJ1-70PC2_PJ1-57PD2_PJ1-77PE2_NJ1-90
2PA0_NJ1-58PB2_PJ1-72PC2_NJ1-55PD2_NJ1-75PE2_PJ1-92
3PA3_P

J1-46

PB0_NJ1-76PC0_PJ1-51PD0_PJ1-71PE0_NJ1-96
4PA3_NJ1-48PB0_PJ1-78PC0_NJ1-49PD0_NJ1-69PE0_PJ1-98
5GND-GND-GND-GND-GND-
6VCCIO_35J1-54VCCIO_35J1-54VCCIO_35J1-54VCCIO_35J1-54VCCIO_35J1-54
7PA1_NJ1-62PB3_PJ1-68PC3_NJ1-59PD3_NJ1-79PE3_PJ1-88
8PA1_PJ1-60PB3_NJ1-66PC3_PJ1-61PD3_PJ1-81PE3_NJ1-86
9PA2_NJ1-52PB1_PJ1-82PC1_NJ1-45PD1_NJ1-65PE1_PJ1-102
10PA2_PJ1-50PB1_NJ1-80PC1_PJ1-47PD1_PJ1-67PE1_NJ1-100
11GND-GND-GND-GND-GND-
12B_VCCIO_35J1-54B_VCCIO_35J1-54B_VCCIO_35J1-54B_VCCIO_35J1-54B_VCCIO_35J1-54



J15J16J17J20J21
PINSignalB2BSignalB2BSignalB2BSignalB2BSignalB2B
1PG2_NJ1-110PF2_PJ1-97PH2_PJ1-115PI2_PJ1-133NC-
2PG2_PJ1-112PF2_NJ1-95PH2_NJ1-113PI2_NJ1-131NC-
3PG0_PJ1-114PF0_PJ1-91PH0_PJ1-111PI0_PJ1-129I2C_SCLJ1-142
4PG0_NJ1-116PF0_NJ1-89PH0_NJ1-109PI0_NJ1-127I2C_SDAJ1-144
5GND-GND-GND-GND-GND-
63.3VJ1-74, J1- 43VCCIO_35J1-543.3VJ1-74, J1- 433.3VJ1-74, J1- 433.3VJ1-74, J1- 43
7PG3_PJ1-108PF3_NJ1-99PH3_NJ1-117PI3_NJ1-135NC-
8PG3_NJ1-106PF3_PJ1-101PH3_PJ1-119PI3_PJ1-137NC-
9PG1_NJ1-120PF1_NJ1-85PH1_NJ1-105PI1_NJ1-123I2C_SCLJ1-142
10PG1_PJ1-121PF1_PJ1-87PH1_PJ1-107PI1_PJ1-125I2C_SDAJ1-144
11GND-GND-GND-GND-GND-
123.3VJ1-74, J1- 43B_VCCIO_35J1-543.3VJ1-74, J1- 433.3VJ1-74, J1- 433.3VJ1-74, J1- 43

USB to JTAG/UART bridge

The TEB0724 carrier board has on-board microUSB 2.0 (J4) high-speed to UART/FIFO IC FT2232H (U1) from FTDI. Channel A can be used as JTAG Interface (MPSSE) to program on module JTAG devices. Channel B can be used as UART Interface routed via a level shifter to the 1.8V section of the B2B connector, usually connected to the PS of the SoM. There is also a 256-byte serial EEPROM connected to the FT2232H chip pre-programmed with license code to support Xilinx programming tools.

Warning

Do not access the FT2232H EEPROM using FTDI programming tools, doing so will erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license the on-board JTAG will not be accessible any more with any Xilinx tools. Software tools from FTDI website do not warn or ask for confirmation before erasing user EEPROM content.

CAN Screw Terminal

The CAN bus is routed to screw terminal J2.

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titleCAN bus connection

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CAN Screw Terminal

The CAN bus is routed to screw terminal J2.

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titleCAN bus connection

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 PINSignalB2B
J2-1CAN0_NJ1-1
J2-2GND
J2-3CAN0_PJ1-3


Jumpers on J22-1 to J22-3 and J22-2 to J22-4 connect proper split termination resistors to the CAN bus.

Pin Header

Pin Header J6 provides access to power functions, bootmode selection and PMIC In-Circuit Programming (For initial PMIC In-Circuit Programming of the module, Diode D28 has to be removed).

Scroll Title
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titlePin Header J6

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 PINSignalB2B
J6-1VINJ1-154, J1-156, J1-158, J1-160
J6-2VINJ1-154, J1-156, J1-158, J1-160
J6-3GND
J6-4GND
J6-5I2C_SCLJ1-142
J6-6VBATJ1-152
J6-7I2C_SDAJ1-144
J6-8PWR_GPIO2J1-143
J6-9ONKEYJ1-148
J6-10PWR_GPIO4J1-141
J6-11PWR_TPJ1-146
J6-12RESETREQJ1-150
J6-13MODE0J1-2
J6-14GND
J6-15MODE1J1-4
J6-16GND



Alternatively to selecting B_VCCIO_35 by using S6 dip switches, VCCIO_35 ( e.g. SoM TE0724, Bank 35) can be selected by removing R45 and adding a jumper on optional J19. In table 18 valid jumper positions are given. Voltages and maximum current ratings could be found in the corresponding TRM of the attached module, (e.g. TE0724 TRM#PowerRails ).

Jumpers on J22-1 to J22-3 and J22-2 to J22-4 connect proper split termination resistors to the CAN bus.

Oscillators

The module has the following reference clock signals provided by on-board oscillators:

Scroll Title
anchorTable_OBP_CLKPHJ19
titleReference clock signalsOptional Pin Header J19

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Clock SourceSchematic NameFrequencyClock Destination
SiTime SiT8008AI oscillator, U4OSCI12.000000 MHz U1, pin 3.

...

 PINSignalB2B
J19-1VLDO1J1-83
J19-2GND
J19-3VCCIO_35J1-54
J19-4VLDO2J1-94

J19-5

VLDO34J1-53
J19-6GND




Scroll Title
anchorTable_OBP_LEDVSJ19
titleOn-board LEDsJ19 Jumper settings for VCCIO_35 voltage selection

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Color

LED Jumper positionSignalDescription and Notes
D1greenVINpower indicator
D2-D7redULED1..6User LED
D8greenMIO9

MIO user LED

J3BgreenPHY_LED0Ethernet status
J3CyellowPHY_LED1Ethernet status

On-board Push Buttons

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anchorTable_OBP_PB
titleOn-board Push Button

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S2

...

PS MIO user button, pulled up, on push de-asserted

e.g. TE0724

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J19  1-3



VLDO1



3.3V

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J19  4-3



VLDO2



1,8V

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J19  5-3



VLDO34



2,5V




Warning

Respect VLDO current limitations!

Optional fitted headers J7, J8 and J9 are to provide full access to the Pins at the B2B connector, especially for testing and extension purposes.  Description follows below.

PL Button and LED IOs are additionally routed to optionally assembled pin header J8.

Dip-Switches

Dip-switch S6-1..3 are used to select the adjustable board power. Tabel 14 shows the signals, table 15 how to adjust the switches for corresponding B_VCCIO_35 Voltages.

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anchorTable_OBP_DIS
titleDip-Switches

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S6-3

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Scroll Title
anchorTable_OBP_DSSPHJ8
titleSelect B_VCCIO_35 via Dip-Switches.Optional Pin Header J8

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S6-3
 PINSignalB2B
J8-1B_VCCIO_35S6-1S6-23.3VONONON
2.5VOFFONON

1.8V

ONOFFON
1.5VOFFOFFON
1.25VONONOFF
1.2VOFFONOFF

Pin Header

J1-43, J1-74
J8-2GND
J8-3S4J1-126
J8-4S2J1-124
J8-5ULED5J1-130
J8-6ULED6J1-128
J8-7ULED3J1-134
J8-8ULED4J1-132
J8-9ULED1J1-138
J8-10ULED2J1-136



Optional pin header J7 gives access to otherwise not used PS MIO IOs at a 3.3V bankPin Header J6 provides access to power functions, bootmode selection and PMIC In-Circuit Programming (For initial PMIC In-Circuit Programming of the module, Diode D28 has to be removed).

Scroll Title
anchorTable_OBP_PHJ6PHJ7
titleOptional Pin Header J6J7

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 PINSignalB2B
J6-1VINJ1-154, J1-156, J1-158, J1-160
J6-2VINJ1-154, J1-156, J1-158, J1-160
J6-3GNDJ6-4GND
J6-5I2C_SCLJ1-142
J6-6VBATJ1-152
J6-7I2C_SDAJ1-144
J6-8PWR_GPIO2J1-143
J6-9ONKEYJ1-148
J6-10PWR_GPIO4J1-141
J6-11PWR_TPJ1-146
J6-12RESETREQJ1-150
J6-13MODE0J1-2
J6-14GND
J6-15MODE1J1-4
J6-16GND
B2B
J7-13.3V43, 74
J7-2GND
J7-3GND
J7-4MIO8J1-14
J7-5MIO10J1-31
J7-6MIO11J1-33
J7-7MIO12J1-35
J7-8MIO13J1-37
J7-9MIO14J1-39
J7-10MIO15J1-41



Optional pin header J9 gives access to otherwise not used PS MIO IOs at a 1.8V bankAlternatively to selecting B_VCCIO_35 by using S6 dip switches, VCCIO_35 ( e.g. SoM TE0724, Bank 35) can be selected by removing R45 and adding a jumper on optional J19. In table 18 valid jumper positions are given. Voltages and maximum current ratings could be found in the corresponding TRM of the attached module, (e.g. TE0724 TRM#PowerRails ).

J19  1-3

VLDO1

3.3V

J19  4-3

VLDO2

1,8V

J19  5-3

VLDO34

2,5V

Scroll Title
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titleOptional Pin Header J19J9.

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 PINSignalB2B
J19J9-1VLDO11.8VJ1-8363
J19J9-2GND
J19J9-3GND
J9-4MIO_46J1-32
J9-5MIO_50VCCIO_35J1-5440
J19J9-46VLDO2MIO_PB

J1

-94

J19-5

VLDO34J1-53
J19-6GND
Scroll Title
anchorTable_OBP_VSJ19
titleJ19 Jumper settings for VCCIO_35 voltage selection
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Jumper positionSignale.g. TE0724
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Warning

Respect VLDO current limitations!

Optional fitted headers J7, J8 and J9 are to provide full access to the Pins at the B2B connector, especially for testing and extension purposes.  Description follows below.

...

-42


On-board Peripherals

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USB to JTAG/UART bridge

The TEB0724 carrier board has on-board microUSB 2.0 (J4) high-speed to UART/FIFO IC FT2232H (U1) from FTDI. Channel A can be used as JTAG Interface (MPSSE) to program on module JTAG devices. Channel B can be used as UART Interface routed via a level shifter to the 1.8V section of the B2B connector, usually connected to the PS of the SoM. There is also a 256-byte serial EEPROM connected to the FT2232H chip pre-programmed with license code to support Xilinx programming tools.

Warning

Do not access the FT2232H EEPROM using FTDI programming tools, doing so will erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license the on-board JTAG will not be accessible any more with any Xilinx tools. Software tools from FTDI website do not warn or ask for confirmation before erasing user EEPROM content.

Oscillators

The module has the following reference clock signals provided by on-board oscillators:

Scroll Title
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titleReference clock signals

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Clock SourceSchematic NameFrequencyClock Destination
SiTime SiT8008AI oscillator, U4OSCI12.000000 MHz U1, pin 3.


On-board LEDs

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titleOn-board LEDs

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LED ColorSignalDescription and Notes
D1greenVINpower indicator
D2-D7redULED1..6User LED
D8greenMIO9

MIO user LED

J3BgreenPHY_LED0Ethernet status
J3CyellowPHY_LED1Ethernet status


On-board Push Buttons

Scroll Title
anchorTable_OBP_PHJ8PB
titleOptional Pin Header J8On-board Push Button

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43, J1-74126
 PINButtonSignalB2BDescription and Notes
S1ONKEYJ8-13.3VJ1-148Power Button, pulled up, on push de-asserted
S3RESETREQJ8-2GNDJ8-3S4J1-
J8-4S2J1-124
J8-5ULED5J1-130
J8-6ULED6J1-128
J8-7ULED3J1-134
J8-8ULED4J1-132
J8-9ULED1J1-138
J8-10ULED2J1-136
150User LED pulled up, on push de-asserted

S2

S2J1-124PL user button, pulled up, on push de-asserted
S4S4J1-126PL user button, pulled up, on push de-asserted
S5MIO51J1-42

PS MIO user button, pulled up, on push de-asserted


Dip-Switches

Dip-switch S6-1..3 are used to select the adjustable board power. Tabel 14 shows the signals, table 15 how to adjust the switches for corresponding B_VCCIO_35 VoltagesOptional pin header J7 gives access to otherwise not used PS MIO IOs at a 3.3V bank.

Scroll Title
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titleOptional Pin Header J7Dip-Switches

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 PINSignalB2B
J7-13.3V43, 74
J7-2GNDJ7-3GND
J7-4MIO8J1-14
J7-5MIO10J1-31
J7-6MIO11J1-33
J7-7MIO12J1-35
J7-8MIO13J1-37
J7-9MIO14J1-39
J7-10MIO15J1-41

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SwitchSignal
S6-1VADJ_VS0
S6-2VADJ_VS1

S6-3

VADJ_VS2
S6-4NC




Scroll Title
anchorTable_OBP_PHJ9DSS
titleSelect B_VCCIO_35 via Dip-SwitchestitleOptional Pin Header J9.

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J9-1J1-42
B_VCCIO_35S6-1S6-2S6-3
3.3VONONON
2.5VOFFONON
 PINSignalB2B

1.8V

ONJ1-63J9-2GNDJ9-3GND
J9-4MIO_46J1-32
J9-5MIO_50J1-40
OFFON
1.5VOFFOFFON
1.25VONONOFF
1.2VOFFONOFFJ9-6MIO_PB


Power and Power-On Sequence

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Scroll Title
anchorTable_TS_AMR
titleRecommended Operating Conditions.

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ParameterMinMaxUnitsReference Document
VIN supply voltage04.55.5VDepends mostly on attached SoM, values here are for TE0724 PMIC, da9062_3v4.pdfCAN Transceiver, MCP2542FD.
Operating temperature-2570°CPush buttons datasheet.


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Page properties
hiddentrue
idComments

In 'Physical Dimension' section, top and button view of moduloe must be insterted, information regarding physical dimention can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part)for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02//www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

Documents/AD-TE0745-02-30-1I.PDF

Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .



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titlePhysical Dimension


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titlePhysical Dimension

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Currently Offered Variants

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titleHardware Revision Number.

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Document Change History

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titleDocument change history.

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Date

Revision

Contributors

Description

Page info
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Page info
infoTypeModified by
dateFormatyyyy-MM-dd
typeFlat

  • Update Recommended Operating Conditions

v.50Martin Rohrmüller
  • Update to TRM 2.4 style
  • Corrected Table 15
  • Added Comment on Module PMIC in Circuit Programming



v.31

Martin Rohrmüller


  • Splitted table 9 in two parts

v.30

Martin Rohrmüller

Update to REV02

  • Two DCDCs added, changes in the entire document

v.29Martin Rohrmüller
  • Added Figure J19 Jumper settings
  • updated Table counter

v.28Martin Rohrmüller
  • Updated assembly pictures
  • Added typical power consumption
  • Added hints on power rail voltages

v.27Martin Rohrmüller
  • Updated link to TE0724

v.26Martin Rohrmüller
  • Changed VCCIO_35 connection:
    R45 not placed , J19 placed

v.25Martin Rohrmüller
  • include B2B infos from general page

v.24Martin Rohrmüller
  • corrected links to connector datasheets

v.23John Hartfiel
  • style update

2018-07-10

v.19

Martin Rohrmüller

  • Initial document.



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