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changes.mady.by.user Pedram Babakhani

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  • MPSoC:  XCZU2CG - Xilinx Zynq UltraScale+ MPSoC
    • Package: 1SBVA484E
    • Speed Grade: -1 (Slowest)

    • Temperature Grade: Expanded Extended (0 to +128 °C100 °C)

  • RAM/Storages:
    • SDRAM: LPDDR4 -3733 8Gb 256Mx32256Mx16x 2 
    • SPI Flash 256Mb (32M x 8) 133 MHz
    • EEPROMs 2Kb (256 x 8)
    • EEPROMs 4Kb (512 x 8)
  • Interfaces: 
    • USB JTAG/UART microUSB
    • 1GB Ethernet RJ45
    • USB 3.0 Host (Type A Connector)
    • microSD Card
    • M.2 SSD PCIe
    Display Interfaces: 
    • 3.5 mm Earphone Jack (PWM Output)
    • Display Port
    • VGA
    • 4 Digit 7-Segment LED Display
    • 8 LEDs
    Audio:
    • 3
    • .5 mm Earphone Jack (PWM Output)
    Input:
    • 5 User Buttons
    • 8 Bit Slide Switches
    • Reset Button
    User I/O:
    • 2x Pmod Connector
  • Communication:
    • 1GB Ethernet RJ45
    • USB 3.0 Host (Type A Connector)
  • Debug
    • USB JTAG/UART microUSB
  • Power
    • 5 V +/
    Power
    • 5 V +/- 10%
    • ~3.5 W
  • Dimension: 100mm x 100mm

...

Scroll Title
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titleTE0802 Block Diagram


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Main Components

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Bootmode signals must be set through DIP Switch S9S1. 

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titleBoot Process

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MODE Signal State

MODE2

S9-C

MODE1

S9S1-2(B)

MODE0

S9S1-1(A)

Boot Mode

MODE[2:0]=000

OFFOFFOFF

JTAG

MODE[2:0]=001

OFFOFFONQSPI (24 bit)not supported

MODE[2:0]=010

OFF

ONOFFQSPI(32 bit)

MODE[2:0]=011

OFF

ONONSD0(2.0)
MODE[2:0]=111ONONONUSB(2.0)


Reset setting is available through Push Button BTN6.

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Scroll Title
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titleGeneral I/O to Pin Header and Connectors Information

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12
FPGA BankConnector I/O Signal CountVoltage LevelNotes
Bank 503Micro USB, J8 (over FTDI)4 Single Ended3.3 VJTAG
Bank 500Micro USB, J8 (over FTDI)2 Single Ended3.3 VUART
Bank 500Micro SD Card, J97 Single Ended3.3 V
Bank 502Micro SD CardETH RJ45, J4 (over ETH PHY)14 Single Ended1.8 V
Bank 505, 502USB 3.0, J11 (USB2 over USB PHY)2 Differential Pairs, 12 Single Ended-- / 1.8V0.85 V

Bank 505, 501

SSD M.2, U5

2 Differential Pairs

0.85 V

Bank 501SSD M.2

,

U5

5 Single Ended

-- / 3.3 V


Bank 505, 501Display Port Connector, J32 Differential Pairs0.85 VBank 26D-Sub Host Socket, J72 , 5 Single Ended--/ 3.3 V
Bank 26, 65, 66,D-Sub Host Socket (VGA), J714 Single Ended3.3 V / 1.8 V / 1.8 V
Bank 65Earphone, J123 Single Ended1.8 V
Bank 500Grove Connector, J102 Single Ended3.3 V
Bank 26Pmod Host Socket, J58 Single Ended3.3 V
Bank 26Pmod Host Socket, J6 8 Single Ended3.3 V


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Scroll Title
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titleMicro SD Card Connector Information

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SchematicConnected toNotes
SD_DAT0

MIO 13, FPGA Bank 500


SD_DAT1MIO 14, FPGA Bank 500
SD_DAT2MIO 15, FPGA Bank 500
SD_DAT3MIO 16, FPGA Bank 500
SD_CLKMIO 22, FPGA Bank 500
SD_CMDMIO 21, FPGA Bank 500
SD_CDMIO 24, FPGA Bank 500


RJ45 Connector

TE0802 is equipped with a RJ45 connector and an Ethernet PHYs. RJ45 connector J4 is connected to Ethernet PHYs U6.

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titleRJ45 Connector Information

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PinSchematicETH PinNotes
2PHY_MDI0_PMDIP[0]
3PHY_MDI0_NMDIN[0]
4PHY_MDI1_PMDIP[1]
5PHY_MDI1_NMDIN[1]
6PHY_MDI2_PMDIP[2]
7PHY_MDI2_NMDIN[2]
8PHY_MDI3_PMDIP[3]
9PHY_MDI3_NMDIN[3]


USBs Sockets

TE0802 is equipped with a Micro USB2.0 B connector J8 and a USB3.0 connector J11.

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titleUSB3.0 A Socket Information

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USB3.0 PinSchematicConnected toNotes
D-USB0_D_NUSB PHY, U22
D+USB0_D_PUSB PHY, U22
StdA_SSRX-USB_RX2_NFPGA Bank 505
StdA_SSRX+USB_RX2_PFPGA Bank 505
StdA_SSTX-USB_TX2_NFPGA Bank 505
StdA_SSTX+USB_TX2_PFPGA Bank 505
VBUSVBUSUSB PHY, U22


SSD M.2 Connector

TE0802 is equipped with a SSD M.2 connector (U5).

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titleSSD M.2 Connector Information

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PinSchematicConnected toNotes
PERn0/SATA-B+

SSD_RX3_N

Pin M22, FPGA Bank 505
PERp0/SATA-B-SSD_RX3_PPin M21, FPGA Bank 505
PERn0/SATA-A+

SSD_TXC3_N

Pin K22, FPGA Bank 505
PERp0/SATA-A-SSD_TXC3_PPin M21, FPGA Bank 505
REFCLKN

SSD_RCLK_N

Pin 9, Clock Generator U8
REFCLKPSSD_RCLK_PPin 10, Clock Generator U8
DAS/DSS#SSD_DASMIO35, FPGA Bank 501
DEVSLPSSD_SLEEPMIO32, FPGA Bank 501
PERST#SSD_PERSTnMIO31, FPGA Bank 501
CLKREQ#SSD_CLKRQMIO33, FPGA Bank 501
PEWake#SSD_WAKEMIO34, FPGA Bank 501


Display Port Connector

TE0802 is equipped with a Display Port connector (J3).

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titleDisplay Port Socket Information

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SchematicCorresponding SignalsConnected toNotes
DP_TX_L0_P/NDP0_TX_P/NPin A19/A20, FPGA Bank 505
DP_TX_L1_P/NDP1_TX_P/NPin C19/C20, FPGA Bank 505
DP_TX_AUX_P/NDP_AUX_TX/RXMIO27, MIO30, FPGA Bank 501


D-Sub Connector

TE0802 is equipped with a D-Sub connector (J7).

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titleD-Sub Connector Information

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SchematicCorresponding SignalsConnected toNotes
VGA_REDVGA_R0...3Bank 65Red Channel
VGA_GREENVGA_G0...3Bank 65Green Channel
VGA_BLUEVGA_B0...3Bank 66Blue Channel
VGA_RGB_HSYNCVGA_HSBank 26Horizontal Sync
VGA_RGB_VSYNCVGA_VSBank 26Vertical Sync

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Headphone Connector

TE0802 is equipped with a headphone connector (J12).

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titleHeadphone Connector Information

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SchematicConnected toNotes
JACKSNSPin F3, FPGA Bank 65
PWM_RPin F4, FPGA Bank 65
PWM_LPin E3, FPGA Bank 65


Grove Connector

TE0802 is equipped with a grove connector (J10).

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titleGrove Connector Information

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SchematicConnected toNotes
Grove_SCL0MIO18, FPGA Bank 500
Grove_SDA0MIO19, FPGA Bank 500


Pmod Sockets

TE0802 has 2 Pmod 2x6 host sockets which are connected to the FPGA.

Scroll Title
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titlePmod SMD Host Socket Information

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DesignatorSignalsConnected to Notes
J5PMOD_A0...7Bank 26J6PMOD_B0...7Bank 26
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DesignatorSignalsConnected to Notes
J5PMOD_A0...7Bank 26
J6PMOD_B0...7Bank 26


Test Points

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titleTest Points Information

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Test Point

SignalsNotes
TP1+1.1V_LPDDR4
TP2+1.8V_MGTRAVTT
TP3+1.8V_PL
TP4FT_B_TX
TP5DP_TX_PWR
TP6GND
TP7GND
TP8PMIC2_SDA
TP9PMIC2_TP
TP10ONKEY2
TP11PMIC2_SCL
TP12DP_TX_HPD
TP13DP_TX_PWR
TP14INT_SCL1
TP15INT_SDA1
TP16FT_B_RX
TP17CLOCKDIST_OE
TP18+0.85V_VCCINT
TP19+3.3V
TP20+1.8V_PS
TP21ERR_STATUS
TP22+1.2V_PSPLL
TP23GND
TP24GND
TP25PMIC1_SCA
TP26PMIC1_SDA
TP27ONKEY1
TP28PMIC1_TP
TP29POR_B
TP30PSBATT
TP31SRST_B
TP32DONE
TP33INIT_B
TP34VBUS
TP35USB_VBUS
TP36PROG_B
TP37ERR_OUT


On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

...

Scroll Title
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titleOn-board Peripherals

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Chip/InterfaceDesignatorNotes
Quad SPI Flash Memory81199613U16
LPDDR4 SDRAM81199613U13
EEPROM81199613U2, U18
USB ULPI PHY81199613U22
Ethernet PHY81199613U6
FTDI FT2232H81199613U17
Clock Generator81199613U8
OscillatorsU7, U15, U19, U23, U43
7-Segment Display81199613D9
User LED81199613LED0...7
Push Button81199613BTN1...5
DIP Switch81199613S1, S7../S.8


Quad SPI Flash Memory

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

he TE0802 evaluation board has  one single QSPI flash connected as x4. Flash size depends on the assembly option, default 32MB

Scroll Title
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titleQuad SPI Interface MIOs and Pins

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MIO PinSchematicU16 PinNotes
MIO0MIO0B2SPI_CLK
MIO1MIO1D2SPI_DQ1
MIO2MIO2C4SPI_DQ2
MIO3MIO3D4SPI_DQ3
MIO4MIO4D3SPI_DQ0
MIO5MIO5C2SPI_CS


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The TE0802 evaluation board has 1 GByte volatile LPDDR4 SDRAM IC (U13) for storing user application code and data. The details depends on the assembly option.

  • Part number: K4F8E304HB_MGC IS43LQ32256A-062BLI
  • Supply voltage: 1.06 -1.8 17 V
  • Speed: 3733 Mbps 1600 MHz 
  • Temperature: -55 40 to +125 85 C

EEPROM


Scroll Title
anchorTable_OBP_FPGA_EEP
titleI2C FPGA EEPROM Interface MIOs and Pins

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MIO PinSchematicU2 PinNotes
MIO8Int_SCL1SCL
MIO9Int_SDA1SDA


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Scroll Title
anchorTable_OBP_I2C_FPGA_EEP
titleI2C Address for FPGA EEPROM

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MIO PinTypeI2C AddressDesignatorNotes
MIO8...94AA025E48T-I/OT0x50U2EEPROM with MAC



Scroll Title
anchorTable_OBP_FTDI_EEP
titleI2C FTDI EEPROM Interface Pins

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PinSchematicU18 PinNotes
CSEECS1FTDI
CLKEECLK2FTDI
DIN/DOEEDATA3/4FTDI


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The TE0802 is equipped with an Ethernet PHY (U6) which is connected to RJ45 (JJ4) connector. 

Scroll Title
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titleEthernet PHY Connections and Pins

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Ethernet PHY PinSignal Schematic NamesETHNote
TXD0ETH_TXD0MIO65, FPGA Bank 502
TXD1ETH_TXD1MIO66, FPGA Bank 502
TXD2ETH_TXD2MIO67, FPGA Bank 502
TXD3ETH_TXD3MIO68, FPGA Bank 502
TX_CTRLETH_TXCTLMIO69, FPGA Bank 502
TX_CLKETH_CLKMIO64, FPGA Bank 502
MDIOETH_MDIOMIO77, FPGA Bank 502Pulled-up to +1.8V_PS.
MDCETH_MDCMIO76, FPGA Bank 502
MDIP[0]

PHY_MDI0_P

Pin2, J4 (RJ45)
MDIN[0]PHY_MDI0_NPin3, J4 (RJ45)
MDIP[1]

PHY_MDI1_P

Pin4, J4 (RJ45)
MDIN[1]PHY_MDI1_NPin5, J4 (RJ45)
MDIP[2]

PHY_MDI2_P

Pin6, J4 (RJ45)
MDIN[2]PHY_MDI2_NPin7, J4 (RJ45)
MDIP[3]

PHY_MDI3_P

Pin8, J4 (RJ45)
MDIN[3]PHY_MDI3_NPin9, J4 (RJ45)
LED[0]PHY_LED0LED, J4 (RJ45)
LED[1]PHY_LED1LED, J4 (RJ45)
CONFIG--Pulled-up to +1.8V_PS.
XTAL_INETH_XTAL_INPin 3, U7 (Oscillator)
RESETnETH_RSTMIO37, FPGA Bank 501Pulled-up to +1.8V_PS.
RX_CLKETH_RXCKMIO70, FPGA Bank 502
RX_CTRLETH_RXCTLMIO75, FPGA Bank 502
RXD[0]ETH_RXD0MIO71, FPGA Bank 502
RXD[1]ETH_RXD1MIO72, FPGA Bank 502
RXD[2]ETH_RXD2MIO73, FPGA Bank 502
RXD[3]ETH_RXD3MIO74, FPGA Bank 502


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Scroll Title
anchorTable_OBP_CLK_GEN
titleClock Generator Connections and Pins

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Clock Generator PinSignal Schematic NamesConnected toNote
REFP-Pin 3, U43 (Oscillator)
REFSELREFSEL-Pulled-up to +3.3V.
RESETN/SYNCCLK_GEN_RESETPin B5, FPGA Bank 26Pulled-up to +3.3V.
EEPROMSELEEPROMSEL-Pulled-up to +3.3V.
SDA/GPIO2CLK_GEN_SDA

- (Default)

MIO9, FPGA Bank 500 (R185/196 required)

Pin 2, J14 (Pin Header required)

Pulled-up to +3.3V. (Default)

Pulled-up to +3.3V.

Pulled-up to +3.3V.

SCL/GPIO3CLK_GEN_SCL

- (Default)

MIO8, FPGA Bank 500 (R185/196 required)

Pin 3, J14 (Pin Header required)

Pulled-up to +3.3V. (Default)

Pulled-up to +3.3V.

Pulled-up to +3.3V.

OE/GPIO4--Pulled-up to +3.3V.

Y1P

CLK_Y1_P / CLK_DP_PPin G19, FPGA Bank 50527 MHz
Y1NCLK_Y1_N / CLK_DP_NPin G20, FPGA Bank 50527 MHz

Y2P

CLK_Y2_P / CLK_USB_PPin J19, FPGA Bank 50526 MHz
Y2NCLK_Y2_N / CLK_USB_NPin J20, FPGA Bank 50526 MHz

Y3P

CLK_Y3_P / CLK_PCIe_PPin L19, FPGA Bank 505100 MHz
Y3NCLK_Y3_N / CLK_PCIe_NPin L20, FPGA Bank 505100 MHz

Y4P

CLK_Y4_P / SSD_RCLK_PPin 55, U5 (M.2)100 MHz
Y4NCLK_Y4_N / SSD_RCLK_NPin 53, U5 (M.2)100 MHz


Clock Sources

Scroll Title
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titleOscillators

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DesignatorSignal Schematic NamesConnected toDescriptionFrequencyNote
U7ETH_XTAL_INPin 34, U6 (Ethernet PHY)Clock for Ethernet25 MHz
U15PS_CLKPin H14, FPGA Bank 503Clock for FPGA33 MHz
U23USB_CLK / USB0_RCLKPin 26, U22 (USB PHY)Clock for USB52 MHz
U43-Pin 5, U8 (Clock Generator)Clock for Clock Generator25 MHz


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Scroll Title
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titleDIP Switches

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DesignatorSchematicConnected toFunctionalityNote
S1AS1-1(A)MODE0Pin J16, FPGA Bank 503DIPPulled-down to GND.
S1BS1-2(B)MODE1Pin H15, FPGA Bank 503DIPPulled-down to GND.
S1CS1-3(C)USER_CFG0Pin A4, FPGA Bank 66DIPPulled-down to GND.
S1DS1-4(D)USER_CFG1Pin B4, FPGA Bank 66DIPPulled-down to GND..
S7-1(A)S7AUSER_SW7Pin M5, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S7BS7-2(B)USER_SW6Pin M4, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S7CS7-3(C)USER_SW5Pin J2, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S7DS7-4(D)USER_SW4Pin K1, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S8AS8-1(A)USER_SW3Pin L1, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S8BS8-2(B)USER_SW2Pin M1, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S8CS8-3(C)USER_SW1Pin P2, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S8DS8-4(D)USER_SW0Pin P3, FPGA Bank 65DIPPulled-up to +1.8V_PL.


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Scroll Title
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titlePower Distribution


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Power-On Sequence

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titlePower Sequency
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TBD

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PMICs will be reset after pressing Push Button BTN6 (POR_B).

Power Rails

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titleModule Power Rails

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Power Rail NameDirectionNotes
VINInINSupply Voltage
+5VOutJ1...2
+3.3VOutJ14, J10


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Scroll Title
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titleAbsolute Maximum Ratings

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SymbolsDescriptionMinMaxUnit
VINInput Supply Voltage (J13)-3.57V
T_STGStorage Temperature-40
50
85
V
°C


Recommended Operating Conditions

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titleRecommended Operating Conditions

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ParameterMinMaxUnitsReference Document
VIN45.5VSchematic "POWER" (Component: LTC4365ITS8)
T_STG085°CZynq Ultrascale+ Data sheet


Physical Dimensions

Module size: 100 mm × 100 mm.  Please download the assembly diagram for exact numbers.

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Scroll Title
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titleTrenz Electronic Shop Overview

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Trenz Shop TE0702 TE0802 Overview Page
English pageGerman page


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Scroll Title
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titleHardware Revision History

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DateRevisionChangesDocumentation Link
2019-04-2902
  • Added suppressor 1SMA5.0AT3G on power input
  • Changed OV and UV protection range
  • Changed VGA schematic
  • USB page: VBUS resistor changed on 1KThe revision has been renamed as TE0802-02-2AEV2-A
REV02
2018-10-1701ReleaseREV01


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

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titleDocument Change History

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DateRevisionContributorDescription

Page info
infoTypeModified date
dateFormatyyyy-MM-dd
typeFlat

Page info
infoTypeCurrent version
prefixv.
typeFlat
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Page info
infoTypeModified by
typeFlat
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Initial Release

  • Typo correction
2020-11-19v.65Pedram Babakhani
  • initial release

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all

Page info
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  • --


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