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Bank | Type | Connector | I/O Signal Count | Voltage | Notes |
---|---|---|---|---|---|
34 | HR | J1 | 8 | 3.3V | Signal Schematic names: 'SCL', 'SDA', 'D8' ... 'D13'. |
34 | HR | J2 | 8 | 3.3V | Signal Schematic names: 'RXD', 'TXD', 'D2' ... 'D7'. |
34 | HR | J6 | 8 | 3.3V | Signal Schematic names: 'PIO01' ... 'PIO08'. |
34 | HR | J11 | 1 | 3.3V | Signal Schematic name: 'AIN_FPGA'. |
35 | HR | J4 | 6 | 3.3V | Signal Schematic names: 'AIN0' ... 'AIN5', usable as single ended of differential analog input inputs or regular digital I/O's. |
35 | HR | J5 | 1 | 3.3V | Connector dedicated to ESP8266 module. |
500 | MIO | J10 | 7 | 3.3V | SDIO interface to SD Card socket. |
501 | MIO | J5 | 4 | 3.3V | Connector dedicated to ESP8266 module . |
Table 2: Overview of the Zynq SoC's PS/PL banks I/O signals
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Bank | Type | VCCIO | I/O Signal Count | Available on Connectors | Notes |
---|---|---|---|---|---|
34 | HR | 3.3V | 44 | 25 | 8 user I/O's on Pmod connector J6, female pin header J1 and J2 each. 1 I/O on pin header J11. |
35 | HR | 3.3V | 8 | 7 | 6 user I/O's on female pin header J4, 1 user I/O on female pin header J5. |
500 | PS MIO | 3.3V | 15 | - | 6 MIO pins used for QSPI flash memory interface, 7 MIO pins used for SD Card interface, 1 MIO pin connected to red LED D2, 1 MIO pin as reset pin routed to USB PHY U18, 'POR_B'-signal is connected to voltage monitor circuit 23. |
501 | PS MIO | 3.3V | 16 | 4 | 12 MIO pins used for USB ULPI interface, 4 MIO pins used for ESP8266 interface header J5. |
0 | Config | 3.3V | 54 | - | 4 I/O's are dedicated to JTAG interface, 'PROG_B'-signal is connected to voltage monitor circuit 23. |
Table 3: General overview of Zynq SoC PL/PS I/O bank
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Button | Signal Schematic Name | Connected to | Notes |
---|---|---|---|
S1 | 'NRST' | Voltage Monitor Circuit, U23 | Triggers system reset. |
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Board Variant | Xilinx Zynq SoC | DDR3L SDRAM | ARM Cores | PL Cells | LUTs | Flip-Flops | Block RAM | DSP Slices | Zynq SoC Operating Temp. | Temp. Range |
---|---|---|---|---|---|---|---|---|---|---|
TE0723-02 | XC7Z010-1CLG225C | 128 MBytes | Dual-core | 28K | 17,6K | 35,2K | 2.1 MBytes | 80 | 0°C to +85°C | Commercial |
TE0723-03M | XC7Z010-1CLG225C | 512 MBytes | Dual-core | 28K | 17,6K | 35,2K | 2.1 MBytes | 80 | 0°C to +85°C | Commercial |
TE0723-03-07S-1C | XC7Z007S-1CLG225C | 512 MBytes | Single-core | 23K | 14,4K | 28,8K | 1.8 MBytes | 66 | 0°C to +85°C | Commercial |
Table 21: Board variants
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Parameter | Min | Max | Units | Reference Document |
---|
VIN supply voltage
V
Storage temperature
-40
+85
°C
Table 22: Board absolute maximum ratings.
5V power supply voltage | 4.75 | 5.25 | V | USB2.0 VBUS voltage specification |
HR PL I/O banks input voltage (VCCIO single ended) | -0.4 | VCCO + 0.55 | V | Xilinx datasheet DS187 (VCCO 3.3V nominal) |
PS MIO I/O banks input voltage (VCCIO single ended) | -0.4 | VCCO + 0.55 | V | Xilinx datasheet DS187 (VCCO 3.3V nominal) |
Analog Multiplexer IC pins input voltage | 0 | 3.3V | V | TI CDx4HC405x data sheet |
Storage temperature | -40 | +85 | °C | WL-SMCW SMD LED data sheet |
Table 22: Board absolute maximum ratings
Parameter | Min | Max | Units | Reference Document |
---|---|---|---|---|
5V power supply voltage | 4.75 | 5.25 | V | USB2.0 VBUS voltage specification |
HR PL I/O banks input voltage (VCCIO single ended) | -0.20 | VCCO + 0.20 | V | Xilinx datasheet DS187 (VCCO 3.3V nominal) |
PS MIO I/O banks input voltage (VCCIO single ended) | -0.20 | VCCO + 0.20 | V | Xilinx datasheet DS187 (VCCO 3.3V nominal) |
Analog Multiplexer IC pins input voltage | 0 | 3.3V | V | TI CDx4HC405x data sheet |
Operating Temperature Commercial | 0 | +85 | °C | Xilinx datasheet DS190 |
Table 23: Board recommended operating conditions
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Note |
---|
Please check Xilinx datasheet DS187 for complete list of absolute maximum and recommended operating ratings for the Zynq-7 device. |
...
Please note that two different units are used on the figures below, SI system millimeters (mm) and imperial system thousandths of an inch(mil). To convert mils to millimeters and vice versa use formula 100mil's = 2,54mm.
Figure 5: Board physical dimensions
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Date | Revision | Notes | PCN | Documentation Link |
---|---|---|---|---|
2016-07-15 | 03 | Refer to Changes list in Schematic for further details in changes to REV02 | - | TE0723-03 |
2015-11-06 | 02 | Second Production Release | - | TE0723-02 |
- | 01 | First Production Release | - | - |
...
Figure 6: TE0723 board hardware revision number
Date | Revision | Contributors | Description | ||||||||
---|---|---|---|---|---|---|---|---|---|---|---|
| Ali Naseri, |
|
Table 25: Document change history.
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