Page History

Custom_table_size_100

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Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM"

Template Change history:

Version	Changes	Author
4.2	Changes Xilinx to AMD	ED
4.1	Minor changes Notes Tables	ED
4.0	Rework for smaller TRM which can be generated faster Reduce Signal Interfaces Pin Reduce On Board Perihery Reduce Power Move Configuration Signals from Overview to own section	JH
3.12	Version History changed from list to table all changed title-alignment for tables from left to center	ma
3.11	update "Recommended Operating Conditions" section
3.1	New general notes for temperature range to "Recommended Operating Conditions"
3.02	add again fix table of content with workaround to use it for pdf and wiki Export Link for key features examples Notes for different Types (with and without Main FPGA) Export Link for Signals, Interfaces and Pins examples Notes for different Types (Modul, Modul Hypride, Evalboard, Carrier)
3.01	remove fix table of content and page layout ( split page layout make trouble with pdf export) changed and add note to signal and interfaces, to on board periphery section ...(not finished)
3.00	→ separation of Carrier/Module and evaluation kit TRM
2.15	add excerpt macro to key features
2.14	add fix table of content add table size as macro

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Important General Note:

If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

Figure template:

Scroll Title

anchor	Figure_anchorname
title-alignment	center
title	Text

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, objects are only linked.

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Table template:
- Layout macro can be use for landscape of large tables

Scroll Title

anchor	Table_tablename
title-alignment	center
title	Text

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Example	Comment
1	2

The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below
- <type>_<main section>_<name>
  - type: Figure, Table
  - main section:
    - "OV" for Overview
    - "SIP" for Signal Interfaces and Pins,
    - "OBP" for On board Peripherals,
    - "PWR" for Power and Power-On Sequence,
    - "B2B" for Board to Board Connector,
    - "TS" for Technical Specification
    - "VCP" for Variants Currently in Production
    - "RH" for Revision History
  - name: custom, some fix names, see below
- Fix names:
  - "Figure_OV_BD" for Block Diagram
  - "Figure_OV_MC" for Main Components
  - "Table_OV_IDS" for Initial Delivery State
  - "Table_PWR_PC" for Power Consumption
  - "Figure_PWR_PD" for Power Distribution
  - "Figure_PWR_PS" for Power Sequence
  - "Figure_PWR_PM" for Power Monitoring
  - "Table_PWR_PR" for Power Rails
  - "Table_PWR_BV" for Bank Voltages
  - "Table_TS_AMR" for Absolute_Maximum_Ratings
  - "Table_TS_ROC" for Recommended_Operating_Conditions
  - "Figure_TS_PD" for Physical_Dimensions
  - "Table_VCP_SO" for TE_Shop_Overview
  - "Table_RH_HRH" for Hardware_Revision_History
  - "Figure_RH_HRN" for Hardware_Revision_Number
  - "Table_RH_DCH" for Document_Change_History
Use Anchor in the document: add link macro and add "#<anchorname>
Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>

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-----------------------------------------------------------------------

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Note for Download Link of the Scroll ignore macro:

Link to the base folder of the module (remove de/ or en/ from the URL):
Example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5_Carriers/TE0728/

Scroll Ignore
Download PDF version of this document.

Overview

The Trenz Electronic TE0808 is an industrial grade MPSoC SOM integrating an AMD Zynq UltraScale+ MPSoC, DDR4 SDRAM with 64-Bit width data bus connection, SPI Boot Flash memory for configuration and operation, transceivers and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking connections in a compact 5.2 cm x 7.6 cm form factor.

Refer to http://trenz.org/te0808-info for the current online version of this manual and other available documentation.

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Notes :

short description of the PCB
Short Link of the wiki resources reference:
- Use short link the Wiki Resource page, for example: http://trenz.org/te0728-info
- List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

Key Features

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Note:
'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

→ See examples fro different types <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-KeyFeatures

Excerpt

SoC
- Device: ZU6 / ZU9 / ZU15 ^{1) 2)}
- Engine: CG / EG ¹⁾
- Speedgrade: -1 / -2 ¹⁾
- Temperature Range: Extended / Industrial ¹⁾
- Package: FFVC900
RAM/Storage
- 4 GByte DDR4 SDRAM ³⁾
- 2 x 64 MByte Serial Flash ⁴⁾
- EEPROM with MAC address
On Board
- Oscillator
Interface
- 4 x B2B Connector (ST5)
  - up to 204 PL IO
    - HP: 156
    - HD: 48
  - up to 65 PS MIO
  - 4 GTR
  - 16 GTH
  - I2C, JTAG, CONFIG
Power
- 3.3 V power supply via B2B Connector needed ⁵⁾.
Dimension
- 76 mm x 52 mm
Notes
¹⁾ Please, take care of the possible assembly options. Furthermore, check whether the power supply is powerful enough for your FPGA design.
²⁾ without PCIe Core on PL, see XMP104
³⁾ Up to 8 GByte are possible with a maximum bandwidth of 2400 MBit/s.
⁴⁾ Please, take care of the possible assembly options.
⁵⁾ Dependent on the assembly option a higher input voltage may be possible

Block Diagram

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add drawIO object in Scroll Ignore section and add reference image in Scroll Only.

Note
For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .

Note

Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name.

Example: TE0812 Block Diagram

Note

All created DrawIOs should be named according to the Module name:

Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD

Scroll Title

anchor	Figure_OV_BD
title-alignment	center
title	TE0808 block diagram

Scroll Ignore

draw.io Diagram

border	true

diagramName	TE0808_OV_BD
simpleViewer	false
links	auto
tbstyle	top
lbox	true
diagramWidth	641
height	895
revision	1

Scroll Only
Image Added

Main Components

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Notes :

Picture of the PCB (top and bottom side) with labels of important components
Add List below

Note
For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .

Scroll Title

anchor	Figure_OV_MC
title-alignment	center
title	TE0808 main components

Scroll Ignore

draw.io Diagram

border	true

diagramName	TE0808_OV_MC
simpleViewer	false
links	auto
tbstyle	top
lbox	true
diagramWidth	740
height	1030
revision	1

Scroll Only
Image Added

SoC, U1
DDR4, U2, U3, U9, U12
Quad SPI Flash, U7, U17
Connector, J1, J2, J3, J4
EEPROM, U4
Clock Generator, U5
Oscillator, U25, U32
Done LED D1

Initial Delivery State

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Note

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

Scroll Title

anchor	Table_OV_IDS
title-alignment	center
title	Initial delivery state of programmable devices on the module

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Storage device name	Content	Notes
DDR4 SDRAM	not programmed
Quad SPI Flash	not programmed
EEPROM	not programmed besides factory programmed MAC address
Programmable Clock Generator	not programmed

Signals, Interfaces and Pins

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For subsection examples see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-Signals,InterfacesandPins

Note
Table with all connectors and Designtor List of different interfaces per connector IO CNT (for FPGA IOs where functionality can be changed by customer)

Connectors

Scroll Title

anchor	Table_SIP_C
title-alignment	center
title	Board Connectors

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orientation	portrait
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repeatTableHeaders	default
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cellHighlighting	true

Connector Type	Designator	Interface	IO CNT	Notes
B2B	JM1	MGT PL	12 x MGT (RX/TX)
B2B	JM1	HP	52 SE / 24 DIFF
B2B	JM2	MGT PS	2 x MGT CLK
B2B	JM2	CLK	4 x DIFF CLK	PLL
B2B	JM2	MGT PL	4 x MGT (RX/TX)
B2B	JM2	MGT PS	4 x MGT (RX/TX)
B2B	JM2	CFG¹⁾	1 x JTAG
B2B	JM2	CFG¹⁾	4 x MODE
B2B	JM2	CFG¹⁾	1 x I2C	PLL, EEPROM
B2B	JM2	CFG¹⁾	34 CTRL/Status
B2B	JM3	HD	48 SE / 24 DIFF
B2B	JM3	MGT PL	3 x MGT CLK
B2B	JM3	CLK	DIFF CLK	PLL
B2B	JM3	MIO	65 PS GPIO
B2B	JM4	HP	104 SE / 48 DIFF

¹⁾ see Configuration and System Control Signals

Test Points

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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.

Example:

Test Point	Signal	Notes¹⁾
TP1	PWR_PL_OK

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

Scroll Title

anchor	Table_SIP_TPs
title-alignment	center
title	Test Points Information

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orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
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cellHighlighting	true

Test Point	Signal	Notes
TP1	PLL_SCL	pulled-up to PS_1V8
TP2	PLL_SDA	pulled-up to PS_1V8
TP3	LP_DCDC
TP4	DCDCIN
TP5	GND
TP6	TCK
TP7	PL_DCIN
TP8	GND
TP9	GT_DCDC
TP10	GND
TP11	TDI
TP12	TDO
TP13	TMS
TP14	PS_1V8
TP15	No Net Name	REF3312AIDCKT (U33) ouput voltage
TP16	FP_0V85
TP17	DDR_2V5
TP18	DDR_PLL
TP19	PL_VCCINT
TP20	AUX_R
TP21	AVTT_R
TP22	AUX_L
TP24	AVCC_R
TP26	AVTT_L
TP28	AVCC_L
TP30	PS_PLL
TP31	PS_AVTT
TP32	LP_0V85
TP33	PS_AUX
TP34	PS_AVCC
TP36	POR_B	pulled-up to PS_1V8

On-board Peripherals

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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection

Example:

Chip/Interface	Designator	Connected To	Notes
ETH PHY	U10	B2B connector J1 SoC MIO	Gigabit ETH PHY

Scroll Title

anchor	Table_OBP
title-alignment	center
title	On board peripherals

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sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Chip/Interface	Designator	Connected To	Notes
DDR4 SDRAM	U2, U3, U9, U12	SoC - PS
Quad SPI Flash	U7, U17	SoC - PS	Booting.
EEPROM	U4	B2B - J2
Clock Generator	U5	B2B - J2 SoC, - MGT
Oscillator	U25	Clock Generator	25 MHz
Oscillator	U32	SoC - PS	33.333333 MHz

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For example subsections see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-On-boardPeripherals

Configuration and System Control Signals

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Overview all Controller signals, like Reset, Boote Mode, JTAG Interface(Connector or USB In case of FTDI)...
In case it's connected to CPLD always link to CPLD description and add not from the current implementation here(in case it's available)

Scroll Title

anchor	Table_OV_CNTRL
title-alignment	center
title	Controller signal.

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orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
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cellHighlighting	true

Connector+Pin	Signal Name	Direction¹⁾	Description
JM2-77	EN_PLL_PWR	IN	Enable PLL power supply.
JM2-79	EN_GT_L	IN	Enable left GTH transceiver power-up.
JM2-80	PG_PLL_1V8	OUT	SI_PLL_1V8 power rail powered-up.
JM2-81	PLL_FINC	IN	PLL Frequency incrementation.
JM2-82	PG_PSGT	OUT	GTR transceivers powered-up.
JM2-83	MR	IN	Manual reset.
JM2-84	EN_PSGT	IN	Enable GTR transceiver power-up.
JM2-85	PLL_LOLn	OUT	Loss of lock status.
JM2-86	ERR_STATUS	OUT	PS error status ²⁾.
JM2-87	PLL_SEL1	IN	PLL clock selection.
JM2-88	ERR_OUT	OUT	PS error indication ²⁾.
JM2-89	PLL_RST	IN	PLL reset.
JM2-90	PLL_SCL	IN	I2C clock. Pulled up to PS_1V8.
JM2-91	PG_GT_R	OUT	Right GTH Transceivers powered-up.
JM2-92	PLL_SDA	IN/OUT	I2C data. Pulled up to PS_1V8.
JM2-93	PLL_SEL0	IN	PLL clock selection.
JM2-94	PLL_FDEC	IN	PLL Frequency decrementation.
JM2-95	EN_GT_R	IN	Enable right GTH transceiver power-up.
JM2-96	SRST_B	IN	System reset ²⁾. Pulled-up to PS_1V8.
JM2-97	PG_GT_L	OUT	Left GTH Transceivers powered-up.
JM2-98	INIT_B	IN/OUT	Initialization completion indicator after POR ²⁾. Pulled-up to PS_1V8.
JM2-100	PROG_B	IN/OUT	Power-on reset ²⁾. Pulled-up to PS_1V8.
JM2-101	EN_PL	IN	Enable programable logic power-up.
JM2-102	EN_FPD	IN	Enable full-power domain power-up.
JM2-103 / JM2-105 / JM2-107 / JM2-109	MODE3..0	IN	Boot mode selection ²⁾: JTAG QUAD-SPI (32 Bit) SD1 (2.0) eMMC (1.8 V) SD1 LS (3.0) Supported Modes depends also on used Carrier.
JM2-104	PG_PL	OUT	Programmable logic powered-up. Pulled-up to PL_DCIN.
JM2-106	LP_GOOD	OUT	Low-power domain powered-up. Pulled up to LP_DCDC.
JM2-108	EN_LPD	IN	Enable low-power domain power-up.
JM2-110	PG_FPD	OUT	Full-power domain powered-up. Pulled-up to DCDCIN.
JM2-112	EN_DDR	IN	Enable DDR power-up.
JM2-114	PG_DDR	OUT	DDR power supply powered-up. Pulled-up to DCDCIN.
JM2-116	DONE	OUT	PS done signal ²⁾. Pulled-up to PS_1V8.
JM2-119 / JM2-121	DX_P / DX_N	-	SoC temperatur sensing diode pins ²⁾.
JM2-120 / JM2-122 / JM2-124 / JM2-126	TCK / TDI / TDO / TMS	Signal-dependent	JTAG configuration and debugging interface. JTAG reference voltage: PS_1V8
JM2-125	PSBATT	IN	PS RTC Battery supply voltage ^{2) 3)}.
JM2-127	PUDC_B	IN	Configuration pull-ups setting ²⁾. Pulled-up to PL_1V8.

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

²⁾ See UG1085 for additional information.

Power and Power-On Sequence

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Enter the default value for power supply and startup of the module here.

Order of power provided Voltages and Reset/Enable signals

Link to Schematics, for power images or more details

Power Rails

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List of all Powerrails which are accessible by the customer

Main Power Rails and Variable Bank Power

Scroll Title

anchor	Table_PWR_PR
title-alignment	center
title	Module power rails.

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sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
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cellHighlighting	true

Power Rail Name/ Schematic Name	Connector + Pin	Direction¹⁾
VCCO_66	JM1-90 / JM1-120	IN
VREF_66	JM1-108	IN
PL_1V8	JM1-91 / JM1-121	OUT
PL_DCIN	JM1-151 / JM1-153 / JM1-155 / JM1-157 / JM1-159	IN
LP_DCDC	JM2-138 / JM2-140 / JM2-142 / JM2-144	IN
DCDCIN	JM2-153 / JM2-154 / JM2-155 / JM2-156 / JM2-157 / JM2-158 / JM2-159 / JM2-160	IN
PS_1V8	JM2-99 / JM3-147 / JM3-148	OUT
PS_BATT	JM2-125	IN
DDR_1V2	JM2-135	OUT
VCCO_48	JM3-15 / JM3-16	IN
VCCO_47	JM3-43 / JM3-44	IN
PLL_3V3	JM3-152	IN
SI_PLL_1V8	JM3-151	OUT
GT_DCDC	JM3-157 / JM3-158 / JM3-159 / JM3-160	IN
VCCO_64	JM4-58 / JM4-106	IN
VREF_64	JM4-88	IN
VCCO_65	JM4-69 / JM4-105	IN
VREF_65	JM4-15	IN

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

Recommended Power up Sequencing

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List baseboard design hints for final baseboard development.

The power up sequencing highly depends on the use case. In general, it should be possible to enable/disable the processing system (PS) / programmable logic (PL) independently. Furthermore, within the processing logic it should be possible to enable/disable only low-power domain and/or low-power and full-power domain. Additionally, usage of GTR for PS side and GTH for PL side should be possible. GTH transceivers on left and right side are usable independently. Because of this flexibility the needed parts of the following table needs to be selected individually. For detailed information take a look into schematics. Attention: PL usage is not completely independent of PS side. For PL usage it is necessary to enable PS low-power domain.

Scroll Title

anchor	Table_BB_DH
title-alignment	center
title	Baseboard Design Hints

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Sequence	Net name	Recommended Voltage Range	Pull-up/down	Description	Notes
0	-	-	-	Configuration signal setup.	See Configuration and System Control Signals.
1 ¹⁾	PSBATT	1.2 V ... 1.5 V	-	Battery connection.	Battery Power Domain usage. When not used, tie to GND.
2	Processing System (PS):			Procedure for PS starting.
2.1	Low-power domain:			Bring-up for low-power domain PS.
2.1.1	LP_DCDC	3.3 V (± 5 %) ²⁾	-	Low-power domain power supply.	Main module power supply for low-power domain. 5.5 A recommended. Power consumption depends mainly on design and cooling solution.
2.1.2	EN_LPD	-	-	Low-power domain power enable.
2.1.3	LP_GOOD	-	PU ³⁾, LP_DCDC	Low-power domain power good status.	Module power-on sequencing for low-power domain finished.
2.2	Full-power domain:			Bring-up for full-power domain PS.	Full-power PS domain needs powered low-power PS domain.
2.2.1	DCDCIN	3.3 V (± 5 %) ²⁾		Full-power domain and GTR transceiver power supply.	Main module power supply for full-power domain. 7 A recommended. Power consumption depends mainly on design and cooling solution.
2.2.2	EN_FPD	DCDCIN	-	Full-power domain power enable.
2.2.3	PG_FPD	-	PU ³⁾, DCDCIN	Full-power domain power good status.	Module power-on sequencing for full-power domain finished.
2.2.4	EN_DDR	DCDCIN	-	DDR memory power enable.
2.2.5	PG_DDR	-	PU ³⁾, DCDCIN	DDR memory power good status.	Module power-on sequencing for DDR memory finished.
2.3	GTR Transceiver			Procedure for GTR transceiver starting.	PS transceiver usage needs powered PS (low- and full-power domain).
2.3.1	EN_PSGT	DCDCIN	-	GTR transceiver power enable.
2.3.2	PG_PSGT	-	-	GTR transceiver power good status.	Module power-on sequencing for GTR transceiver finished.
2	Programmable Logic (PL)			Procedure for PL starting.	PL usage needs powered PS low-power domain.
2.1	PL_DCIN	3.3 V (± 5 %) ²⁾	-	Programmable logic power supply.	Main module power supply for programmable logic. 12 A recommended. Power consumption depends mainly on design and cooling solution.
2.2	EN_PL	-	PU ³⁾, PL_DCIN	Programmable logic power enable.
2.3	PG_PL	-	PU ³⁾, PL_DCIN	Programmable logic power good status.	Module power-on sequencing for programmable logic finished. Periphery and variable bank voltages can be enabled on carrier.
2.4	VCCO_47 / VCCO_48 / VCCO_64 / VCCO_65 / VCCO_66	⁴⁾	-	Module bank voltages.	Enable bank voltages after PG_PL deassertion.
3	GTH / GTY Transceiver			Procedure for GTH / GTY transceiver starting.	PL transceiver usage needs powered PL and low-power PS domain.
3.1	GT_DCDC	3.3 V (± 5 %) ²⁾	-	GTH transceiver power supply.	Main module power supply for GTH transceiver. 5 A recommended. Power consumption depends mainly on design and cooling solution.
3.2¹⁾	EN_PLL_PWR	-	-	PLL power enable.
3.2¹⁾	PG_PLL_1V8	-	-	PLL power good status.
3.2¹⁾	PLL_3V3	3.3 V (± 5 %)		PLL power supply
3.3	EN_GT_L / EN_GT_R	GT_DCDC	-	GTH / GTY left / right transceiver power enable.	Transceivers on left / right side can be used independently.
3.4	PG_GT_L / PG_GT_R	-	-	GTH / GTY transceiver power good status.
4	MR			Manual Reset	Low active release after all needed power domains are enabled.

¹⁾ Optional

²⁾ Dependent on the assembly option a higher input voltage may be possible.

³⁾ On module

⁴⁾ See DS925 for additional information.

Board to Board Connectors

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This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series,
For example: 6 x 6 SoM LSHM B2B Connectors
Include Page
6 x 6 SoM LSHM B2B Connectors
6 x 6 SoM LSHM B2B Connectors

Include Page

	5.2 x 7.6 UltraSoM+ ST5 and SS5 B2B Connectors
	5.2 x 7.6 UltraSoM+ ST5 and SS5 B2B Connectors

Technical Specifications

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List of all Powerrails which are accessible by the customer

Main Power Rails and Variable Bank Power add boarder one time maximum Rating (Board will damaged)

Absolute Maximum Ratings ^*)

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title-alignment	center
title	Absolute maximum ratings

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Power Rail Name/ Schematic Name	Description	Min	Max	Unit
LP_DCDC	Micromodule Power	-0.300	4.0	V
DCDCIN	Micromodule Power	-0.300	6.0	V
GT_DCDC	Micromodule Power	-0.300	6.0	V
PL_DCIN	Micromodule Power	-0.300	3.6	V
PLL_3V3	PLL power supply	-0.500	3.8	V
PS_BATT	RTC / BBRAM	-0.500	2.000	V
VCCO_47	HD IO Bank power supply	-0.500	3.400	V
VCCO_48	HD IO Bank power supply	-0.500	3.400	V
VCCO_64	HP IO Bank power supply	-0.500	2.000	V
VCCO_65	HP IO Bank power supply	-0.500	2.000	V
VCCO_66	HP IO Bank power supply	-0.500	2.000	V
VREF_64	Bank input reference voltage	-0.500	2.000	V
VREF_65	Bank input reference voltage	-0.500	2.000	V
VREF_66	Bank input reference voltage	-0.500	2.000	V

^*) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

Recommended Operating Conditions

This TRM is generic for all variants. Temperature range can be differ depending on the assembly version. Voltage range is mostly the same during variants (exceptions are possible, depending on custom request)

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Variants of modules are described here: Article Number Information
Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C
Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C
The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.

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Parameter	Min	Max	Units	Reference Document
LP_DCDC ¹⁾	3.135	3.465	V
DCDCIN ¹⁾	3.135	3.465	V
GT_DCDC ¹⁾	3.135	3.465	V
PL_DCIN ¹⁾	3.135	3.465	V
PLL_3V3	3.14	3.465	V
PS_BATT	1.200	1.500	V	See FPGA datasheet.
VCCO_47	1.140	3.400	V	See FPGA datasheet.
VCCO_48	1.140	3.400	V	See FPGA datasheet.
VCCO_64	0.950	1.900	V	See FPGA datasheet.
VCCO_65	0.950	1.900	V	See FPGA datasheet.
VCCO_66	0.950	1.900	V	See FPGA datasheet.
VREF_64	0.6	1.2	V	See FPGA datasheet.
VREF_65	0.6	1.2	V	See FPGA datasheet.
VREF_66	0.6	1.2	V	See FPGA datasheet.

¹⁾ Higher values may possible. For more information consult schematic and according datasheets.

Physical Dimensions

Module size: 76 mm × 52 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 5 mm.

PCB thickness: 1.6 mm (± 10 %).

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Currently Offered Variants

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DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706

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Trenz shop TE0808 overview page
English page	German page

Revision History

Hardware Revision History

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2020-11-25 REV02
Resistors R14 and R15 was replaced by 953R (was 5K1)
Resistor R5 was replaced by 5K1, R8 by 953R (was 9K09 and 1K69 respectively)
REV02

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Date	Revision	Changes	Documentation Link
-	05	Second production silicon: revised PL_VCCINT power supply. PCB: revised routing and components placement; added signal BG1 for DDP DDR4 IC. Added support of new packages. PCB: revised routing and components placement; R5 pulled up to 1.2V. R5 value changed to 49.9R; added test points; added MAC EEPROM U48. I2C bus PLL_SCL/SDA. Added pull up resistor to I2C bus; PCB - revised FPGA location. Package placed 1.5mm closer to connector J3; PCB - updated silckscreen. Added company address, CE and WEEE symbols; PCB - updated signal trace lengths. (29.11.2022) Changed note near J2.97 and net PG_GT_L from "On board pull-up R" to "External pull-up R Required"	TE0808-05
-	04	First production silicon: Added resistors R65,R82,R86,R87 (240R) for each DDR4-chip for supporting DDP DDR4 chips Full library update (09.06.2020) R19 value was changed to 10K (was: 4K99) to set PS_MGTRAVCC 0.85V	TE0808-04
-	03	Second ES production release	TE0808-03
2016-03-09	02	First ES production release	TE0808-02
-	01	Prototypes	-

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Document Change History

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Description

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change default RAM size on key feature section
typo and revision history update

2024-09-18

v.48

John Hartfiel

Review and Public Update

2023-10-13

v.44

ED

Updated to new TRM style

2022-09-13

v.41

Vadim Yunitski

Updated PG_PL pull-up resistor requirements

2021-09-07

V.39

John Hartfiel

Correction Power section

2021-05-17

v.37

John Hartfiel

typo correction in DDR section

2021-03-11

v.35

Antti Lukats

typo correction in PLL_RST
add pin on power rails table
correction MGT Lane assignment
correction MGT CLK assignment

2019-01-27

v.30

Martin Rohrmüller

Corrected clock connection to J2

2018-11-20

v.29

John Hartfiel

Notes for power supply

2018-08-27

v.27

John Hartfiel

typo correction SI5345 I2C address

2028-06-28

v.26

John Hartfiel

typo SI5348 B2B IOs + link correction

2017-11-13

v.24

Ali Naseri

updated B2B connector max. current rating per pin

2017-11-13

v.22

John Hartfiel

rework B2B section

2017-10-20

v.21

Ali Naseri

Update links (pdf, documentation) to revision 4
ES silicon note removed

2017-08-28

v.15

John Hartfiel

Update section: Variants Currently In Production

2017-08-28

v.14

Jan Kumann

Block diagram changed.
SPI flash section fixed.
Few smaller improvements.

2017-08-15

v.12

Vitali Tsiukala

Changed signals count in the B2B connectors table

2017-08-15

v.11

John Hartfiel, Ali Naseri

PCB REV04 Initial release
update boot mode section

2017-02-06

v.1

Jan Kumann

Initial document

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Overview

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Refer to "https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/TE0808" for downloadable version of this manual and the rest of available documentation.

The Trenz Electronic TE0808 is an industrial-grade MPSoC UltraSoM integrating a Xilinx Zynq UltraScale+, max. 8 GByte DDR4 SDRAM with 64-Bit width databus connection, max. 512 MByte Flash memory for configuration and operation, 20 Gigabit transceivers, and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking connections.

Note
Current TE0808 boards are equipped with ES1 silicon. Erratas and functional restrictions may exist, please check Xilinx documentation and contact your local Xilinx FAE for restrictions.

Block Diagram

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Figure 1: TE0808-03 Block Diagram

Main Components

Image Removed Image Removed

Figure 2: TE0808-03 MPSoC module

Xilinx ZYNQ UltraScale+ XCZU9EG MPSoC, U1
Low-power programmable oscillator @ 33.333333 MHz (PS_CLK), U32
Red LED (DONE), D1
256Mx16 DDR4-2400 SDRAM, U12
256Mx16 DDR4-2400 SDRAM, U9
256Mx16 DDR4-2400 SDRAM, U2
256Mx16 DDR4-2400 SDRAM, U3
12A PowerSoC DCDC converter, U4
Quartz crystal, Y1
Low-power programmable oscillator @ 25.000000 MHz (IN0 for U5), U25
10-channel programmable clock generator, U5
Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J4
Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J2
Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J3
Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J1
Quartz crystal, Y2
256 Mbit serial NOR Flash memory, U7
256 Mbit serial NOR Flash memory, U17

Key Features

MPSoC: ZYNQ UltraScale+ ZU9EG 900 pin package
Memory
- 64-Bit DDR4, 8 GByte maximum
- Dual SPI boot Flash in parallel, 512 MByte maximum
User I/O
- 65 x MIO, 48 x HD (all), 156 x HP (3 banks)
- Serial transceiver: 4 x GTR + 16 x GTH
- Transceiver clocks inputs and outputs
- PLL clock generator inputs and outputs
Size: 52 x 76 mm, 3 mm mounting holes for skyline heat spreader
B2B connectors: 4 x 160 pin
Si5345 - 10 output PLL
All power supplies on board, single 3.3V power source required
- 14 on-board DCDC regulators and 13 LDOs
- LP, FP, PL separately controlled power domains
Support for all boot modes (except NAND) and scenarios
Support for any combination of PS connected peripherals

Initial Delivery State

...

Content

...

Notes

...

SPI Flash main array

...

Not programmed

...

eFUSE Security

...

Not programmed

...

Table 1: Initial Delivery State of the flash memories

Signals, Interfaces and Pins

Board to Board (B2B) connectors

The TE0808 MPSoC UltraSoM has four Board to Board (B2B) connectors with 160 contacts per connector.

Each connector has a specific arrangement of the signal-pins, which are grouped together in categories related to their functionalities and to their belonging to particular units of the Zynq Ultrascale+ MPSoC like I/O-banks, interfaces and Gigabit transceivers
or to the on-board peripheral ICs of the SoM.

Following table lists the I/O-bank signals, which are routed from the MPSoC's PL and PS banks as LVDS-pairs or single ended I/O's to the B2B connectors.

...

B47_L1_P ... B47_L12_P
B47_L1_N ... B47_L12_N

...

VCCO47
pins J3-43, J3-44

...

VCCO max. 3.3V
usable as single-ended I/O's

...

B48_L1_P ... B48_L12_P
B48_L1_N ... B48_L12_N

...

VCCO48
pins J3-15, J3-16

...

VCCO max. 3.3V
usable as single-ended I/O's

...

B64_L1_P ... B64_L24_P
B64_L1_N ... B64_L24_N

...

VCCO64
pins J4-58, J4-106

...

VCCO max. 1.8V
usable as single-ended I/O's

...

B65_L1_P ... B65_L24_P
B65_L1_N ... B65_L24_N

...

VCCO65
pins J4-69, J4-105

...

VCCO max. 1.8V
usable as single-ended I/O's

...

B_64_T0 ... B_64_T3
pins J4-8, J4-6, J4-4, J4-2

...

VCCO64
pins J4-58, J4-106

...

B_65_T0 ... B_65_T3
pins J4-7, J4-5, J4-3, J4-1

...

VCCO65
pins J4-69, J4-105

...

B66_L1_P ... B66_L24_P
B66_L1_N ... B66_L24_N

...

VCCO66
pins J1-90, J1-120

...

VCCO max. 1.8V
usable as single-ended I/O's

...

B_66_T0 ... B_66_T3
pins J1-147, J1-145, J1-143, J1-141

...

VCCO66
pins J1-90, J1-120

...

VCCO max. 1.8V
only single-ended I/O's

...

Table 2: B2B connector pin-outs of available PL and PS banks of the TE0808-03 SoM

For detailed information about the B2B pin-out, please refer to the Pin-out table.

MGT lanes

The B2B connector J1 and J2 provide also access to the MGT-banks of the Zynq Ultrascale+ MPSoC. There are 20 high-speed data lanes (Xilinx GTH / GTR transceiver) available composed as differential signaling pairs for both directions (RX/TX).

The MGT-banks have also clock input-pins which are exposed to the B2B connectors J2 and J3. Following MGT-lanes are available on the B2B connectors:

...

B228_RX3_P, B228_RX3_N, pins J1-27, J1-29
B228_TX3_P, B228_TX3_N, J1-26, J1-28

B228_RX2_P, B228_RX2_N, pins J1-33, J1-35
B228_TX2_P, B228_TX2_N, J1-32, J1-34

B228_RX1_P, B228_RX1_N, pins J1-39, J1-41
B228_TX1_P, B228_TX1_N, J1-38, J1-40

B228_RX0_P, B228_RX0_N, pins J1-45, J1-47
B228_TX0_P, B228_TX0_N, J1-44, J1-46

...

1 reference clock signal (B228_CLK0) from B2B connector
J3 (pins J3-60, J3-62) to bank's pins R8/R7

1 reference clock signal (B228_CLK1) from programmable
PLL clock generator U5 to bank's pins N8/N7

...

B229_RX3_P, B229_RX3_N, pins J1-27, J1-29
B229_TX3_P, B229_TX3_N, pins J1-26, J1-28

B229_RX2_P, B229_RX2_N, pins J1-33, J1-35
B229_TX2_P, B229_TX2_N, pins J1-32, J1-34

B229_RX1_P, B229_RX1_N, pins J1-39, J1-41
B229_TX1_P, B229_TX1_N, pins J1-38, J1-40

B229_RX0_P, B229_RX0_N, pins J1-45, J1-47
B229_TX0_P, B229_TX0_N, pins J1-44, J1-46

...

1 reference clock signal (B229_CLK0) from B2B connector
J3 (pins J3-65, J3-67) to bank's pins L8/L7

1 reference clock signal (B229_CLK1) from programmable
PLL clock generator U5 to bank's pins J8/J7

...

B230_RX3_P, B230_RX3_N, pins J1-3, J1-5
B230_TX3_P, B230_TX3_N, pins J1-2, J1-4

B230_RX2_P, B230_RX2_N, pins J1-9, J1-11
B230_TX2_P, B230_TX2_N, pins J1-8, J1-10

B230_RX1_P, B230_RX1_N, pins J1-15, J1-17
B230_TX1_P, B230_TX1_N, pins J1-14, J1-16

B230_RX0_P, B230_RX0_N, pins J1-21, J1-23
B230_TX0_P, B230_TX0_N, pins J1-20, J1-22

...

1 reference clock signal (B230_CLK1) from B2B connector
J3 (pins J3-59, J3-61) to bank's pins G8/G7

1 reference clock signal (B230_CLK0) from programmable
PLL clock generator U5 to bank's pins E8/E7

...

B128_RX3_N, B128_RX3_P, pins J2-28, J2-30
B128_TX3_N, B128_TX3_P, pins J2-25, J2-27

B128_RX2_N, B128_RX2_P, pins J2-34, J2-36
B128_TX2_N, B128_TX2_P, pins J2-31, J2-33

B128_RX1_N, B128_RX1_P, pins J2-40, J2-42
B128_TX1_N, B128_TX1_P, pins J2-37, J2-39

B128_RX0_N, B128_RX0_P, pins J2-46, J2-48
B128_TX0_N, B128_TX0_P, pins J2-43, J2-45

...

1 reference clock signal (B128_CLK1) from B2B connector
J2 (pins J2-22, J2-24) to bank's pins D25/D26

1 reference clock signal (B128_CLK0) from programmable
PLL clock generator U5 to bank's pins F25/F26

...

B505_RX3_N, B505_RX3_P, pins J2-52, J2-54
B505_TX3_N, B505_TX3_P, pins J2-49, J2-51

B505_RX2_N, B505_RX2_P, pins J2-58, J2-60
B505_TX2_N, B505_TX2_P, pins J2-55, J2-57

B505_RX1_N, B505_RX1_P, pins J2-64, J2-66
B505_TX1_N, B505_TX1_P, pins J2-61, J2-63

B505_RX0_N, B505_RX0_P, pins J2-70, J2-72
B505_TX0_N, B505_TX0_P, pins J2-67, J2-69

...

2 reference clock signals (B505_CLK0, B505_CLK1) from B2B connector
J2 (pins J2-10/J2-12, J2-16/J2-18) to bank's pins P25/P26, M25/M26

2 reference clock signal (B505_CLK2, B505_CLK3) from programmable
PLL clock generator U5 to bank's pins K25/K26, H25/H26

Table 3: B2B connector pin-outs of available MGT-lanes of the MPSoC

JTAG Interface

JTAG access is provided through the MPSoC's PS configuration bank 503 with bank voltage 'PS_1V8'.

...

Table 4: B2B connector pin-out of JTAG interface

Configuration bank control signals

The Xilinx Zynq Ultrascale+ MPSoC's PS configuration bank 503 control signal pins are accessible through B2B-connector J2.

...

4-bit boot mode pins

For further information about the boot-modes refer to the Xilinx Zynq Ultrascale+ TRM 'ug1085'.

...

ERR_OUT signal is asserted for accidental loss of
power, an error, or an exception in the MPSoC's Platform Management Unit (PMU)

ERR_STATUS indicates a secure lockdown state

...

Table 5: B2B connector pin-out of MPSoC's PS configuration bank

Analog Input

The Xilinx Zynq Ultrascale+ MPSoC provides input-pins for differential analog values. The pins are exposed to B2B-connector J2.

...

Table 6: B2B connector pin-out of analog input pins

Quad-SPI Flash memory

The TE0808-03 SoM is equipped with two Serial Flash Memory with up to 512 Mbyte storage capacity each. The flash memory ICs with the schematic designators U7 and U17 are connected to bank 500 (PSMIO) of the Zynq MPSoC module via QSPI interface, enabling a 8-Bit width databus connection.

Following table shows the mapping of the MIO-pins to the flash memory ICs.

...

Chip-select (low-active)

...

Chip-select (low-active)

...

Table 7: Flash memory QSPI-interface

DDR4 SDRAM

The TE0808-03 UltraSoM is equipped with with four DDR4-2400 SDRAM modules with up to 8 Gbyte memory density. The SDRAM modules are connected to the Zynq MPSoC's PS DDR-controller (bank 504) with a 64-bit databus width.

LEDs

TE0808 has one red LED (D1) which reflects MPSoC's 'DONE' signal. This LED goes ON when power has been applied to the module and stays ON until MPSoC's programmable logic is configured properly.

Clocking

Programmable Clock Generator

Following table illustrates on-board Si5345A programmable clock multiplier chip inputs and outputs:

...

Table 8: Programmable PLL clock generator input/output

The Si5345A programmable clock generator's control interface pins are exposed to B2B connector J2. For further information refer to the Si5345A data sheet.

...

Device Reset (low-active)

...

I²C interface, needed extern pull-ups.

I²C address in current configuration: 1101010b

Table 9: B2B connector pin-out of Si5345A programmable clock generator

The TE0808-03 SoM is equipped with two on-board oscillators to provide the Zynq's MPSoC's PS configuration bank 503 with reference clock-signals.

...

Table 10: Reference clock-signals to PS configuration bank 503

Power and Power-On Sequence

Power supply with minimum current capability of 3A for system startup is recommended. For the lowest power consumption and highest efficiency of on board DC/DC regulators it is recommended to powering the module from one single 3.3V supply. All input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

The TE0808-03 module with the Xilinx Zynq Ultrascale+ MPSoC delivers a heterogeneous multi-processing system with integrated programmable logic and independently operable elements and is designed to meet embedded system power management requirement by advanced power management features. This features allow to offset the power and heat constraints against overall performance and operational efficiency.

This features allowing highly flexible power management are achieved by establishing Power Domains for power isolation. The Zynq Ultrascale+ MPSoC has multiple power domains, whereby each power domain requires its particular extern DCDC converters.

The Processing System contains three Power Domains:

Battery Power Domain (BBRAM and RTC)
Full-Power Domain (Application Processing Unit, DDR Controller, Graphics Processing Unit and High-Speed Connectivity)
Low-Power Domain (Real-Time Processing Unit, Security and Configuration Unit, Platform Management Unit, System Monitor and General Connectivity)

The fourth Power Domain is for the Programmable Logic (PL). If individual Power Domain control is not required, power rails can be shared between domains.

On the TE0808-03 SoM, following Power Domains can be powered up individually with power rails available on the B2B connectors:

Full-Power Domain, supplied by power rail 'DCDCIN'
Low-Power Domain, supplied by power rail 'LP_DCDC'
Programmable Logic, supplied by power rail 'PL_DCIN'
Battery Power Domain, supplied by power rail 'PS_BATT'

Each Power Domain has its own "Enabling"- and "Power Good"-signal. The power rail 'GT_DCDC' is necessary for generating the supply voltages for the high speed Gigabit Transceivers units of the Zynq Ultrascale+ MPSoC.

Power-On Sequence utilizing DCDC control signals

To power up the TE0808-03 SoM properly, a specific sequence must be kept of enabling the on-board DCDC converters dedicated to the particular Power Domains and powering up the on-board voltages.

The first activated Power Domain is the Low-Power Domain. Therefore, the power rail 'LP_DCDC' have to be powered up and the Enable-signal 'EN_LPD' (pin J2-108, 7V max.) have to be asserted. The resulting Power-Good-Signal 'LP_GOOD' (pin J2-106) will go high after the voltages of the Low-Power Domain are properly powered up.

Image Removed

Figure 3: Low-Power Domain

The second activated Power Domain is the Programmable Logic. Therefore, the power rail 'PL_DCIN' have to be powered up and the Enable-signal 'EN_PL' (pin J2-101) have to be asserted by pulling this pin up to the voltage 'LP_DCDC' or left floating (drive to GND for disabling). The resulting Power-Good-Signal 'PG_PL' (pin J2-104) will go high after the voltages of the Programmable Logic Domain are properly powered up. The signal 'PG_PL' needs an extern pull-up (max. voltage 'GT_DCDC').

Image Removed

Figure 4: Programmable Logic Domain

Also as second activated Power Domain is the Full-Power Domain. Therefore, the power rail 'DCDCIN' have to be powered up and the Enable-signals 'EN_FPD' (pin J2-102) and 'EN_DDR' (J2-112) have to be asserted (max. voltage 'DCDCIN'). The resulting Power-Good-Signals 'PG_FPD' (pin J2-110) and 'PG_DDR' (J2-114) will go high after the voltages of the Full-Power Domain are properly powered up. In the following, the PSGT voltages (see figure 3) can be powered up by asserting the Enable-signal 'EN_PSGT' (pin J2-84, max. voltage 'DCDCIN'). The resulting Power-Good-Signal 'PG_PSGT' (pin J2-82) needs an extern pull-up (max. 6V).

Image Removed

Figure 5: Full-Power Domain

The supply voltages for the MGT units of the MPSoC will be powered up last. Therefore, the power rail 'GT_DCDC' have to be powered up and the Enable-signals 'EN_GT_R' (pin J2-95), 'EN_GT_L' (pin J2-79) and 'EN_PLL_PWR' (J2-77, 7V max.) have to be asserted (max. voltage 'GT_DCDC'). The resulting Power-Good-Signals 'PG_GT_R' (pin J2-91), 'PG_GT_L' (pin J2-97) and 'PG_PLL_1V8' (J2-80) will go high after the supply voltages of the MGT units are properly powered up. The three Power-Good-Signals need an extern pull-up (max. 6V).

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Figure 6: Powering up MGT supply voltages

The voltages 'LP_DCDC' and 'LP_0V85' are monitored by a the voltage monitor circuit U41, which generates the POR_B signal at Power-On. A manual reset is also possible the driving the MR-pin (J2-83) to GND. Leave this pin unconnected or connect to VDD (LP_DCDC) when unused.

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Figure 7: Voltage monitor circuit

Warning
To avoid any demages to the MPSoC module, check for stabilized on-board voltages in steady state before powering up the MPSoC's I/O bank voltages VCCOx.

Core voltages and main supply voltages have to reach stable state and their "Power Good"-signals have to be asserted before other voltages like bank's I/O voltages (VCCOx) can be powered up.

It is important that all PS and PL I/Os are 3-stated at power-on until the "Power Good"-signals are high, meaning that all on-module voltages have become stable and module is properly powered up.

See Xilinx datasheet DS925 for additional information. User should also check related base board documentation when intending base board design for TE0808-03 SoM.

Power Rails

...

Voltages on B2B
Connectors

...

Input/
Output

...

-

...

J2-154, J2-156, J2-158, J2-160,
J2-153, J2-155, J2-157, J2-159

...

Internal voltage level
1.8V nominal output

...

Internal voltage level
1.8V nominal output

...

Internal voltage level
1.2V nominal output

Table 15: Power rails of the MPSoC module on accessible connectors

Bank Voltages

...

Table 16: Range of MPSoC module's bank voltages

B2B connectors

...

Technical Specifications

Absolute Maximum Ratings

...

Parameter

...

Unit

...

Notes / Reference Document

...

Receiver (RXP/RXN) and transmitter
(TXP/TXN) absolute input voltage

...

Voltage on input pins of
NC7S08P5X 2-Input AND Gate

...

Voltage on input pins (nMR) of
TPS3106K33DBVR Voltage Monitor, U41

...

TPS3106 data sheet,
VDD = LP_DCDC

...

Storage temperature (ambient)

...

–40

...

125

...

°C

...

Recommended Operating Conditions

...

NC7S08P5X data sheet,
see schematic for VCC

...

Voltage on input pins (MR) of
TPS3106K33DBVR Voltage Monitor, U41

...

TPS3106 data sheet,
VDD = LP_DCDC

Note
Assembly variants for higher storage temperature range are available on request.

Physical Dimensions

Module size: 52 mm × 76 mm. Please download the assembly diagram for exact numbers
Mating height with standard connectors: 4mm
PCB thickness: 1.6mm
Highest part on PCB: approx. 3mm. Please download the step model for exact numbers

All dimensions are given in millimeters.

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Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

-40 ... 125 TPS82085SIL data sheet

The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Weight

17 g - Plain module

Revision History

Hardware Revision History

...

Notes

...

Hardware revision number is written on the PCB board together with the module model number separated by the dash.

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Document Change History

...

Revision

...

Disclaimer

...

Trenz Electronic Documentation

Page History

Versions Compared

Old Version 5

New Version Current

Key

Overview

Key Features

Block Diagram

Main Components

Initial Delivery State

Signals, Interfaces and Pins

Connectors

Test Points

On-board Peripherals

DDR4 SDRAM

Quad SPI Flash

EEPROM

Clock Generator

Oscillator

Configuration and System Control Signals

Power and Power-On Sequence

Power Rails

Recommended Power up Sequencing

Board to Board Connectors

Technical Specifications

Absolute Maximum Ratings *)

Recommended Operating Conditions

Physical Dimensions

Currently Offered Variants

Revision History

Hardware Revision History

Document Change History

Disclaimer

Table of contents

Overview

Block Diagram

Main Components

Key Features

Initial Delivery State

Signals, Interfaces and Pins

Board to Board (B2B) connectors

MGT lanes

JTAG Interface

Configuration bank control signals

Analog Input

Quad-SPI Flash memory

DDR4 SDRAM

LEDs

Clocking

Programmable Clock Generator

Power and Power-On Sequence

Power-On Sequence utilizing DCDC control signals

Power Rails

Bank Voltages

B2B connectors

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Physical Dimensions

Operating Temperature Ranges

Weight

Revision History

Hardware Revision History

Document Change History

Disclaimer

Absolute Maximum Ratings ^*)