Scroll Title | ||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||
TEG2000 mounted on the TE0703
|
This page showcases important details of the module-carrier combination TEG2000 + TE0703 and introduces the available script-based test designs shows how to get the board up and running.
Note that some connectors interfaces on the carrier board like ethernet via the RJ45 or USB via the USB Connector cannot easily be implemented in a design due to the missing PHY. For that application a carrier like TEB0707 TEB0707 with CRUVI adapters would be more appropriatea solution.
Hardware | Software |
---|---|
|
|
The module TEG2000 has Cologne Chip GateMate A1 FPGA onboard that allows you to create extensive digital hardware designs.
Most of the FPGA IOs are spread arround the carrier. The TEG2000 is assembled with a QSPI non-volatile Flash memory(128 Mbit) and plenty of IOs which enable great hardware expandability. For communication and configuration the carrier offers a JTAG/UART Interface.
Page properties | ||||
---|---|---|---|---|
| ||||
This Getting Started Guide shows how to set up the board, attach the jumpers, wire it up and connect it with the software. The TE0717 Test Board description goes into "how to use the provided reference design" and in here we touch the aspect of how to add your own IP to the design. This includes changing the Vivado Block Design, regenerating the bitstream and using the hardware export(.xsa file) in Vitis to develop software that runs on the MicroBlaze. |
. |
draw.io Diagram | ||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TEG2000 + TE0703 Hardware Blockdiagram
Basic IOs<->FPGA connections are as following, Table 1:
Component | Signal | FPGA Pin(Loc) | Function |
---|---|---|---|
Green LED D2(on module) | LED1 | IO_SB_B4 | custom LED |
Clock | CLK_FPGA | IO_SB_A8/CLK0 | singled ended 25MHz clock |
Reset | MR | IO_EB_B0 | low active reset signal from S1 |
Info |
---|
Information on IO routing and FPGA pin connections can be found in the schematics. |
Check the Jumper settings. Bank Voltages to 1.8V. Caution! 3.3V setting could destroy the module. The description of the DIP-switches on the carrier can be found here.
Image RemovedImage Added
Expand | ||
---|---|---|
| ||
|