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Note for Download Link of the Scroll ignore macro: |
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Table of Contents |
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Note: 'Key Features' description: Important components and connector or other Features of the module → please sort and indicate assembly options |
- 2x Non-isolated power connectors
- 2x RJ45 Transceivers
- 3x Board to Board (B2B) Connectors
- 2x XMOD JTAG/UART Adaptor
- 4x SMA Coaxial Connectors
- DIP Switch
- 3 x Samtec ASP-122953-01 160-pin stackable, compatible with TE078x
- 2 mm MC LB2-A Soldered Connector for power supply (12V input)
- 4 SMA connectors for MGT
- 2 x 12 pin headers for XMOD
- 1 x DIP switch for modules CPLD Access
- 2 x RJ45 Connector
- USB A Stacked Connector
- Equipped with two TE0790 XMOD FTDI JTAG adapters
- Voltage regulators
- Dimension: 115 x 115 mm
Block Block Diagram
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add drawIO object here.
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anchor | Figure_OV_BD |
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title | TExxxx TEBT0782 block diagram |
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draw.io Diagram |
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border | false |
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viewerToolbar | true |
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fitWindow | false |
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diagramDisplayName | |
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lbox | true |
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revision | 212 |
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diagramName | TEBT0782_OV_BD |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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diagramWidth | 641 |
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Main Components
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anchor | Figure_OV_MC |
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title | TExxxx TEBT0782 main components |
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draw.io Diagram |
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border | false |
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viewerToolbar | true |
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fitWindow | false |
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diagramDisplayName | |
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lbox | true |
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revision | 38 |
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diagramName | TEBT0782_OV_MC |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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diagramWidth | 641440 |
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- RJ45 Transceivers, J1-J2
- USB A Stacked, U7
- XMOD JTAG/UART BaseAdapter, J7
- JTAG CPLD Adapter -J8
- 2 Line Common Mode Choke, J10
- Non-isolated power jack (VIN), J9-J11
- DIP Switch, S1
- SMA Coxial Connectors (MGT_TX), J3-J4
- SMA Coxial Connectors (MGT_RX), J5-, J3...J6
- Board to Board ConnectorsConnector, JB1...JB3
- Board to Board Connector, JB3
- Board to Board Connector, JB2
Initial Delivery State
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Notes : Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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anchor | Table_OV_IDS |
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title | Initial delivery state of programmable devices on the module |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortEnabled | false |
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cellHighlighting | true |
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Storage device name | Content | Notes |
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- | - | - |
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Configuration Signals
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- Overview of Boot Mode, Reset, Enables.
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The general Reset is provided through button S1 on TE0790 XMOD J7.
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anchor | Table_OV_BPRST |
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title | Boot Reset process. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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MODE StateBoot ModeNotesXMOD_B | 135 |
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anchor | Table_OV_RST |
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title | Reset process. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Signal | B2B | I/O | Note |
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XMOD_B | JBC3-135 |
Signals, Interfaces and Pins
Signals, Interfaces and Pins
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Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator Designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
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Scroll Title |
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anchor | Table_SIP_B2B |
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title | General PL I/O to B2B connectors information |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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FPGA Bank | B2B Connector | Interface | Number of I/O |
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Signal CountVoltage Level | |
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JTAG access to the TExxxx SoM through B2B connector JMX.
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anchor | Table_SIP_JTG |
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title | JTAG pins connection |
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JTAG Signal
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B2B Connector
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MIO Pins
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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.
Example:
JB1
| RJ45, J1B-J1C | 1 Differential pair, 2 Single Ended | Yellow, Green LEDs | RJ45, J1A | 4 Differential pair, 8 Single Ended | PHY1 MDIO | RJ45, J2B-J2C | 1 Differential pair, 2 Single Ended | Yellow, Green LEDs | RJ45, J2A | 4 Differential pair, 8 Single Ended | PHY2 MDIO | TE0790 Base, J8 | 4 Single Ended |
| TE0790 Base, J7 | 1 Single Ended |
| USB A Stacked, U7 | 2 Single Ended | USB | Power Switch, U1 | 2 Single Ended |
| SMD Line Filter, L6 | 1 Differential pair, 2 Single Ended | USB1_D | SMD Line Filter, L7 | 1 Differential pair, 2 Single Ended | USB2_D | ESD protection diode, U5 | 1 Single Ended | USB1_VBUS | ESD protection diode, U8 | 1 Single Ended | USB2_VBUS | JB2
| Module TE078x FPGA, Bank 111-112 | 16 Differential pair, 32 Single Ended | MGT_RX8...15, MGT_TX8...15 | Module TE078x FPGA, Bank 34 | 1 Differential pair, 2 Single Ended | J1_B34_VRP, J1_B34_VRN | Module TE078x FPGA, Bank 34 | 1 Differential pair, 2 Single Ended | J1_B33_VRP, J1_B33_VRN | JB3
| TE0790 Base, J8 | 4 Single Ended | M_TCK, M_TMS, M_TDO, M_TDI | TE0790 Base, J7 | 4 Single Ended 2 Single Ended 1 Single Ended | TCK, TMS, TDO, TDI UART RX/TX RESIN | DIP Switch, S1-A | 1 Single Ended | JTAGENB | SMA Coaxial, J3...6 | 2 Differential pair, 4 Single Ended | MGT_RX0, MGT_TX0 | Module TE0782...4 FPGA, Bank 109-110 | 16 Differential pair, 32 Single Ended | MGT_RX1...7, MGT_TX0...7 |
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JTAG/UART to Module SoC/FPGA
JTAG access to the TE078x SoM is available through B2B connector JB3. JTAG access is provided by TE0790 XMOD Adapter on Pin Header J7.
Scroll Title |
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anchor | Table_SIP_JTG |
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title | JTAG pins connection |
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SPI_CS , SPI_DQ0... SPI_DQ3
SPI_SCK
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anchor | Table_OBP_MIOs |
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title | MIOs pins |
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
Scroll Title |
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anchor | Table_OBP |
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title | On board peripherals |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Chip/DesignatorSignal Name | B2B Connector | Notes |
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Quad SPI Flash Memory
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
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anchor | Table_OBP_SPI |
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title | Quad SPI interface MIOs and pins |
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A | XMOD_A | JB3C-129 | UART | B | XMOD_B | JB3C-135 | UART | C | TCK | JB3C-141 | JTAG | D | TDO | JB3C-148 | JTAG | E | CPLD_GPIO4 | JB1A-18 |
| F | TDI | JB3C-147 | JTAG | G | RESIN | JB3C-130 | General Reset | H | TMS | JB3C-142 | JTAG | 3.3V | 3.3V_M | JB1- JB3 |
| VIO | 3.3V_M | JB1- JB3 | 3.3V |
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JTAG/ GPIO to Module CPLD
JTAG access to the System Controller CPLD is provided through B2B connector J3. JTAG access to CPLD is provided by TE0790 XMOD Adapter on Pin Header J8.
Pin 'JTAGENB' must be set high, using DIP Switch S1-A in order to program the System Controller CPLD via JTAG interaface.
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Scroll Title |
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anchor | Table_OBP_RTC |
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title | I2C interface MIOs and pins |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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MIO Pin | Schematic | U? Pin | Notes |
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Scroll Title |
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anchor | Table_OBPSIP_I2C_RTCCPLDJTG |
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title | I2C Address for RTCCPLD JTAG pins connection |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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MIO Pin | I2C Address | Designator | Notes |
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anchor | Table_OBP_EEP |
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title | I2C EEPROM interface MIOs and pins |
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JTAG Interface Pins | Signal Name | B2B Connector | Notes |
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A | CPLD_GPIO0 | JB1A-10 |
| B | CPLD_GPIO1 | JB1A-12 |
| C | M_TCK | JB3B-81 |
| D | M_TDO | JB3B-88 |
| E | CPLD_GPIO2 | JB1A-14 |
| F | M_TDI | JB3B-87 |
| G | CPLD_GPIO3 | JB1A-16 |
| H | M_TMS | JB3B-82 |
| 3.3V | 3.3V_CPLD | JB1- JB3 |
| VIO | 3.3V_CPLD | JB1- JB3 | 3.3V |
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DIP Switch S2 on TE0790 must be set and fixed like the following table.
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anchor | Table_OBP_I2C_EEPROM |
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title | I2C address for EEPROM |
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LEDs
Scroll Title |
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anchor | Table_OBPSIP_JTG_LEDDIP |
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title | On-board LEDsXMOD DIP Switch Setting |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Schematic | Color | Connected to | Active Level | Note |
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DDR3 SDRAM
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.
- Part number:
- Supply voltage:
- Speed:
- NOR Flash
- Temperature:
Ethernet
DIP Switch | Setting | Notes |
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S2-1 | ON | JTAGENB (Enable/Disable module JTAG CPLD IOs) | S2-2 | OFF | NC | S2-3 | OFF | NC | S2-4 | OFF | NC |
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RJ45 Connectors
Scroll Title |
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anchor | Table_OBPSIP_ETHRJ45 |
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title | Ethernet PHY to Zynq SoC connectionsRJ45s Connections to B2B Connectors |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Bank | ETH1 | ETH2 | Signal Description | |
CAN Transceiver
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anchor | Table_OBP_CAN |
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title | CAN Tranciever interface MIOs |
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anchor | Table_OBP_CLK |
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title | Osillators |
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Power and Power-On Sequence
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:
- Power on-sequence
- Power distribution
- Voltage monitoring circuit
Note |
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For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" . |
Power Supply
Power supply with minimum current capability of xx A for system startup is recommended.
Power Consumption
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anchor | Table_PWR_PC |
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title | Power Consumption |
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* TBD - To Be Determined
Power Distribution Dependencies
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anchor | Figure_PWR_PD |
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title | Power Distribution |
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Scroll Ignore |
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Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
RJ45-J1 Pin | RJ45-J2 Pin | Notes |
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B2B |
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PHY_MDI0_P | JB1A-23 | JB1A-39 |
| PHY_MDI0_N | JB1A-21 | JB1A-37 |
| PHY_MDI1_P | JB1A-19 | JB1A-35 |
| PHY_MDI1_N | JB1A-17 | JB1A-33 |
| PHY_MDI2_P | JB1A-15 | JB1A-31 |
| PHY_MDI2_N | JB1A-13 | JB1A-29 |
| PHY_MDI3_P | JB1A-11 | JB1A-27 |
| PHY_MDI3_N | JB1A-9 | JB1A-25 |
| J2_TX9_P | JB1A-95 | - | LED Green/Yellow | J2_TX9_N | JB1A-97 | - | LED Green/Yellow | J2_RX9_N | - | JB1A-96 | LED Green/Yellow | J2_RX9_P | - | JB1A-98 | LED Green/Yellow |
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USB A Stacked Socket
The USB A Stacked (U7) is a dual port USB Socket which provides two USB ports.
Scroll Title |
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anchor | Table_SIP_USB |
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title | Dual Port USB Connections |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Signal Name | Port A | Port B | Notes |
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B2B | Connected to | B2B | Connected to |
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USB_D_P | JB1A-28 | SMD Line Filter, L7 | JB1A-40 | SMD Line Filter, L6 |
| USB_D_N | JB1A-26 | SMD Line Filter, L7 | JB1A-38 | SMD Line Filter, L6 |
| USB_VBUS | JB1A-24 | SMD Line Filter, L7 | JB1A-36 | SMD Line Filter, L6 |
| VBUS_V_EN | JB1A-30 | Power Switch, U1 | JB1A-32 | Power Switch, U1 |
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SMA Coaxial
The TEBT0782 carrier is equipped with 4x SMA Coaxial straight connectors.
Scroll Title |
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anchor | Table_SIP_SMA |
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title | SMAs Connections |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Designator | Schematic | B2B | Notes |
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J3 | MGT_TX0_N | JB3A-29 | Transfer | J4 | MGT_TX0_P | JB3A-31 | Transfer | J5 | MGT_RX0_N | JB3A-30 | Receive | J6 | MGT_RX0_P | JB3A-32 | Receive |
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Test Points
Power-On Sequence
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anchor | Figure_PWR_PS |
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title | Power Sequency |
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Scroll Ignore |
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Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
Voltage Monitor Circuit
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anchor | Figure_PWR_VMC |
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title | Voltage Monitor Circuit |
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Scroll Ignore |
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Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Scroll Title |
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anchor | Table_PWRSIP_PRTestPoint |
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title | Module power rails.Test Points Information |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Power Rail Name | B2B Connector JM1 PinJM2 Pin B2B Connector JM3 Pin | Direction | Notes | |
Bank Voltages
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anchor | Table_PWR_BV |
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title | Zynq SoC bank voltages. |
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Notes |
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TP 1 | VBAT_I | JB3-124 |
| TP 2 | OTG2_ID | JB1-22 |
| TP 3 | OTG1_ID | JB1-34 |
| TP 4 | USB1_VBUS | JB1-36 |
| TP 5 | USB2_VBUS | JB1-24 |
| TP 6 | M_TCK | JB3-81 |
| TP 7 | M_TDO | JB3-88 |
| TP 8 | M_TDI | JB3-87 |
| TP 9 | M_TMS | JB3-82 |
| TP 10 | TCK | JB3-141 |
| TP 11 | TDO | JB3-148 |
| TP 12 | TDI | JB3-147 |
| TP 13 | TMS | JB3-142 |
| TP 14 | VIN | JB1-165...168 |
| TP 15 | 5V | - |
| TP 16 | 3.3V_CPLD | JB1-147...148 |
| TP 17-18 | GND | - |
|
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On-board Peripherals
Page properties |
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|
Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
|
Page properties |
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|
Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
Scroll Title |
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anchor | Table_OBP |
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title | On board peripherals |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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|
DIP Switch
Scroll Title |
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anchor | Table_OBP_DIP |
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title | DIP Switch Connections |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Switch | Connected to | B2B | Notes |
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S1-A | JTABENB | JB3C-136 |
| S1-B...D | - | - | Not connected |
|
Power and Power-On Sequence
Page properties |
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|
In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
|
Power Supply
Power supply with minimum current capability of 3A for system startup is recommended.
Power Consumption
Scroll Title |
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anchor | Table_PWR_PC |
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title | Power Consumption |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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|
Power Input Pin | Typical Current |
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VIN | TBD* |
|
* TBD - To Be Determined
Power Distribution Dependencies
12V power supply (VIN) on J9/J11 (2 mm MC LB2-A solder-in) or on J10 (TE1.5/2-3.5H).
Scroll Title |
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anchor | Figure_PWR_PD |
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title | Power Distribution |
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Scroll Ignore |
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scroll-pdf | false |
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scroll-office | true |
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scroll-chm | true |
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scroll-docbook | true |
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scroll-eclipsehelp | true |
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scroll-epub | true |
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scroll-html | true |
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| draw.io Diagram |
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border | false |
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viewerToolbar | true |
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fitWindow | false |
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diagramDisplayName | |
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lbox | true |
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revision | 7 |
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diagramName | TEBT0784_PWR_PD |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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diagramWidth | 641 |
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Scroll Only |
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Image Added |
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Power-On Sequence
Scroll Title |
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anchor | Figure_PWR_PS |
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title | Power Sequency |
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Scroll Ignore |
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draw.io Diagram |
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border | false |
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viewerToolbar | true |
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fitWindow | false |
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diagramDisplayName | |
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lbox | true |
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revision | 9 |
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diagramName | TEBT0782_PWR_PS |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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diagramWidth | 641 |
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Scroll Only |
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Image Added |
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Power Rails
Scroll Title |
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anchor | Table_PWR_PR |
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title | Module power rails. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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|
Power Rail Name | B2B JB1 Pin | B2B JB2 Pin | B2B JB3 Pin | Direction | Notes |
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VIN | 165, 166, 167, 168 | - | - | Input/Output | Directly to module | 3.3V_M | 99, 100, 111,112, 123, 124, 135, 136, 159, 160, 169, 170, 171, 172 | - | 99, 100, 159, 160 | Input/Output | 160, 169, 170, 171, 172 are output other ones input for IO Banks | 3.3V_CPLD | 147,148 | - | - | Output | Directly to module | 1.8V_M | - | 99,100, 159, 160, 169, 170, 171, 172 | 124 | Input/Output | 169, 170, 171, 172 are output other ones input for IO Banks | VBAT_IN |
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Board to Board Connectors
Page properties |
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|
- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
Include Page |
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| PD:6 x 6 SoM LSHM B2B ConnectorsPD: |
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| 6 x 6 SoM LSHM B2B Connectors |
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|
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? x ? modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.
3 x REF-??????? (compatible to ????????), (?? pins, ?? per row)
Include Page |
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| 8.5 x 8.5 SoM QSH and QTH B2B Connectors |
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| 8.5 x 8.5 SoM QSH and QTH B2B Connectors |
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Technical Specifications
Absolute Maximum Ratings
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anchor | Table_TS_AMR |
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title | PS absolute maximum ratings |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Symbols | Description | Min | Max | Unit |
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V | V | V | V | V | V | V | V | | Note |
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VIN | Input supply voltage | -- | -- | V | Attention: Depends on connected module! 171050601 of the TEBT0782 (-0,3V - 40V) | T_STG | Storage Temperature | -40 | +85 | °C | DIP Switch S1 |
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Recommended Operating Conditions
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anchor | Table_TS_ROC |
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title | Recommended operating conditions. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Parameter | Min | Max | Units | Reference Document |
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V | See ???? datasheets. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | °C | See Xilinx ???? datasheet. | |
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VIN | 11.4 | 12.6 | V | Attention: Depends on connected module! See TE078x TRMs, recommended normally 12V Without module: 171050601 of the TEBT0782 (6V - 36V) | T_OPT | -40 | +85 | °C |
°C | See Xilinx ???? datasheet.
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Physical Dimensions
Module size: 116 mm × 116 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: ? 5 mm.
PCB thickness: ?? 1.6 mm.
Page properties |
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In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM. For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below: https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF
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Scroll Title |
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anchor | Figure_TS_PD |
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title | Physical Dimension |
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Scroll Ignore |
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draw.io Diagram |
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border | false |
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viewerToolbar | true |
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fitWindow | false |
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diagramDisplayName | |
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lbox | true |
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revision | 1 |
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diagramName | TEBT0782_TS_PD |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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diagramWidth | 641 |
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Scroll Only |
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scroll-pdf | true |
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scroll-office | true |
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scroll-chm | true |
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scroll-docbook | true |
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scroll-eclipsehelp | true |
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scroll-epub | true |
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scroll-html | true |
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| Image Modified |
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Currently Offered Variants
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anchor | Table_VCP_SO |
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title | Trenz Electronic Shop Overview |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Revision History
Hardware Revision History
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anchor | Table_RH_HRH |
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title | Hardware Revision History |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Date | Revision | Changes | Documentation Link |
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2016-11-05 | 01 | Initial Release | REV01 |
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
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anchor | Figure_RV_HRN |
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title | Board hardware revision number. |
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draw.io Diagram |
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border | false |
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viewerToolbar | true |
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fitWindow | false |
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diagramDisplayName | |
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lbox | true |
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revision | 14 |
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diagramName | TEBT0782_RH_HRN |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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diagramWidth | 145203 |
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Scroll Only |
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Document Change History
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anchor | Table_RH_DCH |
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title | Document change history. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Date | Revision | Contributor | Description |
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Page info |
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infoType | Modified date |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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| Page info |
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infoType | Current version |
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prefix | v. |
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type | Flat |
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showVersions | false |
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| Page info |
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infoType | Modified by |
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type | Flat |
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showVersions | false |
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change list | | 2019-10-8 | v.45 | John Hartfiel | update power section - XMOD section
| 2019-10-16 | v.44 | Pedram Babakhani | | -- | all | Page info |
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infoType | Modified users |
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type | Flat |
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showVersions | false |
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