Page History
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| Port Name | IO | Description |
|---|---|---|
| RGPIO_M_OUT | out | 23bit data output to slave device* |
| RGPIO_M_IN | in | 23bit data input from slave device* |
| RGPIO_M_RESERVED_OUT | out | 4bit reserved for future usage |
| RGPIO_M_RESERVED_IN | in | 4bit reserved for future usage |
| RGPIO_M_SLAVE_ACTIVATION_CODE | out | 4bit activation code from external slave for information only |
| RGPIO_M_ENABLE | in | Enable RGPIO communication. High active. Set RGPIO data as valid for Slave. Data will always transmitted, if CLK is available. |
| RGPIO_M_USRCLK | in | RGPIO transmission CLK for master and slave |
| RGPIO_M_RESET_N | in | RGPIO Reset. Low active. |
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| Port Name | IO | Description |
|---|---|---|
| RGPIO_S_OUT | out | 23bit data output to master device* |
| RGPIO_S_IN | in | 23bit data input from master device* |
| RGPIO_S_RESERVED_OUT | out | 4bit reserved for future usage |
| RGPIO_S_RESERVED_IN | in | 4bit reserved for future usage |
| RGPIO_S_MASTER_ACTIVATION_CODE | out | 4bit activation code from external master for information only |
| RGPIO_S_ENABLED | out | Interface status. Indicates RGPIO data are valid. |
*currently limited to 23 bit to use IP with CPLD implementations of TE Boards. For general usage, this restriction will be removed on future IP update.
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Document Change History
| Date | Document Revision | IP Revision | Authors | Description | ||||||||||||||||||||||
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| v1.0 |
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