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Template Revision 2.6
- Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM" - Carrier: TRM Name usually "TEB Series Name" +TRM
Example: "TEB0728 TRM"
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Important General Note:
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Note for Download Link of the Scroll ignore macro: |
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Table of Contents |
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The Trenz Electronic TEI0015 is an a commercial-grade, low cost and small size module integrated with Intel® MAX 10. Intel MAX 10 devices are the ideal solution for system management, I/O expansion, communication control planes, industrial, automotive, and consumer applications.
Refer to http://trenz.org/tei0015-info for the current online version of this manual and other available documentation.
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Intel® MAX 10 Commercial [10M08SAU169C8G]
SDRAM Memory up to
64Mb, 166MHz32 Mbyte (8Mbyte default)
USB 2.0
Dual High Speed USB to Multipurpose UART/FIFO IC
- Quad SPI Flash, 64Mb
- EEPROM Memory, 4Kb
8x User LED
USB port
(FT2232H)
- 4 Kbit EEPROM Memory for FTDI configuration data
- Micro USB Receptacle (communication and power)
SPI Flash - NOT INSTALLED (only special option)
- 8x User LED
- 18 Bit 2MSPS 18 Bit Analog to Digital Converter
2x SMA Female Connector
I/O interface: 23x GPIO - Arduino MKR compatible
Power Supply:
5V
Others:Dimension: 86.5mm x 25mm
Others:
Differential Amplifier
Operational Amplifier
Block Diagram
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add drawIO object here.
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| Scroll Title |
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| anchor | Figure_OV_BD |
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| title | TEI0015 block diagram |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| fitWindow | false |
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| diagramDisplayName |
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| lbox | true |
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revision | 17 | | diagramName | TEI0015_OV_BD |
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| simpleViewer | false |
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width | | links | auto |
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| tbstyle | hidden |
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| lbox | true |
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641
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Main Components
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| Scroll Title |
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| anchor | Figure_OV_BD |
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| title | TEI0015 main components |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| fitWindow | false | diagramDisplayName | lbox | true |
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| revision | 6 |
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| diagramName | TEI0015_OV_MC |
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| simpleViewer | false |
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| width | links | auto |
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| tbstyle | hidden |
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| lbox | true |
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| diagramWidth | 641 |
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| revision | 14 |
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SMA Connector, J5...6
- Instrumentation
Amplifier, U12 - U14 - U6
- Series
Voltage Reference, U8
Analog to Digital
ConvertorConverter, U15
- U6Voltage Regulator, U10 - U13 - U16
- Buck
Switching Voltage Regulator/LDO, U11 - U4
SDRAM Memory, U2
- Intel® MAX 10 FPGA, U1SDRAM Memory, U2
SPI Flash Memory, U5
12.00 MHz MEMS oscillator, U7
FTDI USB2 to JTAG/UART adapter
USP to UART convertor, U3
User LEDs, D2...9
- 4Kb
FTDI configuration EEPROM, U9
Configuration/Status LED (Red) , D10
Power-on LED (Green), D1
Push button
Switch, S1...2
Micro USB
portConnector, J9
- Pin Holder
1x14 pin header, J2 (Not assembled)
, J1...4 1x6 pin header, J4 (Not assembled)
1x4 Header, J3 (Not assembled)
1x14 pin header, J1 (Not assembled)
Initial Delivery State
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Notes : Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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| Scroll Title |
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| anchor | Table_OV_IDS |
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| title | Initial delivery state of programmable devices on the module |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default | style | widths |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Storage device name | Content | Notes |
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Quad SPI Flash | N/A | Not Programmedpopulated | | I2C Configuration EEPROM | Programmed | SDRAM | Not ProgrammedFTDI configuration |
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Configuration Signals
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- Overview of Boot Mode, Reset, Enables.
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The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface either in external configuration device (QSPI flash memory U5) or (using a *.POF file) on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile configuration memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up. To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile (using a *.SOF file), means the configuration is lost after power off.
Reset process must be done FPGA Reconfigration can be triggered by pressing push button S1.
| Scroll Title |
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| anchor | Table_OV_RST |
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| title | Reset process. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default | style | widths |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Signal | Push Button | Pin Header | Note |
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RESET | S1 | J2 | connected Connected to nCONFIG |
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Signals, Interfaces and Pins
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| Scroll Title |
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| anchor | Table_SIP_GIOs |
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| title | General I/Os to Pin Headers and connectors information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default | style | widths |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| FPGA Bank | Connector Designator | I/O Signal Count | Voltage Level | Notes |
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| Bank 1A | J1 | 7 | 3.3V | AIN0...6 | | Bank 1B | J4 | 5 | 3.3V | JTAG interface | | Bank 2 | J1 | 4 | 3.3V | DIO2...5 | | Bank 5 | J2 | 9 | 3.3V | DIO6...14 | | J1 | 2 | 3.3V | DIO0...1 | | Bank 8 | J2 | 1 | 3.3V | RESET |
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| Scroll Title |
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| anchor | Table_OBP_IOs |
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| title | FPGA I/O Banks |
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| | Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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style | widths |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| FPGA Bank | I/O Signal Count | Connected to | Notes |
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| Bank 1A | 7 | 1x14 Pin header, J1 | AIN0...6 |
| 1 | Jumper, J3 | AIN7 |
| Bank 1B | 5 | 1x6 Pin header, J4 | JTAG_EN, TDI, TDO, TMS, TCK |
Bank 2
| 4 | 1x14 Pin header, J1 | D2...5 |
| 5 | A2D, U15 | ADC_EN, ADC_SDI, ADC_SDO, ADC_SCK, ADC_CNV |
| 1 | 12MHz Oscillator, U7 | CLK12M |
| 2 | Amplifier, U12 | nIAMP_A0, nIAMP_A1 |
| Bank 3 | 22 | SDRAM, U2 | RAM_ADDR_CMD |
| Bank 5 | 9 | 1x14 Pin header, J2 | DIO6...14 |
| 2 | 1x14 Pin header, J1 | DIO0...1 |
| 1 | D12_R | DIO12 |
| Bank 6 | 16 | SDRAM, U2 | DQ0...15 |
| 2 | SDRAM, U2 | DQM0...1 |
| 1 | D11_R | DIO11 |
Bank 8
| 8 | User Red LEDs, D2...9 | LED0...7 |
| 6 | SPI Flash, U5 | F_CS, F_ |
CK| CKL, F_DI, F_DO, nSTATUS, DEVCLRn |
| 1 | Red LED, D10 | CONF_DONE |
| 6 | FTDI JTAG/UART Adapter, U3 | BDBUS0...5 |
| 1 | Push Button, S2 | USER_BTN |
JTAG Interface
JTAG access to the TEI0015 SoM through pin header connector J4.
Micro-USB Connector
The Micro-USB connector J9 provides an interface to access the FIFO/UART and JTAG functions via FTDI FT2232 chip. The use of this feature requires that FTDI USB drivers are installed on your host PC.
| Scroll Title |
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| anchor | Table_SIPOBP_JTGUSB |
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| title | JTAG Micro USB-2 connector pins connection |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default | style |
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| widths | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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JTAG Signal | Pin Header ConnectorTMS | J4-6 | TDI | J4-5 | TDO | J4-4 | TCK | J4-3 | JTAG_EN | J4-2 | |
On-board Peripherals
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
| VBUS | USB_VBUS |
| | D+ | FTDI FT2232H U3, DP pin |
| | D- | FTDI FT2232H U3, DM pin |
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JTAG Interface
JTAG access to the TEI0015 SoM through pin header connector J4. This is normally not needed as there is on-board USB JTAG functionality.
| Scroll Title |
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| anchor | Table_SIP_JTG |
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| title | JTAG pins connection |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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JTAG Signal | Pin Header Connector | Note |
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| TMS | J4-6 |
| | TDI | J4-5 |
| | TDO | J4-4 |
| | TCK | J4-3 |
| | JTAG_EN | J4-2 | Pulled-up to 3.3V |
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On-board Peripherals
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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| Page properties |
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
| Scroll Title |
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| anchor | Table_OBP |
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| title | On board peripherals |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Scroll Title |
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| anchor | Table_OBP |
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| title | On board peripherals |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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style | widths | | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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SDRAM
TEI0015 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.
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| Scroll Title |
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| anchor | Table_OBP_SDRAM |
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| title | SDRAM interface IOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default | style |
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| widths | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| SDRAM I/O Signals | Signal Schematic Name | Connected to | Notes |
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| Address inputs | A0 ... A13 | bank 3 | - | | Bank address inputs | BA0 / BA1 | bank 3 | - | | Data input/output | DQ0 ... DQ15 | bank 6 | - | | Data mask | DQM0 ... DQM1 | bank 6 | - | | Clock | CLK | bank 3 | - | | Control Signals | CS | bank 3 | Chip select | CKE | bank 3 | Clock enable | RAS | bank 3 | Row Address Strobe | CAS | bank 3 | Column Address Strobe | | WE | bank 3 | Write Enable |
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FTDI FT2232H
The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity features of the FT2232H chip.
FTDI FT2232H chip channel A is used in MPPSE mode for JTAG, 6 I/O's of . Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfacesis configured to be used in async FIFO mode, this is default mode when using preprogrammed FTDI configuration. In this mode the communication from host PC looks like normal UART but from the FTDI side it is 8 bit FIFO style interface.
The configuration of FTDI FT2232H chip is pre-programmed on in the EEPROM U9.
| Scroll Title |
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| anchor | Table_OBP_FTDI |
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| title | FTDI chip interfaces and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default | style |
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| widths | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| FTDI Chip U3 Pin | Signal Schematic Name | Connected to | Notes |
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| ADBUS0 | TCK | FPGA bank 1B, pin G2 | JTAG interface | | ADBUS1 | TDI | FPGA bank 1B, pin F5 | | ADBUS2 | TDO | FPGA bank 1B, pin F6 | | ADBUS3 | TMS | FPGA bank 1B, pin G1 | | BDBUS0 | BDBUS0 | FPGA bank 8, pin A4 | user User configurable | | BDBUS1 | BDBUS1 | FPGA bank 8, pin B4 | user User configurable | | BDBUS2 | BDBUS2 | FPGA bank 8, pin B5 | user User configurable | | BDBUS3 | BDBUS3 | FPGA bank 8, pin A6 | user User configurable | | BDBUS4 | BDBUS4 | FPGA bank 8, pin B6 | user User configurable | | BDBUS5 | BDBUS5 | FPGA bank 8, pin A7 | user User configurable |
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SPI Flash Memory
On-board serial configuration memory (U5) is provided by Winbond with 64 MBit (8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 8 via SPI interface.
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| anchor | Table_OBP_QSPI |
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| title | Quad SPI Flash memory interface |
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FPGA bank 8, pin C4
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| BDBUS6 | BDBUS6 | FPGA bank 6, pin C11 |
| | BDBUS7 | BDBUS7 | FPGA bank 3, pin J7 |
| | BCBUS0 | BCBUS0 | FPGA bank 5, pin J9 |
| | BCBUS1 | BCBUS1 | FPGA bank 3, pin K5 |
| | BCBUS2 | BCBUS2 | FPGA bank 3, pin L4 |
| | BCBUS3 | BCBUS3 | FPGA bank 3, pin L5 |
| | BCBUS4 | BCBUS4 | FPGA bank 3, pin N12 |
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SPI Flash
Optional SPI flash device maybe assembled in custom variants, normally it is not populated.
| Scroll Title |
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| anchor | Table_OBP_QSPI |
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| title | Quad SPI Flash memory interface |
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EEPROM
The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.
| Scroll Title |
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| anchor | Table_OBP_EEP |
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| title | I2C EEPROM interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default | style | widths |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Signal Schematic Name | Connected to | Notes | EECS | FTDI U3, Pin EECS | EECLK | FTDI U3, Pin EECLK | EEDATA | FTDI U3, Pin EEDATA |
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A2D Convertor
The TEI0010 board is equipped with the Analog Devices AD4003BCPZ, 18-bit A2D converter (ADC).
| F_CS | FPGA bank 8, pin B3 | Chip select | | F_CLK | FPGA bank 8, pin A3 | Clock | | F_DI | FPGA bank 8, pin A2 | Data in / out | | nSTATUS | FPGA bank 8, pin C4 | Data in / out, configuration dual-purpose pin of FPGA | | DEVCLRN | FPGA bank 8, pin B9 | Data in / out, configuration dual-purpose pin of FPGA | | F_DO | FPGA bank 8, pin B2 | Data in / out |
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EEPROM
The configuration of FTDI FT2232H chip is pre-programmed in the EEPROM U9.
| Scroll Title |
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| anchor | Table_OBP_EEP |
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| title | I2C EEPROM interface MIOs |
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| Scroll Title |
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| anchor | Table_OBP_A2D |
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| title | A2D converter interface and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default | style | widths |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| PinsSchematic | Connected to | Notes | IN+ | Diff Amplifier U14, VOUT- | IN- | Diff Amplifier U14, VOUT+ | SDI | Bank 2, ADC_SDI | SDO | Bank 2, ADC_SDO | SCK | Bank 2, ADC_SCK | CNV | Bank 2, ADC_CNV |
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LEDs
EECS | FTDI U3, Pin EECS |
| | EECLK | FTDI U3, Pin EECLK |
| | EEDATA | FTDI U3, Pin EEDATA |
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ADC
The TEI0015 board is equipped with the Analog Devices AD4003BCPZ-RL7 18-bit 2MSPS ADC.
| Scroll Title |
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| anchor | Table_OBP_LEDA2D |
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| title | On-board LEDsA2D converter interface and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default | style |
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| widths | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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|
Designator| Color | Active LevelNote | | D2...9 | Red | LED1...8 | Active High | User LEDs | | D10 | Red | CONF_DONE | Active Low | Configuration DONE LED | | D1 | Green | 3.3V Power Rail | Active High | After power on it will be on | |
Micro-USB2 Connector
The Micro-USB2 connector J9 provides an interface to access the UART and JTAG functions via FTDI FT2232 chip. The use of this feature requires that USB driver is installed on your host PC.
IN+ | Diff Amplifier U14, VOUT- |
| | IN- | Diff Amplifier U14, VOUT+ |
| | SDI | FPGA, bank 2, pin M2, ADC_SDI |
| | SDO | FPGA, bank 2, pin M1, ADC_SDO |
| | SCK | FPGA, bank 2, pin N3, ADC_SCK |
| | CNV | FPGA, bank 2, pin N2, ADC_CNV |
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LEDs
| Scroll Title |
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| anchor | Table_OBP_USBLED |
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| title | Micro USB-2 connector pinsOn-board LEDs |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default | style | widths |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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|
Pins | Connected to | Active Level | Note |
|---|
| VBUS | USB_VBUS | It is connected to GND | D+ | FTDI U3, DP pin | D- | FTDI U3, DM pin | |
Clock Sources
| D2...9 | Red | LED1...8 | Active High | User LEDs | | D10 | Red | CONF_DONE | Active Low | Configuration DONE LED | | D1 | Green | 3.3V | Active High | After power on it will be on. |
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Push Bottuns
| Scroll Title |
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| anchor | Table_OBP_LED |
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| title | On-board Push Buttons |
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| Scroll Title |
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| anchor | Table_OBP_CLK |
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| title | Osillators |
|---|
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| Scroll Table Layout |
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| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default | style |
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| widths | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
|---|
|
|
| Clock Source | Schematic Name | Frequency | Note |
|---|
| Microchip MEMS Oscillator, U7 | CLK12M | 12.00 MHz | Connected to FTDI FT2232 U3, pin 3 Connected to FPGA SoC bank 2, pin H6 |
Power and Power-On Sequence
...
In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:
- Power on-sequence
- Power distribution
- Voltage monitoring circuit
| Note |
|---|
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" . |
| Designator | Connected to | Functionality | Note |
|---|
| S1 | RESET | General reset |
| | S2 | USER_BTN | User push button | Connected to FPGA Bank 8. |
|
Clock Sources
Power Supply
To power-up the module, power supply with minimum current capability of 1A is recommended.
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| Scroll Title |
|---|
| anchor | Table_PWR_PC |
|---|
| title | Power Consumption |
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| | Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
style | widths | | sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
| FPGA | Typical Current |
|---|
| Intel MAX 10 10M08 FPGA SoC | TBD* |
* TBD - To Be Determined
Actual power consumption depends on the FPGA design and ambient temperature.
...
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Clock Source | Schematic Name | Frequency | Note |
|---|
| MEMS Oscillator, U7 | CLK12M | 12.00 MHz | Connected to FTDI FT2232 U3, pin 3. Connected to FPGA SoC bank 2, pin H6. |
|
Power and Power-On Sequence
| Page properties |
|---|
|
In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
|
Power Supply
The module is power supplied from USB (optionally via unpopulated pin header).
Power Consumption
| Scroll Title |
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| anchor | FigureTable_PWR_PDPC |
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| title | Power Distribution |
|---|
| | Scroll Ignore |
|---|
| draw.io Diagram |
|---|
| border | false |
|---|
| viewerToolbar | true |
|---|
| fitWindow | false |
|---|
| diagramDisplayName | TEI0015_PWR_P |
|---|
| lbox | true |
|---|
| revision | 8 |
|---|
| diagramName | TEI0015_PWR_PD |
|---|
| simpleViewer | false |
|---|
width | | links | auto |
|---|
| tbstyle | hidden |
|---|
| diagramWidth | 638 |
|---|
| Scroll Only |
|---|
 Image Removed
|
Power-On Sequence
...
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| FPGA | Typical Current |
|---|
| Intel MAX 10 10M08 FPGA | TBD* |
|
* TBD - To Be Determined
Actual power consumption depends on the FPGA design and ambient temperature.
Power Distribution Dependencies
| Scroll Title |
|---|
| anchor | Figure_PWR_PSPD |
|---|
| title | Power SequencyDistribution |
|---|
|
| Scroll Ignore |
|---|
| draw.io Diagram |
|---|
| border | false |
|---|
| viewerToolbar | true |
|---|
| fitWindow | false | diagramDisplayName |
|---|
| lbox | true |
|---|
| revision | 7 |
|---|
| diagramName | TEI0015_PWR_PSPD |
|---|
| simpleViewer | false | width |
|---|
| links | auto |
|---|
| tbstyle | hidden |
|---|
| diagramWidth | 641 |
|---|
|
| | Scroll Only |
|---|
 Image Removed | | diagramDisplayName | TEI0015_PWR_P |
|---|
| lbox | true |
|---|
| diagramWidth | 638 |
|---|
| revision | 12 |
|---|
|
|
| Scroll Only |
|---|
Image Added |
|
Power-On Sequence
There is no specific or special power-on sequence, just one single power source is needed. After power on the green LED (D1) will be on.
Power Rails
| Scroll Title |
|---|
| anchor | Table_PWR_PR |
|---|
| title | Module power rails. |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default | style | widths |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Power Rail Name | Connector J2 Pin | Connector J9 Pin |
|---|
Connector Designator | VCC / VCCIO Schematic Name | VoltageVIN5V | Input| Input | 5 V - Pin Header | | 3.3V |
3.3V5VJ95V | Input | | - | J9-1 | Input | 5 V - USB Connector |
|
Bank Voltages
| Scroll Title |
|---|
| anchor | Table_PWR_BV |
|---|
| title | Zynq Intel MAX 10 SoC bank voltages. |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default | style | widths |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Schematic Name | | Notes |
|---|
| Bank 1A | VCCIO1A | 3.3V |
| | Bank 1B | VCCIO1B | 3.3V |
| | Bank 2 | VCCIO2 | 3.3V |
| | Bank 3 | VCCIO3 | 3.3V |
| | Bank 5 | VCCIO5 | 3.3V |
| | Bank 6 | VCCIO6 | 3.3V |
| | Bank 8 | VCCIO8 | 3.3V |
|
|
...
| Scroll Title |
|---|
| anchor | Table_TS_AMR |
|---|
| title | PS absolute Absolute maximum ratings |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default | style |
|---|
| widths | sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Symbols | Description | Min | Max | Unit | Reference Document |
|---|
VIN supply voltage (5.0V nominal)VIN | Supply voltage | 4.75 | 5.25 | V |
| I/O Input voltage for FPGA I/O bank | -0.5 | 4.12 | V | Intel MAX 10 datasheet | | Voltage on ADC IC U15 pins | -5.0 | 5.0 | V | AD4003BCPZ datasheet | | Analog reference voltage on IC U15 | 5.0 | 5.0 | V | AD4003BCPZ datasheet | Storage Temperature | -40
| | CH1-, CH1+ | Analog input voltage on amplifier U12 pin 1, 10 | -30 | 30 | V | AD8251 datasheet | T_STG | Storage Temperature | -25 | +85 | °C |
|
|
Recommended Operating Conditions
...
| Scroll Title |
|---|
| anchor | Table_TS_ROC |
|---|
| title | Recommended operating conditions. |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default | style | widths |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Symbols | Min | Max | Unit | Reference Document |
|---|
VIN supply voltage |
(5.0V nominal)4.75 | 5.25 | V | | I/O Input voltage for FPGA I/O bank | -0.5 | 4.12 | V | Intel MAX 10 datasheet | | Voltage on ADC IC U15 pins | -0.1 | 5.1 | V | AD4003BCPZ datasheet | | Analog reference voltage on IC U15 | 5.0 | 5.0 | V | AD4003BCPZ datasheet | Storage Temperature(5.0V nominal) | 4.75 | 5.25 | V |
| | Analog input voltage on amplifier U12 pin 1 (CH1-), 10 (CH1+) | -10 | 10 | V | AD8251 datasheet | T_OP | 0 | +70 | °C | W9864G6JT-6 datasheet |
|
Physical Dimensions
Module size: 25 mm × 86.5 mm × 25 mm. Please download the assembly diagram for exact numbers.
PCB thickness: 1.65 22 mm.
| Page properties |
|---|
|
In 'Physical Dimension' section, top and button view of moduloe must be insterted, information regarding physical dimention can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part)for every SoM. For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below: https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF
|
...
| Scroll Title |
|---|
| anchor | Figure_TS_PD |
|---|
| title | Physical Dimension |
|---|
|
| Scroll Ignore |
|---|
| draw.io Diagram |
|---|
| border | false |
|---|
| viewerToolbar | true |
|---|
| fitWindow | false | diagramDisplayName |
|---|
| lbox | true |
|---|
| false | revision | 1 |
|---|
| diagramName | TEI0015_TS_PD |
|---|
| simpleViewer | false | width |
|---|
| links | auto |
|---|
| tbstyle | hidden |
|---|
| lbox | true |
|---|
| diagramWidth | 641 |
|---|
| revision | 1 |
|---|
|
|
| Scroll Only |
|---|
| scroll-pdf | true |
|---|
| scroll-office | true |
|---|
| scroll-chm | true |
|---|
| scroll-docbook | true |
|---|
| scroll-eclipsehelp | true |
|---|
| scroll-epub | true |
|---|
| scroll-html | true |
|---|
| 
|
|
...
| Scroll Title |
|---|
| anchor | Table_VCP_SO |
|---|
| title | Trenz Electronic Shop Overview |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
|
Revision History
Hardware Revision History
| Scroll Title |
|---|
| anchor | Table_VCPRH_SOHRH |
|---|
| title | Trenz Electronic Shop Overview Hardware Revision History |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default | style | widths |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
|
| Trenz shop TE0728 overview page |
|---|
| English page | German page |
Revision History
Hardware Revision History
List of online PCN ...Link
| | sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Date | Revision | Changes | Documentation Link |
|---|
| 2019-02-11 | 01 | - | REV01 |
|
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
| Scroll Title |
|---|
| anchor | Figure_RV_HRN |
|---|
| title | Board hardware revision number. |
|---|
|
| Scroll Ignore |
|---|
| draw.io Diagram |
|---|
| border | false |
|---|
| viewerToolbar | true |
|---|
| fitWindow | false |
|---|
| diagramName | TEI0015_RH_RHN |
|---|
| simpleViewer | false |
|---|
| links | auto |
|---|
| tbstyle | hidden |
|---|
| lbox | true |
|---|
| diagramWidth | 158 |
|---|
| revision | 2 |
|---|
|
|
| Scroll Only |
|---|
| scroll-pdf | true |
|---|
| scroll-office | true |
|---|
| scroll-chm | true |
|---|
| scroll-docbook | true |
|---|
| scroll-eclipsehelp | true |
|---|
| scroll-epub | true |
|---|
| scroll-html | true |
|---|
|  Image Added
|
|
| Scroll Title |
|---|
| anchor | Table_RH_HRH |
|---|
| title | Hardware Revision History |
|---|
|
| Scroll Table Layout |
|---|
|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
style | widths | | sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
| Date | Revision | Changes |
|---|
2019-02-06 | 01 | -
Document Change History
| Page properties |
|---|
|
- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
|
...
| Scroll Title |
|---|
| anchor | Table_RH_DCH |
|---|
| title | Document change history. |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default | style |
|---|
| widths | sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Date | Revision | Contributor | Description |
|---|
| Page info |
|---|
| infoType | Modified date |
|---|
| dateFormat | yyyy-MM-dd |
|---|
| type | Flat |
|---|
|
| | Page info |
|---|
| infoType | Current version |
|---|
| prefix | v. |
|---|
| type | Flat |
|---|
| showVersions | false |
|---|
|
| | Page info |
|---|
| infoType | Modified by |
|---|
| type | Flat |
|---|
| showVersions | false |
|---|
|
| | | v.98 | ED | | -- | all | | Page info |
|---|
| infoType | Modified users |
|---|
| type | Flat |
|---|
| showVersions | false |
|---|
|
| |
|
...