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  1. SMT pin header, J26
  2. SMT pin header, J27
  3. Board to Board  (B2B) Connector, JM1
  4. Board to Board  (B2B) Connectorr, JM2
  5. XMOD header, JX1
  6. Voltage Regulator, U1
  7. User Red LED, D2
  8. User Green LED, D1 (Red)
  9. SFP+ Connector, J1
  10. User Red LED, D3
  11. 50 - pin header solder pad(Not assembled),  J20
  12. 16 - pin header solder pad(Not assembled),  J3,
  13. 10-pin header solder pad(Not assembled), J4 
  14. 50-pin header solder pad(Not assembled), J17

Initial Delivery State

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Notes :Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.If there is no components which might have initial data ( possible on carrier) you must keep the table empty
  • Pin headers (not soldered to the board, but included in the package as separate component)


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Storage device nameContentNotes
---------


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SignalB2BSignal StateNote
PROG_BJM1-94Active LowClear FPGA configuration  vand and initiate a new configuration


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Board to Board (B2B) I/Os

FPGA bank number and number Number of I/O signals and Interfaces connected to the B2B connector:

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B2B ConnectorInterfaceNumber of I/ONotes
JM1



User I/O52 Single ended, 27 Differential-
MGT lanes4 Differential, 2 lanes
MGT reference clock input2 Single ended, 1 Differential
JTAG4 Single ended
SoM control signals2 Single ended'PROG_B', ' DONE'
JM2User I/O36 Single ended or 18 differential-
SFP+ Interface control signals8 Single ended
QSPI interface6 Single ended
UART interface2 Single ended
User LEDs2 Single endedRed, Green
SoM control signals1 Single ended'BOOTMODE'


On-board Pin Header

TEBA0714 is equipped with four pin headers J17, J20, J3 and J4 which are not assembled on the board, in case of need customer can solder the pins and have access to the signals in the following table.

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Pin HeaderInterfaceNumber of I/ONotes
J17



User I/O36 Single ended, 18 DifferentialModule FPGA Bank 14
SPI interface6 Single ended-
Power4 Single ended3.3V, V_CFG
J20User I/O42 Single ended or 21 differentialModule FPGA Bank 34
Power4 Single ended3.3V, V_CFG
User LEDs2 Single endedRed, Green
SoM control signals1 Single ended'BOOTMODE'
J3JTAG 4 Single ended
UART2 Single endedB14_L25, B14_L0
ADC2 Single ended
Clock2 Single ended, 1 Differential
Power4 Single ended3.3V, V_CFG
Control Signals2 Single endedBOOTMODE, PROG_B
J4User I/O6 Single ended or 3 differential
Power2 Single ended3.3V, 3.3V_OUT


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XMOD Header PinSchematicB2B Connector
Connected to
Pin HeaderNote
AB14_L25JM2-97
B14_L25
J3-4UART Transfer
BB14_L0JM2-99
B14_L0
J3-7UART Receive
EBOOTMODEJM2-100
BOOTMODE
J3-9
GPROG_BJM1-94
PROG_B
J3-11
CTCKJM1-90
TCK
J3-4
DTDIJM1-86
TDI
J3-10
FTDOJM1-88
TDO
J3-8
HTMSJM1-92
TMS
J3-12
3.3V3.3VJM1-97,99
3.3V
J3,J4,J17,J20Nominal Input Voltage
VIO
JM2-53
V_CFG-J17-45Configuration Voltage


The DIP-switch S2 on Xmod XMOD Adapter TE0790 must be set as the following table.

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S2
ON
Status
OFFDefault
Description
1Normal modeAdapter board CPLD update mode
Notes      
1ONUpdate Mode JTAG access to SC CPLD only
2
Do not use (illegal setting)
Normal mode
OFFMust be in OFF state always
.3VIO connected to 3.3VPower VIO from pin header J2OFFUser I/O Voltage4Power 3.3V from USBPower 3.3V from pin header J2OFFPower on-board peripherals (FTDI chip & SC CPLD, ...)

The voltages 3.3V (VCC) and VIO (variable SC CPLD I/O-voltage) should be configured by the DIP-switches S2-3 and S2-4 as the following.

3.3V (pin 5) and VIO (pin 6) sourced USB (Pin 5 and Pin 6 are shorted and both are 3.3V)

3OFF3.3V  is inputsupplied from pin headers externally
4OFFVIO is inputsupplied from pin header externally
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S2-3S2-43.3V (VCC) Pin 5VIO Pin 6Description
OFFOFF3.3V from base (input**)VIO from base (input**)3.3V (pin 5) and VIO (pin 6) sourced from base
OFFON3.3V from USB* (output**)VIO from base (input**)VIO sourced from base by Pin 6
ONOFF3.3V from base (input**)3.3V from base (input**)VIO and 3.3V source by base (Pin 5 and Pin 6 are shorted and both must be sourced by 3.3V)
ONON3.3V from USB* (output**)3.3V from USB* (output**)