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changes.mady.by.user Pedram Babakhani

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  • MPSoC:  XCZU2CG - Xilinx Zynq UltraScale+ MPSoC
    • Package: 1SBVA484E
    • Speed Grade: -1 (Slowest)

    • Temperature Grade: Expanded Extended (0 to +128 °C100 °C)

  • RAM/Storages:
    • SDRAM: LPDDR4 -3733 8Gb 256Mx16x 2 
    • SPI Flash 256Mb (32M x 8) 133 MHz
    • EEPROMs 2Kb (256 x 8)
    • EEPROMs 4Kb (512 x 8)

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Scroll Title
anchorFigure_OV_BD
titleTE0802 Block Diagram


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Main Components

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Bootmode signals must be set through DIP Switch S9S1. 

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titleBoot Process

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OFF

MODE Signal State

MODE2

S9-C

MODE1

S9S1-2(B)

MODE0

S9S1-1(A)

Boot Mode

MODE[2:0]=000

OFFOFF

JTAG

MODE[2:0]=001

OFFOFFONQSPI (24 bit)not supported

MODE[2:0]=010

OFF

ONOFFQSPI(32 bit)

MODE[2:0]=011

OFFONONSD0(2.0)
MODE[2:0]=111ONONONUSB(2.0)


Reset setting is available through Push Button BTN6.

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Scroll Title
anchorTable_SIP_B2B
titleGeneral I/O to Pin Header and Connectors Information

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12
FPGA BankConnector I/O Signal CountVoltage LevelNotes
Bank 503Micro USB, J8 (over FTDI)4 Single Ended3.3 VJTAG
Bank 500Micro USB, J8 (over FTDI)2 Single Ended3.3 VUART
Bank 500Micro SD Card, J97 Single Ended3.3 V
Bank 502Micro SD CardETH RJ45, J4 (over ETH PHY)14 Single Ended1.8 V
Bank 505, 502USB 3.0, J11 (USB2 over USB PHY)2 Differential Pairs, 12 Single Ended-- / 1.8V0.85 V

Bank 505, 501

SSD M.2, U5

2 Differential Pairs

0.85 V

Bank 501SSD M.2

,

U5

5 Single Ended

-- / 3.3 V


Bank 505, 501Display Port Connector, J32 Differential Pairs0.85 VBank 26D-Sub Host Socket, J72 , 5 Single Ended--/ 3.3 V
Bank 26, 65, 66,D-Sub Host Socket (VGA), J714 Single Ended3.3 V / 1.8 V / 1.8 V
Bank 65Earphone, J123 Single Ended1.8 V
Bank 500Grove Connector, J102 Single Ended3.3 V
Bank 26Pmod Host Socket, J58 Single Ended3.3 V
Bank 26Pmod Host Socket, J6 8 Single Ended3.3 V


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Scroll Title
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titleTest Points Information

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-

Test Point

SignalsB2B ConnectorNotes
1TP1+1.1V_LPDDR4-
2TP2+1.8V_MGTRAVTT-
3TP3+1.8V_PL-
4TP4FT_B_TX-
5TP5DP_TX_PWR
TP6GND
6TP7GND-7GND-
TP88PMIC2_SDA
-TP99PMIC2_TP-
10TP10ONKEY2-
11TP11PMIC2_SCL-
12TP12DP_TX_HPD
-TP1313DP_TX_PWR
-TP1414INT_SCL1-
15TP15INT_SDA1
-TP1616FT_B_RX-
17TP17CLOCKDIST_OE
-TP1818+0.85V_VCCINT
-TP1919+3.3V-
20TP20+1.8V_PS
-TP2121ERR_STATUS-
22TP22+1.2V_PSPLL
-TP2323GND
-TP2424GND
-TP2525PMIC1_SCA-
26TP26PMIC1_SDA-
27TP27ONKEY1-
28TP28PMIC1_TP
-TP2929POR_B
-TP3030PSBATT-
31TP31SRST_B-
32TP32DONE-
33TP33INIT_B
-TP3434VBUS
-TP3535USB_VBUS
-TP3636PROG_B-
37TP37ERR_OUT-


On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

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Scroll Title
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titleOn-board Peripherals

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Chip/InterfaceDesignatorNotes
Quad SPI Flash Memory81199613U16
LPDDR4 SDRAM81199613U13
EEPROM81199613U2, U18
USB ULPI PHY81199613U22
Ethernet PHY81199613U6
FTDI FT2232H81199613U17
Clock Generator81199613U8
OscillatorsU7, U15, U19, U23, U43
7-Segment Display81199613D9
User LED81199613LED0...7
Push Button81199613BTN1...5
DIP Switch81199613S1, S7../S.8


Quad SPI Flash Memory

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

he TE0802 evaluation board has  one single QSPI flash connected as x4. Flash size depends on the assembly option, default 32MB

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titleQuad SPI Interface MIOs and Pins

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MIO PinSchematicU16 PinNotes
MIO0MIO0B2SPI_CLK
MIO1MIO1D2SPI_DQ1
MIO2MIO2C4SPI_DQ2
MIO3MIO3D4SPI_DQ3
MIO4MIO4D3SPI_DQ0
MIO5MIO5C2SPI_CS


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Scroll Title
anchorTable_OBP_I2C_FPGA_EEP
titleI2C Address for FPGA EEPROM

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MIO PinTypeI2C AddressDesignatorNotes
MIO8...94AA025E48T-I/OT0x50U2EEPROM with MAC



Scroll Title
anchorTable_OBP_FTDI_EEP
titleI2C FTDI EEPROM Interface Pins

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PinSchematicU18 PinNotes
CSEECS1FTDI
CLKEECLK2FTDI
DIN/DOEEDATA3/4FTDI


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Scroll Title
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titleClock Generator Connections and Pins

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Clock Generator PinSignal Schematic NamesConnected toNote
REFP-Pin 3, U43 (Oscillator)
REFSELREFSEL-Pulled-up to +3.3V.
RESETN/SYNCCLK_GEN_RESETPin B5, FPGA Bank 26Pulled-up to +3.3V.
EEPROMSELEEPROMSEL-Pulled-up to +3.3V.
SDA/GPIO2CLK_GEN_SDA

- (Default)

MIO9, FPGA Bank 500 (R185/196 required)

Pin 2, J14 (Pin Header required)

Pulled-up to +3.3V. (Default)

Pulled-up to +3.3V.

Pulled-up to +3.3V.

SCL/GPIO3CLK_GEN_SCL

- (Default)

MIO8, FPGA Bank 500 (R185/196 required)

Pin 3, J14 (Pin Header required)

Pulled-up to +3.3V. (Default)

Pulled-up to +3.3V.

Pulled-up to +3.3V.

OE/GPIO4--Pulled-up to +3.3V.

Y1P

CLK_Y1_P / CLK_DP_PPin G19, FPGA Bank 50527 MHz
Y1NCLK_Y1_N / CLK_DP_NPin G20, FPGA Bank 50527 MHz

Y2P

CLK_Y2_P / CLK_USB_PPin J19, FPGA Bank 50526 MHz
Y2NCLK_Y2_N / CLK_USB_NPin J20, FPGA Bank 50526 MHz

Y3P

CLK_Y3_P / CLK_PCIe_PPin L19, FPGA Bank 505100 MHz
Y3NCLK_Y3_N / CLK_PCIe_NPin L20, FPGA Bank 505100 MHz

Y4P

CLK_Y4_P / SSD_RCLK_PPin 55, U5 (M.2)100 MHz
Y4NCLK_Y4_N / SSD_RCLK_NPin 53, U5 (M.2)100 MHz


Clock Sources

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titleOscillators

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DesignatorSignal Schematic NamesConnected toDescriptionFrequencyNote
U7ETH_XTAL_INPin 34, U6 (Ethernet PHY)Clock for Ethernet25 MHz
U15PS_CLKPin H14, FPGA Bank 503Clock for FPGA33 MHz
U23USB_CLK / USB0_RCLKPin 26, U22 (USB PHY)Clock for USB52 MHz
U43-Pin 5, U8 (Clock Generator)Clock for Clock Generator25 MHz


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Scroll Title
anchorTable_OBP_DIP_SWITCH
titleDIP Switches

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DesignatorSchematicConnected toFunctionalityNote
S1AS1-1(A)MODE0Pin J16, FPGA Bank 503DIPPulled-down to GND.
S1BS1-2(B)MODE1Pin H15, FPGA Bank 503DIPPulled-down to GND.
S1CS1-3(C)USER_CFG0Pin A4, FPGA Bank 66DIPPulled-down to GND.
S1DS1-4(D)USER_CFG1Pin B4, FPGA Bank 66DIPPulled-down to GND.
S7AS7-1(A)USER_SW7Pin M5, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S7BS7-2(B)USER_SW6Pin M4, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S7-3(C)S7CUSER_SW5Pin J2, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S7DS7-4(D)USER_SW4Pin K1, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S8AS8-1(A)USER_SW3Pin L1, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S8BS8-2(B)USER_SW2Pin M1, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S8CS8-3(C)USER_SW1Pin P2, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S8DS8-4(D)USER_SW0Pin P3, FPGA Bank 65DIPPulled-up to +1.8V_PL.


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Scroll Title
anchorFigure_PWR_PD
titlePower Distribution


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Power-On Sequence

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anchorFigure_PWR_PS
titlePower Sequency
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TBD

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PMICs will be reset after pressing Push Button BTN6 (POR_B).

Power Rails

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titleModule Power Rails

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Power Rail NameDirectionNotes
VININSupply Voltage
+5VOutJ1...2
+3.3VOutJ14, J10


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Scroll Title
anchorTable_TS_AMR
titleAbsolute Maximum Ratings

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SymbolsDescriptionMinMaxUnit
VINInput Supply Voltage (J13)-3.57V
T_STGStorage Temperature-40
50
85
V
°C


Recommended Operating Conditions

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Scroll Title
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titleRecommended Operating Conditions

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ParameterMinMaxUnitsReference Document
VIN45.5VSchematic "POWER" (Component: LTC4365ITS8)
T_STG085°CZynq Ultrascale+ Data sheet


Physical Dimensions

Module size: 100 mm × 100 mm.  Please download the assembly diagram for exact numbers.

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Scroll Title
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titleTrenz Electronic Shop Overview

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Trenz Shop TE0702 TE0802 Overview Page
English pageGerman page


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Scroll Title
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titleHardware Revision History

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DateRevisionChangesDocumentation Link
2019-04-2902
  • Added suppressor 1SMA5.0AT3G on power input
  • Changed OV and UV protection range
  • Changed VGA schematic
  • USB page: VBUS resistor changed on 1KThe revision has been renamed as TE0802-02-2AEV2-A
REV02
2018-10-1701ReleaseREV01


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

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Scroll Title
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titleDocument Change History

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DateRevisionContributorDescription

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Initial Release

  • Typo correction
2020-11-19v.65Pedram Babakhani
  • initial release

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