Page History

Template Revision 2.7 - on construction

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HTML

<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
<style>
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  width: 100% !important;
  max-width: 1200px !important;
 }
</style>

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hidden	true
id	Comments

Important General Note:

Date	Version	Changes	Author
2023-12-14	3.1.17	updated according to Vivado 2023.2	ma
2023-06-13	3.1.16	Design flow: added alternative programming files in Petalinux added chapter FSBL Patch in Software Design - Petalinux	ma
2023-06-01	3.1.15	removed u-boot.dtb from Design flow	ma
2023-06-01	3.1.14	expandable lists for revision history and supported hardware	wh
2023-05-25	3.1.13	updated according to Vivado 2022.2	ma
2023-02-08	3.1.12	removed content of Special FSBL for QSPI programming	ma
2022-08-24	3.1.11	Modification from link "available short link"	ma
2022-01-25	3.1.10	removed u-boot.dtb from QSPI-Boot mode and SD-Boot mode. Is implemented in BOOT.bin corrected Boot Source File in Boot Script-File	ma
2022-01-14	3.1.9	extended notes for microblaze boot process with linux add u.boot.dtb to petalinux notes add dtb to prebuilt content replace 20.2 with 21.2	jh
2021-06-28	3.1.8	added boot process for Microblaze minor typos, formatting	ma
2021-06-01	3.1.7	carrier reference note	jh
2021-05-04	3.1.6	removed zynq_ from zynq_fsbl	ma
2021-04-28	3.1.5	added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export minor typos, formatting	ma
2021-04-27	3.1.4	Version History changed from list to table Design flow removed step 5 from Design flow changed link from TE Board Part Files to Vivado Board Part Flow changed cmd shell from picture to codeblock added hidden template for "Copy PetaLinux build image files", depending from hardware added hidden template for "Power on PCB", depending from hardware Usage update of boot process Requirements - Hardware added "^*used as reference" for hardware requirements all placed a horizontal separation line under each chapter heading changed title-alignment for tables from left to center all tables added "<project folder>\board_files" in Vivado design sources	ma
	3.1.3	Design Flow formatting Launch formatting	ma
	3.1.2	minor typing corrections replaced SDK by Vitis changed from / to \ for windows paths replaced <design name> by <project folder> added "" for path names added boot.src description added USB for programming	ma
	3.1.1	swapped order from prebuilt files minor typing corrections removed Win OS path length from Design flow, added as caution in Design flow	ma
	3.1	Fix problem with pdf export and side scroll bar update 19.2 to 20.2 add prebuilt content option
	3.0	add fix table of content add table size as macro removed page initial creator

Custom_table_size_100

Page properties

hidden	true
id	Comments

Important General Note:

Export PDF to download, if vivado revision is changed!

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

Figure template (note: inner scroll ignore/only only with drawIO object):

Scroll Title

anchor	Figure_xyz
title	Text

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, use

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Table template:
- Layout macro can be use for landscape of large tables
- Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)
Scroll Title
anchor Table_xyz
title Text
Scroll Table Layout
orientation portrait
sortDirection ASC
repeatTableHeaders default
sortByColumn 1
sortEnabled false
cellHighlighting true
Example Comment
1 2

...

Overview

Scroll Ignore

scroll-pdf	true
scroll-office	true
scroll-chm	true
scroll-docbook	true
scroll-eclipsehelp	true
scroll-epub	true
scroll-html	true

Page properties

hidden	true
id	Comments

Notes :

short description of the design
Short Link of "Scroll only" macro:
- Use short link the Wiki Resource page, for example: http://trenz.org/te0720-info
- List of available short links: https://wiki.trenz-electronic.de/display/TI/Redirects

ZynqMP PS Design with Linux Example and simple frequency counter to measure SI5338 Reference CLK with Vivado HW-Manager.
Wiki Resources page: http://trenz.org/te0820-info

Key Features

Page properties

hidden	true
id	Comments

Notes :

Add basic key futures, which can be tested with the design

Excerpt
Vitis/Vivado 2023.2 PetaLinux SD ETH USB I2C RTC FMeter MAC from EEPROM User LED (PCB REV03 only) Modified FSBL for SI5338 programming

Revision History

Page properties

hidden	true
id	Comments

Notes :

add every update file on the download
add design changes on description

Expand

title	Expand List

Scroll Title

anchor	Table_DRH
title-alignment	center
title	Design Revision History

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Date	Vivado	Project Built	Authors	Description
2024-03-05	2023.2	TE0820-test_board-vivado_2023.2-build_4_20240305102020.zip TE0820-test_board_noprebuilt-vivado_2023.2-build_4_20240305102020.zip	Manuela Strücker	bugfix file_location.txt update USB available in uboot
2024-02-23	2023.2	TE0820-test_board-vivado_2023.2-build_4_20240222140518.zip TE0820-test_board_noprebuilt-vivado_2023.2-build_4_20240222140518.zip	Manuela Strücker	2023.2 release new assembly variants
2023-06-22	2022

...

Export PDF to download, if vivado revision is changed!

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

...

Figure template (note: inner scroll ignore/only only with drawIO object):

...

anchor	Figure_xyz
title	Text

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, use

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

...

Table template:

Layout macro can be use for landscape of large tables
Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)

...

anchor	Table_xyz
title	Text

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

...

Scroll pdf ignore

Overview

Page properties

hidden	true
id	Comments

Notes :

short description of the design
Short Link of "Scroll only" macro:
- Use short link the Wiki Resource page, for example: http://trenz.org/te0720-info
- List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

ZynqMP PS Design with Linux Example and simple frequency counter to measure SI5338 Reference CLK with Vivado HW-Manager.
Wiki Resources page: http://trenz.org/te0820-info

Key Features

Page properties

hidden	true
id	Comments

Notes :

Add basic key futures, which can be tested with the design

Excerpt
Vitis/Vivado 2019.2 PetaLinux SD ETH USB I2C RTC FMeter MAC from EEPROM User LED (PCB REV03 only) Modified FSBL for SI5338 programming Special FSBL for QSPI programming

Revision History

Page properties

hidden	true
id	Comments

Notes :

add every update file on the download
add design changes on description

...

anchor	Table_DRH
title	Design Revision History

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

...

add fsbl_flash binary
Vitis script updates (include linux domain and prebuilt linux files for vitis)
prebuilt binary export on selection guide

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2019.2 update
Vitis support

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New assembly variants

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bugfix fsbl (removed second PSU init)

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new assembly variants
USB2 only (change PS IP and device tree)
FSBL changes

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renamed ...D variantes to ...A

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TE0820-test_board_noprebuilt-vivado_2018.3-build_01_20190221103025.zip
TE0820-test_board-vivado_2018.3-build_01_20190221102913.zip

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TE Script update
rework of the FSBLs
SI5338 CLKBuilder Pro Project
some additional Linux features
MAC from EEPROM
new assembly variants
remove special compiler flags, which was needed in 2018.2

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TE0820-test_board_noprebuilt-vivado_2018.2-build_03_20181031164506.zip

TE0820-test_board-vivado_2018.2-build_03_20181031164452.zip

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new assembly variants
update optional petalinux startup init script

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correction:
- TE0820-03-4EV-1EA has 2GB DDR, now 2GB instead of 1GB is initialised
- small changes on DDR setup of TE0820-02-2EG-1EE

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different design for REV03
small petalinux changes
IO renaming
additional notes for FSBL generated with Win SDK
changed *.bif

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bugfix board part files BANK1 MIO voltages
Add "dummy" PS USB3 parameter so solve problems with some USB2 devices

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solved JTAG/Linux issue

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board part csv update

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rework board part files
solved USB, QSPI and PHy issue

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solved SD WP Problem

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initial release

Release Notes and Know Issues

Page properties

hidden	true
id	Comments

Notes :

add known Design issues and general notes for the current revision
do not delete known issue, add fixed version time stamp if issue fixed

...

anchor	Table_KI
title	Known Issues

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

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Do not use HW Manager connection, or if debugging is nessecary:

Boot linux with usb terminal
From the terminal: root root mount ifconfig eth0
Open two new SSH terminals via ethernet: root root , run user application ...
Exit and close the usb terminal

...

Requirements

Software

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hidden	true
id	Comments

Notes :

list of software which was used to generate the design

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anchor	Table_SW
title	Software

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

...

Hardware

Page properties

hidden	true
id	Comments

Notes :

list of software which was used to generate the design

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

...

anchor	Table_HWM
title	Hardware Modules

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

...

Design supports following carriers:

...

anchor	Table_HWC
title	Hardware Carrier

script update Board Part update (minor changes)
2020-01-22	2019.2	TE0820-test_board_noprebuilt-vivado_2019.2-build_3_20200122154341.zip TE0820-test_board-vivado_2019.2-build_3_20200122154318.zip	John Hartfiel	script update for linux user
2020-01-14	2019.2	TE0820-test_board-vivado_2019.2-build_3_20200114081551.zip TE0820-test_board_noprebuilt-vivado_2019.2-build_3_20200114081612.zip	John Hartfiel	add fsbl_flash binary Vitis script updates (include linux domain and prebuilt linux files for vitis) prebuilt binary export on selection guide
2019-12-19	2019.2	TE0820-test_board-vivado_2019.2-build_1_20191219075647.zip TE0820-test_board_noprebuilt-vivado_2019.2-build_1_20191219080228.zip	John Hartfiel	2019.2 update Vitis support
2019-10-29	2018.3	TE0820-test_board_noprebuilt-vivado_2018.3-build_09_20191029071045.zip TE0820-test_board-vivado_2018.3-build_09_20191029071028.zip	John Hartfiel	new assembly variants
2019-08-09	2018.3	TE0820-test_board_noprebuilt-vivado_2018.3-build_07_20190809084040.zip TE0820-test_board-vivado_2018.3-build_07_20190809083901.zip	John Hartfiel	bugfix fsbl (removed second PSU init)
2019-06-19	2018.3	TE0820-test_board_noprebuilt-vivado_2018.3-build_06_20190619073300.zip TE0820-test_board-vivado_2018.3-build_06_20190619073243.zip	John Hartfiel	new assembly variants USB2 only (change PS IP and device tree) FSBL changes
2019-04-01	2018.3	TE0820-test_board_noprebuilt-vivado_2018.3-build_03_20190401130135.zip TE0820-test_board-vivado_2018.3-build_03_20190401130123.zip	John Hartfiel	renamed ...D variants to ...A
2019-02-21	2018.3	TE0820-test_board_noprebuilt-vivado_2018.3-build_01_20190221103025.zip TE0820-test_board-vivado_2018.3-build_01_20190221102913.zip	John Hartfiel	TE Script update rework of the FSBLs SI5338 CLKBuilder Pro Project some additional Linux features MAC from EEPROM new assembly variants remove special compiler flags, which was needed in 2018.2
2018-10-31	2018.2	TE0820-test_board_noprebuilt-vivado_2018.2-build_03_20181031164506.zip TE0820-test_board-vivado_2018.2-build_03_20181031164452.zip	John Hartfiel	new assembly variants update optional petalinux startup init script
2018-09-12	2018.2	TE0820-test_board_noprebuilt-vivado_2018.2-build_03_20180912094615.zip TE0820-test_board-vivado_2018.2-build_03_20180912094558.zip	John Hartfiel	correction: TE0820-03-4EV-1EA has 2GB DDR, now 2GB instead of 1GB is initialised small changes on DDR setup of TE0820-02-2EG-1EE
2018-08-15	2018.2	TE0820-test_board-vivado_2018.2-build_01_20180706212937.zip TE0820-test_board_noprebuilt-vivado_2018.2-build_01_20180706212952.zip	John Hartfiel	different design for REV03 small petalinux changes IO renaming additional notes for FSBL generated with Win SDK changed *.bif
2018-06-19	2017.4	TE0820-test_board-vivado_2017.4-build_10_20180619160713.zip TE0820-test_board_noprebuilt-vivado_2017.4-build_10_20180619160728.zip	John Hartfiel	bugfix board part files BANK1 MIO voltages Add "dummy" PS USB3 parameter so solve problems with some USB2 devices
2018-05-24	2017.4	TE0820-test_board-vivado_2017.4-build_10_20180524151356.zip TE0820-test_board_noprebuilt-vivado_2017.4-build_10_20180524151342.zip	John Hartfiel	solved Linux Flash issue new assembly variant
2018-04-25	2017.4	TE0820-test_board-vivado_2017.4-build_07_20180425134435.zip TE0820-test_board_noprebuilt-vivado_2017.4-build_07_20180425134459.zip	John Hartfiel	new assembly variants
2018-02-06	2017.4	TE0820-test_board-vivado_2017.4-build_06_20180206203359.zip TE0820-test_board_noprebuilt-vivado_2017.4-build_06_20180206203414.zip	John Hartfiel	solved JTAG/Linux issue
2018-02-01	2017.4	TE0820-test_board-vivado_2017.4-build_05_20180201084319.zip TE0820-test_board_noprebuilt-vivado_2017.4-build_05_20180201094724.zip	John Hartfiel	board part csv update
2018-01-24	2017.4	TE0820-test_board-vivado_2017.4-build_05_20180124085247.zip TE0820-test_board_noprebuilt-vivado_2017.4-build_05_20180124085303.zip	John Hartfiel	rework board part files solved USB, QSPI and PHY issue
2017-11-21	2017.2	TE0820-test_board-vivado_2017.2-build_05_20171121160552.zip TE0820-test_board_noprebuilt-vivado_2017.2-build_05_20171121160606.zip	John Hartfiel	solved SD SDX Cards Problem Separate csv name for all assembly variants
2017-11-20	2017.2	TE0820-test_board-vivado_2017.2-build_05_20171120162931.zip TE0820-test_board_noprebuilt-vivado_2017.2-build_05_20171120162851.zip	John Hartfiel	solved SD WP Problem
2017-10-19	2017.2	TE0820-test_board-vivado_2017.2-build_05_20171019104824.zip TE0820-test_board_noprebuilt-vivado_2017.2-build_05_20171019104837.zip	John Hartfiel	initial release

Release Notes and Know Issues

Page properties

hidden	true
id	Comments

Notes :

add known Design issues and general notes for the current revision
do not delete known issue, add fixed version time stamp if issue fixed

Scroll Title

anchor	Table_KI
title-alignment	center
title	Known Issues

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Issues	Description	Workaround	To be fixed version
Uboot: Ethernet not present	Ethernet in Uboot cannot be used due to no MAC address set (Error: ethernet@ff0e0000 address not set.)	please set CONFIG_NET_RANDOM_ETHADDR in petalinux-config -c u-boot as a side effect, MAC address will be random in Linux also	2023.2 version
Xilinx Software	Incompatibility of board files for ZynqMP with eMMC activated between 2021.2 and 2021.2.1 patch, see Xilinx Forum Request	use corresponding board files for the Vivado versions	--
Uboot did not start	Effected Design: TE0820-test_board-vivado_2020.2-build_5_20210601084124.zip TE0820-test_board_noprebuilt-vivado_2020.2-build_5_20210601092528.zip	Use older version, this will be fixed as soon as possible	Solved with 20220124 update
Flash access on Linux	Device tree is not correct on Linux	add compatibility to "compatible “jedec,spi-nor”"	Solved with 20180524 update
USB UART Terminal is blocked / SDK Debugging is blocked	This happens only with 2017.4 Linux , when JTAG connection is established on Vivado HW Manager.	Do not use HW Manager connection, or if debugging is necessary: Boot linux with usb terminal From the terminal: root root mount ifconfig eth0 Open two new SSH terminals via ethernet: root root , run user application ... Exit and close the usb terminal	Solved with 20180206 update

Requirements

Software

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hidden	true
id	Comments

Notes :

list of software which was used to generate the design

Scroll Title

anchor	Table_SW
title-alignment	center
title	Software

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Software	Version	Note
Vitis	2023.2	needed, Vivado is included into Vitis installation
PetaLinux	2023.2	needed
SI ClockBuilder Pro	---	optional

Hardware

Page properties

hidden	true
id	Comments

Notes :

list of software which was used to generate the design

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on "<project folder>\board_files\*_board_files.csv"

Design supports following modules:

Expand

title	Expand List

Scroll Title

anchor	Table_HWM
title-alignment	center
title	Hardware Modules

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default

...

Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 SoM Carriers

...

Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 cm carriers
Used as reference carrier.

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Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 SoM Carriers

...

Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 SoM Carriers

...

Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 SoM Carriers
No SD Slot available, pins goes to Pin Header
For TEBA0841 REV01, please contact TE support

Additional HW Requirements:

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anchor	Table_AHW
title	Additional Hardware

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

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Content

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hidden	true
id	Comments

Notes :

content of the zip file

For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

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anchor	Table_DS
title	Design sources

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orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
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Additional Sources

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anchor	Table_ADS
title	Additional design sources

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

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Prebuilt

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hidden	true
id	Comments

Notes :

...

anchor	Table_PF
title	Prebuilt files

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

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File

...

File-Extension

...

Description

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Debian SD-Image

...

*.img

...

Debian Image for SD-Card

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MCS-File

...

*.mcs

...

Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

...

MMI-File

...

*.mmi

...

File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

...

SREC-File

...

*.srec

...

Converted Software Application for MicroBlaze Processor Systems

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anchor	Table_PF
title	Prebuilt files (only on ZIP with prebult content)

Scroll Table Layout

orientation	portrait
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sortByColumn	1
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cellHighlighting	true

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File

...

File-Extension

...

Description

...

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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id	Comments

Important set new Vivado version link on every Design update of new vivado version!
Set Link to download folder (Remove ../de/.. ../en/.. from url) for example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0712/Reference_Design/2018.2/test_board

Reference Design is available on:

TE0820 "Test Board" Reference Design

Design Flow

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id	Comments

Notes :

Basic Design Steps
Add/ Remove project specific description

Note
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

Launch

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Note:

Programming and Startup procedure

Programming

Note
Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

Note: Depending on CPLD Firmware and Boot Mode settings, QSPI boot with Linux image on SD or complete SD Boot is possible.

Get prebuilt boot binaries

_create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Press 0 and enter to start "Module Selection Guide"
1. Select assembly version
2. Validate selection
3. Select Create and open delivery binary folder
  Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated

QSPI

Optional for Boot.bin on QSPI Flash and image.ub on SD.

Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
optional "TE::pr_program_flash_binfile -swapp hello_te0820" possible
Copy image.ub on SD-Card
- use files from (<project foler>/_binaries_<Artikel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
Insert SD-Card

SD

Use this description for CPLD Firmware with SD Boot selectable.

Copy image.ub and Boot.bin on SD-Card.
- For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

Prepare HW like described on section Programming
Connect UART USB (most cases same as JTAG)
Select SD Card or QSPI as Boot Mode (Depends on used programming variant)
Note: See TRM of the Carrier, which is used.
Power On PCB
Note: 1. ZynqMP Boot ROM loads PMU Firmware and FSBL from SD/QSPI Flash into OCM, 2. FSBL loads ATF(bl31.elf) and U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR

Linux

...

Speed: 115200
COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)

...

User Name: root
Password: root

...

I2C 0 Bus type: i2cdetect -y -r 0
RTC check: dmesg | grep rtc
ETH0 works with udhcpc
USB type "lsusb" or connect USB2.0 device

...

Webserver to get access to Zynq
1. insert IP on web browser to start web interface
init.sh scripts
1. add init.sh script on SD, content will be load automatically on startup (template included in ./misc/SD)

...

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id	Comments

Note:

Add picture of HW Manager
add notes for the signal either groups or topics, for example:
Control:
- add controllable IOs with short notes..
Monitoring:
- add short notes for signals which will be monitored only
SI5338_CLK0 Counter:
Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.Note: Frequency Counter is inaccurate and displayed unit is Hz

SI5338_CLK0 Counter:

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
1. Set radix from VIO signals to unsigned integer.
  Note: Frequency Counter is inaccurate and displayed unit is Hz

SI5338 CLK is configured to 200MHz by default.

PCB REV03 Design:

User LED, see: TE0820 CPLD#LED

Scroll Title

anchor	Figure_VHM
title	Vivado Hardware Manager

Image Removed

PCB REV01, REV02 Design:

PHY LEDS, see: TE0820-REV01_REV02 CPLD#X0/X1Pin
CPLD Firmware, see: TE0820-REV01_REV02 CPLD#X0/X1Pin

Scroll Title

anchor	Figure_VHM1
title	Vivado Hardware Manager PCB REV01,REV02

Image Removed

System Design - Vivado

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id	Comments

Note:

Description of Block Design, Constrains... BD Pictures from Export...

Block Design

PCB REV03

Image Removed

PCB REV01 REV02

Image Removed

PS Interfaces

Activated interfaces:

...

Constrains

Basic module constrains

Code Block

language	ruby
title	_i_bitgen_common.xdc

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design

Design specific constrain

Code Block

language	ruby
title	_i_io.xdc

set_property PACKAGE_PIN K9 [get_ports {SI5338_CLK0_D_clk_p[0]}]
set_property IOSTANDARD LVDS [get_ports {SI5338_CLK0_D_clk_p[0]}]
set_property DIFF_TERM TRUE [get_ports {SI5338_CLK0_D_clk_p[0]}]

set_property PACKAGE_PIN H1 [get_ports {x0[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {x0[0]}]
set_property PACKAGE_PIN J1 [get_ports {x1[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {x1[0]}]

Software Design - Vitis

Page properties

hidden	true
id	Comments

Note:

optional chapter separate
sections for different apps

For SDK project creation, follow instructions from:

Vitis

Application

...

hidden	true
id	Comments

----------------------------------------------------------

FPGA Example

todo..

----------------------------------------------------------

Zynq Example:

zynq_fsbl

TE modified 2018.3 FSBL

General:

Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\
General Changes:
- Display FSBL Banner and Device ID

Module Specific:

Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY

zynq_fsbl_flash

TE modified 2018.3 FSBL

General:

Modified Files: main.c
General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 2018.3 FSBL

General:

Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
General Changes:
- Display FSBL Banner and Device Name

Module Specific:

Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 2018.3 FSBL

General:

Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation

zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Template location: ./sw_lib/sw_apps/

zynqmp_fsbl

TE modified 2019.2 FSBL

General:

Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
General Changes:
- Display FSBL Banner and Device Name

Module Specific:

Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 2019.2 FSBL

General:

Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation

zynqmp_pmufw

Xilinx default PMU firmware.

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Software Design - PetaLinux

Page properties

hidden	true
id	Comments

Note:

optional chapter separate
sections for linux
Add "No changes." or "Activate: and add List"

For PetaLinux installation and project creation, follow instructions from:

PetaLinux KICKstart

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC=""

U-Boot

Start with petalinux-config -c u-boot
Changes:

...

CONFIG_ENV_IS_NOWHERE=y

...

# CONFIG_ENV_IS_IN_SPI_FLASH is not set

...

CONFIG_I2C_EEPROM=y

...

CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA

...

CONFIG_SYS_I2C_EEPROM_ADDR=0x50

...

CONFIG_SYS_I2C_EEPROM_BUS=0

...

CONFIG_SYS_EEPROM_SIZE=256

...

CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=0

...

CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=0

...

CONFIG_SYS_I2C_EEPROM_ADDR_LEN=1

~~TE0820-ES1~~	~~es1~~	~~REV01~~	~~1GB~~	~~64MB~~	~~4GB~~	NA	~~Not longer supported by vivado~~
~~TE0820-02-02CG-1E~~	~~2cg_1e_1gb~~	~~REV02~~	~~1GB~~	~~64MB~~	~~4GB~~	NA	~~Not longer supported use 2020.2 or older~~
~~TE0820-02-02CG-1EA~~	~~2cg_1e_1gb~~	~~REV02~~	~~1GB~~	~~128MB~~	~~4GB~~	NA	~~Not longer supported use 2020.2 or older~~
~~TE0820-02-02EG-1E~~	~~2eg_1e_1gb~~	~~REV02~~	~~1GB~~	~~64MB~~	~~4GB~~	NA	~~Not longer supported use 2020.2 or older~~
~~TE0820-02-02EG-1E3~~	~~2eg_1e_1gb~~	~~REV02~~	~~1GB~~	~~64MB~~	~~4GB~~	~~2.5 mm connectors~~	~~Not longer supported use 2020.2 or older~~
~~TE0820-02-02EG-1EA~~	~~2eg_1e_1gb~~	~~REV02~~	~~1GB~~	~~128MB~~	~~4GB~~	NA	~~Not longer supported use 2020.2 or older~~
~~TE0820-02-02EG-1EL~~	~~2eg_1e_1gb~~	~~REV02~~	~~1GB~~	~~128MB~~	~~4GB~~	~~2.5 mm connectors~~	~~Not longer supported use 2020.2 or older~~
~~TE0820-02-03CG-1E~~	~~3cg_1e_1gb~~	~~REV02~~	~~1GB~~	~~64MB~~	~~4GB~~	NA	~~Not longer supported use 2020.2 or older~~
~~TE0820-02-03CG-1EA~~	~~3cg_1e_1gb~~	~~REV02~~	~~1GB~~	~~128MB~~	~~4GB~~	NA	~~Not longer supported use 2020.2 or older~~
~~TE0820-02-03EG-1E~~	~~3eg_1e_1gb~~	~~REV02~~	~~1GB~~	~~64MB~~	~~4GB~~	NA	~~Not longer supported use 2020.2 or older~~
~~TE0820-02-03EG-1E3~~	~~3eg_1e_1gb~~	~~REV02~~	~~1GB~~	~~64MB~~	~~4GB~~	~~2.5 mm connectors~~	~~Not longer supported use 2020.2 or older~~
~~TE0820-02-03EG-1EA~~	~~3eg_1e_1gb~~	~~REV02~~	~~1GB~~	~~128MB~~	~~4GB~~	NA	~~Not longer supported use 2020.2 or older~~
~~TE0820-02-03EG-1EL~~	~~3eg_1e_1gb~~	~~REV02~~	~~1GB~~	~~128MB~~	~~4GB~~	~~2.5 mm connectors~~	~~Not longer supported use 2020.2 or older~~
~~TE0820-02-04CG-1EA~~	~~4cg_1e_1gb~~	~~REV02~~	~~1GB~~	~~128MB~~	~~4GB~~	NA	~~Not longer supported use 2020.2 or older~~
TE0820-03-02CG-1EA	2cg_1e_2gb	REV03	2GB	128MB	4GB	NA	NA
TE0820-03-02CG-1ED	2cg_1e_2gb	REV03	2GB	128MB	8GB	NA	NA
TE0820-03-02EG-1EA	2eg_1e_2gb	REV03	2GB	128MB	4GB	NA	NA
TE0820-03-02EG-1EL	2eg_1e_2gb	REV03	2GB	128MB	4GB	2.5 mm connectors	NA
TE0820-03-03CG-1EA	3cg_1e_2gb	REV03	2GB	128MB	4GB	NA	NA
TE0820-03-03EG-1EA	3eg_1e_2gb	REV03	2GB	128MB	4GB	NA	NA
TE0820-03-03EG-1EL	3eg_1e_2gb	REV03	2GB	128MB	4GB	2.5 mm connectors	NA
TE0820-03-04CG-1EA	4cg_1e_2gb	REV03	2GB	128MB	4GB	NA	NA
TE0820-03-04EV-1EA	4ev_1e_2gb	REV03	2GB	128MB	4GB	NA	NA
TE0820-03-2AE21FA	2cg_1e_2gb	REV03	2GB	128MB	8GB	NA	NA
TE0820-03-2AI21FA	2cg_1i_2gb	REV03	2GB	128MB	8GB	NA	NA
TE0820-03-2BE21FA	2eg_1e_2gb	REV03	2GB	128MB	8GB	NA	NA
TE0820-03-2BE21FL^*	2eg_1e_2gb	REV03	2GB	128MB	8GB	2.5 mm connectors	NA
TE0820-03-2BI21FA	2eg_1i_2gb	REV03	2GB	128MB	8GB	NA	NA
TE0820-03-2BI21FL	2eg_1i_2gb	REV03	2GB	128MB	8GB	2.5 mm connectors	NA
TE0820-03-3AE21FA	3cg_1e_2gb	REV03	2GB	128MB	8GB	NA	NA
TE0820-03-3AI210A	3cg_1i_2gb	REV03	2GB	128MB	0GB	NA	NA
TE0820-03-3AI21FA	3cg_1i_2gb	REV03	2GB	128MB	8GB	NA	NA
TE0820-03-3BE21FA	3eg_1e_2gb	REV03	2GB	128MB	8GB	NA	NA
TE0820-03-3BE21FL	3eg_1e_2gb	REV03	2GB	128MB	8GB	2.5 mm connectors	NA
TE0820-03-4AE21FA	4cg_1e_2gb	REV03	2GB	128MB	8GB	NA	NA
TE0820-03-4AI21FI	4cg_1i_x_2gb	REV03	2GB	128MB	8GB	without ETH PHY	NA
TE0820-03-4DE21FA	4ev_1e_2gb	REV03	2GB	128MB	8GB	NA	NA
TE0820-03-4DE21FC	4ev_1e_2gb	REV03	2GB	128MB	8GB	without encryption NCNR	NA
TE0820-03-4DE21FL	4ev_1e_2gb	REV03	2GB	128MB	8GB	2.5 mm connectors	NA
TE0820-03-4DI21FA	4ev_1i_2gb	REV03	2GB	128MB	8GB	NA	NA
TE0820-03-5DI21FA	5ev_1i_2gb	REV03	2GB	128MB	8GB	NA	NA
TE0820-03-5DR21FA	5ev_1q_2gb	REV03	2GB	128MB	8GB	NA	NA
TE0820-04-2AE21FA	2cg_1e_2gb	REV04	2GB	128MB	8GB	NA	NA
TE0820-04-2AI21FA	2cg_1i_2gb	REV04	2GB	128MB	8GB	NA	NA
TE0820-04-2AI21MC	2cg_1i_2gb	REV04	2GB	128MB	8GB	NA	NA
TE0820-04-2BE21-V1	2eg_1e_2gb	REV04	2GB	128MB	8GB	NA	Customised
TE0820-04-2BE21FA	2eg_1e_2gb	REV04	2GB	128MB	8GB	NA	NA
TE0820-04-2BE21FAJ	2eg_1e_2gb	REV04	2GB	128MB	8GB	without spacers	NA
TE0820-04-2BE21FL	2eg_1e_2gb	REV04	2GB	128MB	8GB	2.5 mm connectors	NA
TE0820-04-2BE21MA	2eg_1e_2gb	REV04	2GB	128MB	8GB	NA	NA
TE0820-04-2BE21MAJ	2eg_1e_2gb	REV04	2GB	128MB	8GB	NA	NA
TE0820-04-2BI21FA	2eg_1i_2gb	REV04	2GB	128MB	8GB	NA	NA
TE0820-04-2BI21FL	2eg_1i_2gb	REV04	2GB	128MB	8GB	2.5 mm connectors	NA
TE0820-04-2BI21MA	2eg_1i_2gb	REV04	2GB	128MB	8GB	NA	NA
TE0820-04-2BI21ML	2eg_1i_2gb	REV04	2GB	128MB	8GB	NA	NA
TE0820-04-3AE21FA	3cg_1e_2gb	REV04	2GB	128MB	8GB	NA	NA
TE0820-04-3AE21MA	3cg_1e_2gb	REV04	2GB	128MB	8GB	NA	Other EMMC mfr
TE0820-04-3AI21FA	3cg_1i_2gb	REV04	2GB	128MB	8GB	NA	NA
TE0820-04-3AI21FAT	3cg_1i_2gb	REV04	2GB	128MB	8GB	NA	Customer supplied
TE0820-04-3BE21FA	3eg_1e_2gb	REV04	2GB	128MB	8GB	NA	NA
TE0820-04-3BE21FL	3eg_1e_2gb	REV04	2GB	128MB	8GB	2.5 mm connectors	NA
TE0820-04-3BE21KA	3eg_1e_2gb	REV04	2GB	128MB	64GB	NA	NA
TE0820-04-3BE21MA	3eg_1e_2gb	REV04	2GB	128MB	8GB	NA	NA
TE0820-04-3BE21ML	3eg_1e_2gb	REV04	2GB	128MB	8GB	2.5 mm connectors	Other EMMC mfr
TE0820-04-3BE21MLZ	3eg_1e_2gb	REV04	2GB	128MB	8GB	2.5 mm connectors	Other EMMC mfr
TE0820-04-4AE21FA	4cg_1e_2gb	REV04	2GB	128MB	8GB	NA	NA
TE0820-04-4AE21MA	4cg_1e_2gb	REV04	2GB	128MB	8GB	NA	NA
TE0820-04-4AI21FI	4cg_1i_x_2gb	REV04	2GB	128MB	8GB	without ETH PHY	NA
TE0820-04-4BI21KL	4eg_1i_2gb	REV04	2GB	128MB	64GB	2.5 mm connectors	NA
TE0820-04-4DE21FA	4ev_1e_2gb	REV04	2GB	128MB	8GB	NA	NA
TE0820-04-4DE21FL	4ev_1e_2gb	REV04	2GB	128MB	8GB	2.5 mm connectors	NA
TE0820-04-4DE21MA	4ev_1e_2gb	REV04	2GB	128MB	8GB	NA	Other EMMC mfr
TE0820-04-4DI21FA	4ev_1i_2gb	REV04	2GB	128MB	8GB	NA	NA
TE0820-04-4DI21MA	4ev_1i_2gb	REV04	2GB	128MB	8GB	NA	Other EMMC mfr
TE0820-04-5DI21FA	5ev_1i_2gb	REV04	2GB	128MB	8GB	NA	NA
TE0820-04-5DI21MA	5ev_1i_2gb	REV04	2GB	128MB	8GB	NA	NA
TE0820-04-5DR21FA	5ev_1q_2gb	REV04	2GB	128MB	8GB	NA	NA
TE0820-04-S002	3eg_1e_2gb	REV04	2GB	128MB	8GB	NA	Other EMMC mfr\|Custom supplied TE0820-04-3BE21MA
TE0820-04-S002C1	2eg_1e_2gb	REV04	2GB	128MB	8GB	NA	CAO
TE0820-04-S003	3eg_1e_2gb	REV04	2GB	128MB	8GB	2.5 mm connectors	Other EMMC mfr
TE0820-04-S004	2eg_1e_2gb	REV04	2GB	128MB	8GB	NA	CAO
TE0820-04-S005	4cg_1e_2gb	REV04	2GB	128MB	8GB	NA	Other EMMC mfr\|Custom supplied TE0820-04-4AE21MA
TE0820-04-S006	4ev_1e_2gb	REV04	2GB	128MB	8GB	NA	CAO:Other EMMC mfr
TE0820-04-S009	3eg_1e_2gb	REV04	2GB	128MB	8GB	2.5 mm connectors	Other EMMC mfr
TE0820-04-S010	4ev_1e_2gb	REV04	2GB	128MB	8GB	NA	CAO:Other EMMC mfr
TE0820-04-S013	3eg_1e_2gb	REV04	2GB	128MB	8GB	2.5 mm connectors	CAO:Other EMMC mfr
TE0820-04-S016	3eg_1e_2gb	REV04	2GB	128MB	8GB	2.5 mm connectors	CAO:Other EMMC mfr
TE0820-04-S018	4cg_1e_2gb	REV04	2GB	128MB	8GB	NA	CAO
TE0820-05-2AE21MA	2cg_1e_2gb	REV05	2GB	128MB	8GB	NA	NA
TE0820-05-2AE21MAZ	2cg_1e_2gb	REV05	2GB	128MB	8GB	NA	NA
TE0820-05-2AE81MA	2cg_1e_2gb	REV05	2GB	128MB	8GB	NA	NA
TE0820-05-2AI21MA	2cg_1i_2gb	REV05	2GB	128MB	8GB	NA	NA
TE0820-05-2AI81MA	2cg_1i_2gb	REV05	2GB	128MB	8GB	NA	NA
TE0820-05-2BE21MA	2eg_1e_2gb	REV05	2GB	128MB	8GB	NA	NA
TE0820-05-2BE21MAJ	2eg_1e_2gb	REV05	2GB	128MB	8GB	NA	NA
TE0820-05-2BI21MA	2eg_1i_2gb	REV05	2GB	128MB	8GB	NA	NA
TE0820-05-2BI81ML	2eg_1i_2gb	REV05	2GB	128MB	8GB	2.5 mm connectors	NA
TE0820-05-3AE21MA	3cg_1e_2gb	REV05	2GB	128MB	8GB	NA	NA
TE0820-05-3AE81MA	3cg_1e_2gb	REV05	2GB	128MB	8GB	NA	NA
TE0820-05-3BE21MA	3eg_1e_2gb	REV05	2GB	128MB	8GB	NA	NA
TE0820-05-3BE21MAZ	3eg_1e_2gb	REV05	2GB	128MB	8GB	NA	NA
TE0820-05-3BE81MA	3eg_1e_2gb	REV05	2GB	128MB	8GB	NA	NA
TE0820-05-3BE81ML	3eg_1e_2gb	REV05	2GB	128MB	8GB	2.5 mm connectors	Other EMMC mfr
TE0820-05-3BI21ML	3eg_1i_2gb	REV05	2GB	128MB	8GB	2.5 mm connectors	NA
TE0820-05-4AE21MA	4cg_1e_2gb	REV05	2GB	128MB	8GB	NA	NA
TE0820-05-4AE81MA	4cg_1e_2gb	REV05	2GB	128MB	8GB	NA	NA
TE0820-05-4AI21MI	4cg_1i_x_2gb	REV05	2GB	128MB	8GB	without ETH PHY	NA
TE0820-05-4BI21PL	4eg_1i_2gb	REV05	2GB	128MB	64GB	2.5 mm connectors	NA
TE0820-05-4BI21PLZ	4eg_1i_2gb	REV05	2GB	128MB	64GB	2.5 mm connectors	NA
TE0820-05-4DE21MA	4ev_1e_2gb	REV05	2GB	128MB	8GB	NA	Other EMMC mfr
TE0820-05-4DI21MA	4ev_1i_2gb	REV05	2GB	128MB	8GB	NA	Other EMMC mfr
TE0820-05-4DI81MA	4ev_1i_2gb	REV05	2GB	128MB	8GB	NA	Other EMMC mfr
TE0820-05-5DI21MA	5ev_1i_2gb	REV05	2GB	128MB	8GB	NA	NA
TE0820-05-5DI81MA	5ev_1i_2gb	REV05	2GB	128MB	8GB	NA	NA
TE0820-05-S002C1	4cg_1e_2gb	REV05	2GB	128MB	8GB	NA	CAO
TE0820-05-S003	4ev_1e_2gb	REV05	2GB	128MB	8GB	NA	CAO
TE0820-05-S004C1	2eg_1e_2gb	REV05	2GB	128MB	8GB	NA	CAO
TE0820-05-S005	3eg_1e_2gb	REV05	2GB	128MB	8GB	NA	CAO
TE0820-05-S008C1	2eg_1e_2gb	REV05	2GB	128MB	8GB	NA	CAO:without PLL
TE0820-05-S013	2eg_1e_2gb	REV05	2GB	128MB	8GB	NA	CAO:without PLL
TE0820-05-S014C1	4cg_1e_2gb	REV05	2GB	128MB	8GB	NA	CAO
TE0820-05-S016	3eg_1e_2gb	REV05	2GB	128MB	8GB	NA	CAO
TE0820-05-S017C1	2eg_1e_2gb	REV05	2GB	128MB	8GB	NA	CAO:without PLL
TE0820-05-S018	3cg_1e_2gb	REV05	2GB	128MB	8GB	NA	CAO
TE0820-05-S020	3eg_1e_2gb	REV05	2GB	128MB	8GB	NA	CAO
TE0820-05-S022	3cg_1e_2gb	REV05	2GB	128MB	8GB	NA	CAO
TE0820-05-S024C1	2eg_1e_2gb	REV05	2GB	128MB	8GB	NA	CAO

^*used as reference

Design supports following carriers:

Scroll Title

anchor	Table_HWC
title-alignment	center
title	Hardware Carrier

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Carrier Model	Notes
TE0701	Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 SoM Carriers
TE0703*	Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 cm carriers Used as reference carrier.
TE0705	Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 SoM Carriers
TE0706	Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 SoM Carriers
TEB0707	Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 SoM Carriers
TEBA0841	Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 SoM Carriers No SD Slot available, pins goes to Pin Header For TEBA0841 REV01, please contact TE support
TEF1002	Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 SoM Carriers

^*used as reference

Additional HW Requirements:

Scroll Title

anchor	Table_AHW
title-alignment	center
title	Additional Hardware

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Additional Hardware	Notes
USB Cable for JTAG/UART	Check Carrier Board and Programmer for correct type
XMOD Programmer	Carrier Board dependent, only if carrier has no own FTDI
Cooler	It's recommended to use cooler on ZynqMP device

Content

Page properties

hidden	true
id	Comments

Notes :

content of the zip file

For general structure and of the reference design, see Project Delivery - AMD devices

Design Sources

Scroll Title

anchor	Table_DS
title-alignment	center
title	Design sources

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Type	Location	Notes
Vivado	<project folder>\block_design <project folder>\constraints <project folder>\ip_lib <project folder>\board_files	Vivado Project will be generated by TE Scripts
Vitis	<project folder>\sw_lib	Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
PetaLinux	<project folder>\os\petalinux	PetaLinux template with current configuration

Additional Sources

Scroll Title

anchor	Table_ADS
title-alignment	center
title	Additional design sources

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Type	Location	Notes
SI5338	<project folder>\misc\Si5338	SI5338 Project with current PLL Configuration
init.sh	<project folder>\misc\sd\	Additional Initialization Script for Linux

Prebuilt

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hidden	true
id	Comments

Notes :

prebuilt files

Template Table:

Scroll Title

anchor	Table_PF
title-alignment	center
title	Prebuilt files

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

File	File-Extension	Description
BIF-File	*.bif	File with description to generate Bin-File
BIN-File	*.bin	Flash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File	*.bit	FPGA (PL Part) Configuration File
Boot Script-File	*.scr	Distro Boot Script file
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Debian SD-Image	*.img	Debian Image for SD-Card
Diverse Reports	---	Report files in different formats
Hardware-Platform-Description-File	*.xsa	Exported Vivado hardware description file for Vitis and PetaLinux
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
OS-Image	*.ub	Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
SREC-File	*.srec	Converted Software Application for MicroBlaze Processor Systems

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File	File-Extension	Description
BIF-File	*.bif	File with description to generate Bin-File
BIN-File	*.bin	Flash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File	*.bit	FPGA (PL Part) Configuration File
Boot Script-File	*.scr	Distro Boot Script file
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
Hardware-Platform-Description-File	*.xsa	Exported Vivado hardware description file for Vitis and PetaLinux
LabTools Project-File	*.lpr	Vivado Labtools Project File
OS-Image	*.ub	Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems

Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

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Important set new Vivado version link on every Design update of new vivado version!
Set Link to download folder (Remove ../de/.. ../en/.. from url) for example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0712/Reference_Design/2018.2/test_board

Reference Design is available on:

TE0820 "Test Board" Reference Design

Design Flow

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Notes :

Basic Design Steps
Add/ Remove project specific description

Note
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

Launch

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Note:

Programming and Startup procedure

Programming

Note
Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

Note: Depending on CPLD Firmware and Boot Mode settings, QSPI boot with Linux image on SD or complete SD Boot is possible.

Get prebuilt boot binaries

_create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Press 0 and enter to start "Module Selection Guide"
1. Select assembly version
2. Validate selection
3. Select create and open delivery binary folder
  Info
  Note: Folder "<project folder>/_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated

QSPI-Boot mode

Option for Boot.bin on QSPI Flash and image.ub, and boot.scr on SD or USB.

Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Code Block
language py
theme Midnight
title run on Vivado TCL (Script programs BOOT.bin on QSPI flash)
TE::pr_program_flash -swapp u-boot TE::pr_program_flash -swapp hello_te0820 (optional)
Note
To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup
Copy image.ub, and boot.scr on SD or USB
- use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
Set Boot Mode to QSPI-Boot and insert SD or USB.
- Depends on Carrier, see carrier TRM.

SD-Boot mode

Copy image.ub, boot.src and Boot.bin on SD
- use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
- or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
Insert SD-Card in SD-Slot.

JTAG

Not used on this example.

Usage

Prepare HW like described on section Programming
Connect UART USB (most cases same as JTAG)

Select SD Card as Boot Mode (or QSPI - depending on step 1)

Info
Note: See TRM of the Carrier, which is used.

Tip

Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
The boot options described above describe the common boot processes for this hardware; other boot options are possible.
For more information see Distro Boot with Boot.scr

Power On PCB

Expand

title	boot process

1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,

2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,

3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR

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This step depends on Xilinx Device/Hardware

for Zynq-7000 series

1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM,

2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR,

3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR

for ZynqMP???

1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,

2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,

3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR

for Microblaze with Linux

1. FPGA Loads Bitfile from Flash,

2. MCS Firmware configure SI5338 and starts Microblaze, (only if mcs is available)

3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while),

4. U-boot loads Linux from QSPI Flash into DDR

for native FPGA

...

Linux

Open Serial Console (e.g. putty)
- Speed: 115200
- select COM Port
  Info
  Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
Linux Console:
Info
Note: Wait until Linux boot finished

You can use Linux shell now.

Code Block

language	bash
theme	Midnight

i2cdetect -y -r 0	(check I2C 0 Bus)
dmesg | grep rtc	(RTC check)
udhcpc				(ETH0 check)
lsusb				(USB check)

Option Features
- Webserver to get access to Zynq
  - insert IP on web browser to start web interface
- init.sh scripts
  - add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")

Vivado HW Manager

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Note:

Add picture of HW Manager
add notes for the signal either groups or topics, for example:
Control:
- add controllable IOs with short notes..
Monitoring:
- add short notes for signals which will be monitored only
SI5338_CLK0 Counter:
Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.Note: Frequency Counter is inaccurate and displayed unit is Hz

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)

Control:
- User LED (PCB REV03 and newer)
Monitoring:
- SI5338_CLK0 Counter:
  - Set radix from VIO signals to unsigned integer.
    Note: Frequency Counter is inaccurate and displayed unit is Hz
  - SI5338 CLK is configured to 200MHz by default.

PCB REV03 Design:

User LED, see: TE0820 CPLD#LED

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System Design - Vivado

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Note:

Description of Block Design, Constrains... BD Pictures from Export...

Block Design

PCB REV03

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PS Interfaces

Activated interfaces:

Type	Note
DDR
QSPI	MIO
SD0	MIO
SD1	MIO
I2C0	MIO
UART0	MIO
GPIO0	MIO
SWDT0..1
TTC0..3
GEM3	MIO
USB0	MIO, USB2 only

Constrains

Basic module constrains

Code Block

language	ruby
title	_i_bitgen_common.xdc

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design

Design specific constrain

Code Block

language	ruby
title	_i_io.xdc

set_property PACKAGE_PIN K9 [get_ports {SI5338_CLK0_D_clk_p[0]}]
set_property IOSTANDARD LVDS [get_ports {SI5338_CLK0_D_clk_p[0]}]
set_property DIFF_TERM TRUE [get_ports {SI5338_CLK0_D_clk_p[0]}]

set_property PACKAGE_PIN H1 [get_ports {x0[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {x0[0]}]
set_property PACKAGE_PIN J1 [get_ports {x1[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {x1[0]}]

Software Design - Vitis

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Note:

optional chapter separate
sections for different apps

For Vitis project creation, follow instructions from:

Vitis

Application

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----------------------------------------------------------

FPGA Example

----------------------------------------------------------

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2023.2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

Modified Files: blconfig.h, bootloader.c
Changes:
- Add some console outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 2023.2 xilisf_v5_11

Changed default Flash type to 5.

----------------------------------------------------------

Zynq Example:

----------------------------------------------------------

fsbl

TE modified 2023.2 FSBL

General:

Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
Add Files: te_fsbl_hooks.h/.c (for hooks and board)
General Changes:
- Display FSBL Banner and Device ID

Module Specific:

Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY

----------------------------------------------------------

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 2023.2 FSBL

General:

Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
General Changes:
- Display FSBL Banner and Device Name

Module Specific:

Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO

zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

----------------------------------------------------------

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Template location: "<project folder>\sw_lib\sw_apps\"

zynqmp_fsbl

TE modified 2023.2 FSBL

General:

Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
General Changes:
- Display FSBL Banner and Device Name

Module Specific:

Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO

zynqmp_pmufw

Xilinx default PMU firmware.

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Software Design - PetaLinux

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Note:

optional chapter separate
sections for linux
Add "No changes." or "Activate: and add List"

For PetaLinux installation and project creation, follow instructions from:

PetaLinux KICKstart

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

select SD default instead of eMMC:
- CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
add new flash partition for bootscr and sizing
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0_SIZE=0xA00000
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART1_SIZE=0x2000000
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_SIZE=0x40000
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_NAME="bootscr"
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_SIZE=0x80000
Identification
- CONFIG_SUBSYSTEM_HOSTNAME="Trenz"
- CONFIG_SUBSYSTEM_PRODUCT="TE0820"

U-Boot

Start with petalinux-config -c u-boot
Changes:

MAC from eeprom together with uboot and device tree settings:
- CONFIG_ENV_OVERWRITE=y
- CONFIG_NVMEM=y
- CONFIG_DM_RTC=y (needed for nvmem driver because of bug in uboot)
Boot Modes:
- CONFIG_QSPI_BOOT=y
- CONFIG_SD_BOOT=y
- CONFIG_ENV_IS_IN_FAT is not set
- CONFIG_ENV_IS_IN_NAND is not set
- CONFIG_ENV_IS_IN_SPI_FLASH is not set
- CONFIG_BOOT_SCRIPT_OFFSET=0x2A40000
Identification
- CONFIG_IDENT_STRING=" TE0820"

Change platform-top.h:

Code Block

language	js

#include <configs/xilinx_zynqmp.h> #no changes

Device Tree

Code Block

language	js
title	project-spec\meta-user\recipes-bsp\device-tree\files\system-user.dtsi

/include/ "system-conf.dtsi"


/*-------------------- SD0 eMMC ----------------*/
&sdhci0 {
    // disable-wp;
    no-1-8-v;
};


/*-------------------- SD1 sd2.0 ----------------*/
&sdhci1 {
    disable-wp;
    no-1-8-v;
};


/*-------------------- USB 2.0 only ----------------*/
&usb0 {
    status = "okay";
    clock-names = "bus_clk";
    clocks = <&zynqmp_clk USB0_BUS_REF>;
    assigned-clocks = <&zynqmp_clk USB0_BUS_REF>;
};


&dwc3_0 {
    dr_mode = "host";
};
 

/*------------------ ETH PHY --------------------*/
&gem3 {
    //required otherwise petalinux gives a static address here
    /delete-property/ local-mac-address;
    phy-handle = <&phy0>;
    
    nvmem-cells = <&eth0_addr>;
    nvmem-cell-names = "mac-address";
    
    phy0: phy0@1 {
        device_type = "ethernet-phy";
        reg = <1>;
    };
};


/*------------------ QSPI -------------------- */
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
        
        spi-rx-bus-width = <4>;
        spi-tx-bus-width = <4>;
        spi-max-frequency = <90000000>;
    };
};


/*------------------ I2C --------------------*/
&i2c0 {
    eeprom: eeprom@50 {
        compatible = "microchip,24aa025", "atmel,24c02";
        reg = <0x50>;
            
            #address-cells = <1>;
            #size-cells = <1>;
            eth0_addr: eth-mac-addr@FA {
              reg = <0xFA 0x06>;
            };
        };
};

Kernel

Start with petalinux-config -c kernel

Changes:

Only needed to fix JTAG Debug issue:
- CONFIG_CPU_FREQ is not set

Rootfs

Start with petalinux-config -c rootfs

Changes:

for web server app:
- CONFIG_busybox-httpd=y
For additional test tools only:
- CONFIG_i2c-tools=y
- CONFIG_packagegroup-petalinux-utils(util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)
For auto login:
- CONFIG_imagefeature-serial-autologin-root=y

FSBL patch (alternative for vitis fsbl trenz patch)

See "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw"

Petalinux Troubleshoot#Petalinux2023.2

Applications

See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"

startup

Script App to load init.sh from SD Card if available.

webfwu

Webserver application suitable for Zynq access. Need busybox-httpd

Additional Software

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Note:

Add description for other Software, for example SI CLK Builder ...
SI5338 and SI5345 also Link to:
- Si5345
- Si5338

SI5338

File location "<project folder>\misc\Si5338\Si5338-*.slabtimeproj"

General documentation how you work with these project will be available on Si5338

Appx. A: Change History and Legal Notices

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Document Change History

To get content of older revision got to "Change History" of this page and select older document revision number.

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Note this list must be only updated, if the document is online on public doc!
It's semi automatically, so do following
- Add new row below first
- Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template
- Metadata is only used of compatibility of older exports

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Date

Document Revision

Authors

Description

Page info

	modified-date
	modified-date
dateFormat	yyyy-MM-dd

Page info

	current-version
	current-version
prefix	v.

Page info

	modified-user
	modified-user

bugfix file_location.txt
update USB available in uboot

2024-02-23

v.78

Manuela Strücker

2023.2 update
new assembly variants

2024-02-13

v.77

Markus Kirberg

update Release notes and known issues

2023-06-22

v.76

Manuela Strücker

2022.2 update
new assembly variants

2023-03-28

v.75

Manuela Strücker

new assembly variants

2022-09-28

v.74

Manuela Strücker

bugfix fsbl generation
new assembly variants

2022-09-12

v.73

Manuela Strücker

update board part files compatible to Vivado 2021.2.1
new assembly variants

2022-09-06

v.72

Manuela Strücker

new assembly variants

2022-01-26

v.70

John Hartfiel

add missing uboot notes

2022-01-24

v.68

John Hartfiel

Add new delivery design with uboot bugfix

2022-01-21

v.67

John Hartfiel

Add Known issues

2022-01-14

v.66

John Hartfiel

2021.2 release

2021-06-09

v.65

Manuela Strücker

document style update

2021-06-01

v.64

John Hartfiel

2020.2 update
new assembly variants
document style update

2020-05-07

v.62

John Hartfiel

update programming section

2020-04-08

v.61

John Hartfiel

script update
new assembly variants

2020-03-25

v.60

John Hartfiel

script update

2020-01-21

v.59

John Hartfiel

Script update for linux user

2020-01-14

v.58

John Hartfiel

Script update, new features
doc

CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0

Change platform-top.h:

...

language	js

Device Tree

Code Block

language	js

/include/ "system-conf.dtsi"
/ {
  chosen {
    xlnx,eeprom = &eeprom;
  };
};


/* SDIO */

&sdhci1 {
   disable-wp;
   no-1-8-v;
};

/* ETH PHY */
&gem3 {

	status = "okay";
  ethernet_phy0: ethernet-phy@0 {
		compatible = "marvell,88e1510";
		device_type = "ethernet-phy";
    		reg = <1>;
	};
};
/* USB 2.0 */
 
/* USB  */
&dwc3_0 {
    status = "okay";
    dr_mode = "host";
    maximum-speed = "high-speed";
    /delete-property/phy-names;
    /delete-property/phys;
    /delete-property/snps,usb3_lpm_capable;
 	 snps,dis_u2_susphy_quirk;
  	snps,dis_u3_susphy_quirk;
};
   
&usb0 {
    status = "okay";
    /delete-property/ clocks;
    /delete-property/ clock-names;
    clocks = <0x3 0x20>;
    clock-names = "bus_clk";
};




/* QSPI PHY */
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
    };
};

&i2c0 {
  eeprom: eeprom@50 { 
     compatible = "atmel,24c08";
     reg = <0x50>;
  };
};

Kernel

Start with petalinux-config -c kernel

Changes:

CONFIG_CPU_IDLE is not set (only needed to fix JTAG Debug issue)
CONFIG_CPU_FREQ is not set (only needed to fix JTAG Debug issue)
CONFIG_EDAC_CORTEX_ARM64=y

Rootfs

Start with petalinux-config -c rootfs

Changes:

CONFIG_i2c-tools=y
CONFIG_busybox-httpd=y (for web server app)
CONFIG_packagegroup-petalinux-utils(util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)

Applications

startup

Script App to load init.sh from SD Card if available.

See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

webfwu

Webserver application accemble for Zynq access. Need busybox-httpd

Additional Software

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hidden	true
id	Comments

Note:

Add description for other Software, for example SI CLK Builder ...
SI5338 and SI5345 also Link to:
- Si5345
- Si5338

SI5338

File location <design name>/misc/Si5338/Si5338-*.slabtimeproj

General documentation how you work with these project will be available on Si5338

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision got to "Change History" of this page and select older document revision number.

Page properties

hidden	true
id	Comments

Note this list must be only updated, if the document is online on public doc!
It's semi automatically, so do following
- Add new row below first
- Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template
- Metadata is only used of compatibility of older exports

...

anchor	Table_dch
title	Document change history.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
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sortByColumn	1
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...

update
add missing binary files

2019-12-19

v.57

John Hartfiel

2019.2 release

2019-10-29

v.56

John Hartfiel

new assembly variants

2019-08-09

v.55

John Hartfiel

bugfix fsbl

2019-06-19

v.54

John Hartfiel

design changes
new variants

2019-04-01

v.53

John Hartfiel

some notes
renamed ..D variants to ...A

2018-09-21

v.47

John Hartfiel

2018.3 release finished (include design reworks)

2018-10-31

v.43

John Hartfiel

Update Design files for 2GB variants
rebuilt petalinux for optional init script

2018-09-12

v.41

John Hartfiel

Update Design files for 2GB variants

2018-07-11

v.40

John Hartfiel

add notes to ES1

2018-07-06

v.38

John Hartfiel

2018.2 release finished

2018-06-19

v.34

John Hartfiel

Design Files Update

2018-02-13

v.29

John Hartfiel

Design Files Update

2018-02-06

v.27

John Hartfiel

Design Files Update

2018-01-29

v.26

John Hartfiel

Update Known Issues

2018-01-24

v.25

John Hartfiel

Release 2017.4

2018-01-10

v.24

John Hartfiel

Update Known Issues

2017-12-20

v.23

John Hartfiel

Typo correction
Update HW Module Table Description

2017-11-21

v.19

John Hartfiel

Design Update

2017-11-20

v.18

John Hartfiel

Design Update
Add Variants with 128MB Flash

2017-11-13

v.16

John Hartfiel

Update Carrier sections

2017-11-06

v.15

John Hartfiel

Typo corrected

2017-10-23

v.13

John Hartfiel

Update Key Features section
Style Update Additional Software section

2017-10-19

v.9

John Hartfiel

Release 2017.2

2017-09-11

v.1

Page info

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	created-user

Initial release

All

Page info

	modified-users
	modified-users

Legal Notices

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Trenz Electronic Documentation

Page History

Versions Compared

Old Version 58

New Version Current

Key

Overview

Key Features

Revision History

Table of contents

Overview

Key Features

Revision History

Release Notes and Know Issues

Requirements

Software

Hardware

Release Notes and Know Issues

Requirements

Software

Hardware

Content

Design Sources

Additional Sources

Prebuilt

Download

Design Flow

Launch

Programming

Get prebuilt boot binaries

QSPI

SD

JTAG

Usage

Linux

System Design - Vivado

Block Design

PCB REV03

PCB REV01 REV02

PS Interfaces

Constrains

Basic module constrains

Design specific constrain

Software Design - Vitis

Application

zynq_fsbl

zynq_fsbl_flash

zynqmp_fsbl

zynqmp_fsbl_flash

zynqmp_pmufw

hello_te0820

u-boot

zynqmp_fsbl

zynqmp_fsbl_flash

zynqmp_pmufw

hello_te0820

u-boot

Software Design - PetaLinux

Config

U-Boot

Content

Design Sources

Additional Sources

Prebuilt

Download

Design Flow

Launch

Programming

Get prebuilt boot binaries

QSPI-Boot mode

SD-Boot mode

JTAG

Usage

Linux

Vivado HW Manager

System Design - Vivado

Block Design

PCB REV03

PS Interfaces

Constrains