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Custom_table_size_100

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  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"

Template Change history:

DateVersionChangesAuthor

4.1
  • Minor changes
    • Notes
    • Tables
ED

4.0
  • Rework for smaller TRM which can be generated faster
    • Reduce Signal Interfaces Pin
    • Reduce On Board Perihery
    • Reduce Power
    • Move Configuration Signals from Overview to own section
JH

3.12
  • Version History
    • changed from list to table
  • all
    • changed title-alignment for tables from left to center
ma

3.11
  • update "Recommended Operating Conditions" section


3.1
  • New general notes for temperature range to "Recommended Operating Conditions"


3.02
  • add again fix table of content with workaround to use it for pdf and wiki
  • Export Link for key features examples
    • Notes for different Types (with and without Main FPGA)
  • Export Link for Signals, Interfaces and Pins examples
    • Notes for different Types (Modul, Modul Hypride, Evalboard, Carrier)


3.01
  • remove fix table of content and page layout ( split page layout make trouble with pdf export)
  • changed and add note to signal and interfaces, to on board periphery section
  • ...(not finished)


3.00
  • → separation of Carrier/Module and evaluation kit TRM


2.15
  • add excerpt macro to key features


2.14
  • add fix table of content
  • add table size as macro



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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template:

        Scroll Title
        anchorFigure_anchorname
        title-alignmentcenter
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables

      • Scroll Title
        anchorTable_tablename
        title-alignmentcenter
        titleText

        Scroll Table Layout
        orientationportrait
        sortDirectionASC
        repeatTableHeadersdefault
        style
        widths
        sortByColumn1
        sortEnabledfalse
        cellHighlightingtrue

        ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:
        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages
        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview
        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>



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-----------------------------------------------------------------------


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Note for Download Link of the Scroll ignore macro:


Scroll Ignore

Download PDF version of this document.

Overview

The Trenz Electronic TE0817 is an industrial grade MPSoC SOM SoM integrating a Xilinx an AMD Zynq UltraScale+ MPSoC, DDR4 SDRAM with 64-Bit width data bus connection, SPI Boot Flash memory for configuration and operation, transceivers and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking connections in a compact 5.2 cm x 7.6 cm form factor.

Refer to http://trenz.org/te0817-info for the current online version of this manual and other available documentation.

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Notes :

Key Features

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Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

See examples fro different types <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-KeyFeatures


Excerpt
  • SoC
    • Device: ZU4 / ZU5 / ZU7 1)
    • Engine: CG / EG / EV 1)
    • Speedgrade: -1 / -2 / -3 1)
    • Temperature Range: Extended / Industrial 1)
    • Package: FBVB900
  • RAM/Storage
    • 4 GByte DDR4 SDRAM 2)
    • 2 x 64 MByte Serial Flash 3)
    • EEPROM with MAC address
  • On Board
    • Oscillator
  • Interface
    • 4 x B2B Connector (ADM6)
      • up to 204 PL IO

        • HP: 156
        • HD: 48
      • up to 65 PS MIO

      • 4 GTR
      • 16 GTH
      • I2C, JTAG
  • Power
    • 3.3 V power Power supply via B2B Connector needed 4).
  • Dimension
    • 76 mm x 52 mm
  • Notes
    1) Please, take care of the possible assembly options. Furthermore, check whether the power supply is powerful enough for your FPGA design.
    2) Up to 32 8 GByte are possible with a maximum bandwidth of 2400 MBit/s.
    3) Please, take care of the possible assembly options.
    4) Dependant on the assembly option a higher input voltage may be possible.

Block Diagram

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add drawIO object in Scroll Ignore section and add reference image in Scroll Only.

Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


Note

Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name.

Example: TE0812 Block Diagram


Note

All created DrawIOs  should be named according to the Module name:

Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD



Scroll Title
anchorFigure_OV_BD
title-alignmentcenter
titleTE0813 TE0817 block diagram


Scroll Ignore

draw.io Diagram
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diagramNameTE0817_OV_BD
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Scroll Only


Main Components

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Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


Note

For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .



Scroll Title
anchorFigure_OV_MC
title-alignmentcenter
titleTE0813 TE0817 main components


Scroll Ignore

draw.io Diagram
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diagramNameFigure_OV_MC
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revision37



Scroll Only

Image RemovedImage Added


  1. SoC, U1
  2. DDR4, U2, U3, U9, U12
  3. Quad SPI Flash, U7, U17
  4. Connector, J1, J2, J3, J4
  5. EEPROM, U11
  6. Clock Generator, U5
  7. Oscillator, U25, U32Power Supply, U4, U6, U8, U10, U13 ... U15, U18 ... U24, U26 ... U31, U34, U38

Initial Delivery State

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Note

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty



Scroll Title
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titleInitial delivery state of programmable devices on the module

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Storage device name

Content

Notes

DDR4 SDRAMnot programmed
Quad SPI Flashnot programmed
EEPROMnot programmed besides factory programmed MAC address
Programmable Clock Generatornot programmed


Signals, Interfaces and Pins

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For subsection examples see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-Signals,InterfacesandPins

Note
  • Table with all connectors and Designator
  • List of different interfaces per connector
  • IO CNT (for FPGA IOs where functionality can be changed by customer)


Connectors

Scroll Title
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Connector TypeDesignatorInterfaceIO CNT 1)Notes
B2BJM1J1MGT PL4 12 x MGT (RX/TX)
B2BJM1J1HP52 SE / 24 DIFF
B2BJM2J2MGT PS2 x MGT CLK
B2BJ2CLKDIFF CLK
B2BJ2MGT PL4 x MGT (RX/TX)
B2BJM2J2MGT PS4 x MGT (RX/TX)
B2BJM2J2CFGJTAG
B2BJM2J2CFGMODE
B2BJM3J3HD48 SE / 24 DIFF
B2BJM3J3MGT PL3 x MGT CLK
B2BJ3CLKDIFF CLK
B2BJM3J3MIO65 GPIO
B2BJM4J4HP104 SE / 48 DIFF

1) IO CNT depends on assembly variant. E.g. the MGTs are not available for all FPGAs


Test Points

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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.

Example:

Test PointSignalNotes1)
TP1PWR_PL_OK

1) Direction:

    • IN: Input from the point of view of this board.
    • OUT: Output from the point of view of this board.



Scroll Title
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PointNotes1 PS PSPL_1V8GNDGNDPL_VCCINT_IOGNDPLVCCINTVCU_0V9TP18DDR1V2MGTAVTTVTTPLGT_1V05VREFAMGTVCCAUXMGTAVCCLP0V85AUXPSAVCCTP34
Test Point 1)SignalNotes 2)
TP1PLL_SCLpulled-up to SI_PLL_1V8
TP2PLL_SDApulled-up to SI_PLL_1V8
TP3DDR4-TENpulled-down to GND
TP4VTT
TP5GND
TP6TCK
TP7TDI
TP8TDO
TP9TMS
TP10LP_0V85
TP11FP_0V85
TP12PL_VCCINT
TP13FPPS_0V85PLL
TP14PS_GT_1V81V0
TP15GNDFP_0V85
TP16DDR_2V5
TP17DCDC_2V0
TP18DDR_PLL
TP19PS_GT_1V0
TP20PL_VCU
TP21PS_AUX
TP22PS_AVCC
TP23VTT
TP24AUX_R
TP25AVTT_R
TP26AVCC_R
TP27PS_PLL
TP28PS_AVTT
TP29PS_AUX
TP30PS_AVCC
TP31LP_0V85
TP32POR_Bpulled-up to PS_1V8

1) Direction:

    • IN: Input from the point of view of this board.
    • OUT: Output from the point of view of this board.

On-board Peripherals

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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection

Example:

GND
TP33PS_AVTT
TP34DDR_PLL
TP35DDR_2V5
TP36VREFA
TP37VREFA
TP383.3VIN
TP39LP_DCDC
TP40PL_VCCINT
TP41DCDCIN
TP42DCDC_2V0
TP43PL_DCIN
TP44PL_GT_1V45
TP45PL_GT_1V45
TP46GT_DCDC
TP47PL_GT_1V15
TP48PL_GT_1V15
TP49PLL_3V3
TP50AUX_R
TP51PSBATT
TP52AVCC_R
TP53AVTT_R
TP54VCCO_47
TP55PL_VCU
TP56VCCO_48
TP571V8_REFIN
TP581V8_REFIN
TP59VCCO_64
TP601V25_REF
TP611V25_REF
TP62VCCO_65
TP63VCCO_66
TP64PLL_VDDA
TP65PLL_VDDA
TP66PLL_VDD
TP67PLL_VDD
TP68PS_1V8
TP69PL_1V8
TP70SI_PLL_1V8
TP71SI_PLL_1V8
TP72DDR4_1V2

1) Test points depend on revision: Not all testpoints are available for all revisions.

2) Direction:

    • IN: Input from the point of view of this board.
    • OUT: Output from the point of view of this board.


On-board Peripherals

Chip/InterfaceDesignatorConnected ToNotesETH PHYU10
  • B2B connector J1
  • SoC MIO
Gigabit ETH PHY Scroll Title
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titleOn board peripherals
Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueChip/InterfaceDesignatorConnected ToNotes

DDR4 SDRAM

U2, U3, U9, U12SoC - PS

Quad SPI Flash

U7, U17SoC - PSBooting.

EEPROM

U28B2B - J2

Clock Generator

U5SoC, B2B

Oscillator

U6Clock Generator25 MHz

Oscillator

U32SoC33.333333 MHz
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For example subsections see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-On-boardPeripherals

Configuration and System Control Signals

AnchorConfiguration and System Control SignalsConfiguration and System Control Signals
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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection

Example:

Chip/InterfaceDesignatorConnected ToNotes
ETH PHYU10
  • B2B connector J1
  • SoC MIO
Gigabit ETH PHY
  • Overview  all Controller signals, like Reset, Boote Mode, JTAG Interface(Connector or USB In case of FTDI)...
  • In case it's connected to CPLD always link to CPLD description and add not from the  current implementation here(in case it's available)



    1) Direction:

      • IN: Input from the point of view of this board.
      • OUT: Output from the point of view of this board.

    2) See UG1085 for additional information.

    3) See Recommended Operating Conditions.

    Scroll Title
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    titleController signal.On board peripherals

    Scroll Table Layout
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    Connector+Pin

    Signal Name

    Direction1)Description
    JM1.A45POR_OVERRIDEINOverride power-on reset delay 2).
    JM2.A31ERR_OUTOUTPS error indication 2).
    JM2.A34ERR_STATUSOUTPS error status 2).
    JM2.A35LP_GOODOUTLow-power domain powered-up. Pulled up to 3.3VIN
    JM2.A36PLL_SCLINI2C clock
    JM2.A37PLL_SDAIN/OUTI2C data
    JM2.A40PG_VCUOUTProgrammable logic powered-up.
    JM2.A41EN_PSGTINEnable GTR transceiver power-up.
    JM2.A44 / JM2.A45 /
    JM2.A46 / JM2.A47
    TCK / TDI / TDO / TMSSignal-dependent

    JTAG configuration and debugging interface.

    JTAG reference voltage: PS_1V8

    JM2.B29PG_PSGTOUTGTR transceivers powered-up.
    JM2.B30PROG_BIN/OUTPower-on reset 2). Pulled-up to PS_1V8.
    JM2.B33SRST_BINSystem reset 2). Pulled-up to PS_1V8.
    JM2.B34INIT_BIN/OUTInitialization completion indicator after POR 2). Pulled-up to PS_1V8.
    JM2.B37PG_PLOUTVCU powered-up.
    JM2.B38EN_FPDINEnable full-power domain power-up.
    JM2.B41PG_FPDOUTFull-power domain powered-up.
    JM2.B45PG_DDROUTDDR power supply powered-up.
    JM2.B46DONEOUTPS done signal 2). Pulled-up to PS_1V8.
    JM2.B47EN_DDRINEnable DDR power-up.
    JM2.C31MRINManual reset.
    JM2.C35EN_PLINEnable programable logic power-up.
    JM2.C36EN_GT_RINEnable GTH/GTY transceiver power-up.
    JM2.C44 / JM2.C45 / JM2.C46 / JM2.C47MODE3..0INBoot mode selection 2):
    • JTAG
    • QUAD-SPI (32 Bit)
    • SD1 (2.0)
    • eMMC (1.8 V)
    • SD1 LS (3.0)

    Supported Modes depends also on used Carrier.

    JM2.D33PG_GT_ROUTGTH/GTY Transceivers powered-up.
    JM2.D37PSBATTINPS RTC Battery supply voltage 2) 3).
    JM2.D45 / JM2.D46DX_P / DX_N-SoC temperatur sensing diode pins 2).

    Power and Power-On Sequence

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    Enter the default value for power supply and startup of the module here.

    • Order of power provided Voltages and Reset/Enable signals

    Link to Schematics, for power images or more details

    Power Rails

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    List of all Powerrails which are accessible by the customer

    • Main Power Rails and Variable Bank Power
    Scroll Title
    anchorTable_PWR_PR
    title-alignmentcenter
    titleModule power rails.
    Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtruePower Rail Name/ Schematic NameConnector.PinDirection1)Notes
    Chip/InterfaceDesignatorConnected ToNotes

    DDR4 SDRAM

    U2, U3, U9, U12SoC - PS

    Quad SPI Flash

    U7, U17SoC - PSBooting.

    EEPROM

    U11B2B - J2

    Clock Generator

    U5SoC, B2B

    Oscillator

    U25Clock Generator25 MHz

    Oscillator

    U32SoC33.333333 MHz



    Page properties
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    For example subsections see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-On-boardPeripherals

    Configuration and System Control Signals

    Anchor
    Configuration and System Control Signals
    Configuration and System Control Signals

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    • Overview  all Controller signals, like Reset, Boote Mode, JTAG Interface(Connector or USB In case of FTDI)...
    • In case it's connected to CPLD always link to CPLD description and add not from the  current implementation here(in case it's available)


    Scroll Title
    anchorTable_OV_CNTRL
    title-alignmentcenter
    titleController signal.

    Scroll Table Layout
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    sortEnabledfalse
    cellHighlightingtrue

    Connector+Pin

    Signal Name

    Direction1)Description
    J1.A45POR_OVERRIDEINOverride power-on reset delay 2).
    J2.A30PG_PLL_1V8OUTSI_PLL_1V8 power rail powered-up.
    J2.A31ERR_OUTOUTPS error indication 2).
    J2.A34ERR_STATUSOUTPS error status 2).
    J2.A35LP_GOODOUTLow-power domain powered-up. Pulled up to 3.3VIN.
    J2.A36PLL_SCLINI2C clock
    J2.A37PLL_SDAIN/OUTI2C data
    J2.A40PG_VCUOUTVCU power rail powered-up.
    J2.A41EN_PSGTINEnable GTR transceiver power-up.
    J2.A44 / J2.A45 /
    J2.A46 / J2.A47
    TCK / TDI / TDO / TMSSignal-dependent

    JTAG configuration and debugging interface.

    JTAG reference voltage: PS_1V8

    J2.B29PG_PSGTOUTGTR transceivers powered-up.
    J2.B30PROG_BIN/OUTPower-on reset 2). Pulled-up to PS_1V8.
    J2.B33SRST_BINSystem reset 2). Pulled-up to PS_1V8.
    J2.B34INIT_BIN/OUTInitialization completion indicator after POR 2). Pulled-up to PS_1V8.
    J2.B37PG_PLOUTProgrammable logic powered-up.
    J2.B38EN_FPDINEnable full-power domain power-up.
    J2.B41PG_FPDOUTFull-power domain powered-up.
    J2.B42EN_LPDINEnable low-power domain power-up.
    J2.B45PG_DDROUTDDR power supply powered-up.
    J2.B46DONEOUTPS done signal 2). Pulled-up to PS_1V8.
    J2.B47EN_DDRINEnable DDR power-up.
    J2.C30EN_GT_LINNot connected.
    J2.C31MRINManual reset.
    J2.C32PLL_SEL0INPLL clock selection.
    J2.C33PLL_RSTINPLL reset.
    J2.C35EN_PLINEnable programable logic power-up.
    J2.C36EN_GT_RINEnable GTH transceiver power-up.
    J2.C37PLL_FDECINPLL Frequency decrementation.
    J2.C44 / J2.C45 / J2.C46 / J2.C47MODE3..0INBoot mode selection 2):
    • JTAG
    • QUAD-SPI (32 Bit)
    • SD1 (2.0)
    • eMMC (1.8 V)
    • SD1 LS (3.0)

    Supported Modes depends also on used Carrier.

    J2.D29EN_PLL_PWRINEnable PLL power supply.
    J2.D30PLL_FINCINPLL Frequency incrementation.
    J2.D31PLL_LOLnOUTLoss of lock status.
    J2.D32PLL_SEL1INPLL clock selection.
    J2.D33PG_GT_ROUTGTH Transceivers powered-up.
    J2.D37PSBATTINPS RTC Battery supply voltage 2) 3).
    J2.D38PUDC_BINConfiguration pull-ups setting 2). Pulled-up to PL_1V8.
    J2.D45 / J2.D46DX_P / DX_N-SoC temperatur sensing diode pins 2).

    1) Direction:

      • IN: Input from the point of view of this board.
      • OUT: Output from the point of view of this board.

    2) See UG1085 for additional information.

    3) See Recommended Operating Conditions.

    Power and Power-On Sequence

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    Enter the default value for power supply and startup of the module here.

    • Order of power provided Voltages and Reset/Enable signals

    Link to Schematics, for power images or more details


    Power Rails

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    List of all Powerrails which are accessible by the customer

    • Main Power Rails and Variable Bank Power



    Scroll Title
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    title-alignmentcenter
    titleModule power rails.

    Scroll Table Layout
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    Power Rail Name/ Schematic NameConnector.PinDirection1)Notes
    VCCO_66J1.A32 / J1.A33IN
    VREF_66J1.A41IN
    3.3VINJ1.A54 / J1.A55 / J1.B55 / J1.B56IN

    PL_1V8

    J1.C32 / J1.C33 / J1.D33 / J1.D34OUT
    PL_DCINJ1.C56 / J1.C57 / J1.C58 / J1.C59 / J1.C60 / J1.D56 / J1.D57 / J1.D58 / J1.D59 / J1.D60IN
    LP_DCDCJ2.A50 / J2.A51 / J2.A52 / J2.B50 / J2.B51 / J2.B52 / J2.C50 / J2.C51 / J2.C52 / J2.D50 / J2.D51 / J2.D52IN
    DCDCINJ2.A57 / J2.A58 / J2.A59 / J2.A60 / J2.B57 / J2.B58 / J2.B59 / J2.B60 / J2.C57 / J2.C58 / J2.C59 / J2.C60 / J2.D57 / J2.D58 / J2.D59 / J2.D60 / IN
    PS_BATTJ2.D37IN
    DDR_1V2J2.D47OUT
    PS_1V8J2.C34 / J2.D34 / J3.A56 / J3.B56 / J3.C56 / J3.D56OUT
    PLL_3V3J3.A55IN
    GT_DCDCJ3.A59 / J3.A60 / J3.B59 / J3.B60 / J3.C59 / J3.C60 / J3.D59 / J3.D60 /IN
    VCCO_48J3.C7 / J3.C8 / J3.D8 / J3.D9IN
    VCCO_47J3.C19 / J3.C20 / J3.D20 / J3.D21IN
    VCCO_64J4.B21 / J4.B39IN
    VREF_64J4.B30IN
    VCCO_65J4.C21 / J4.C39IN
    VREF_65J4.C30IN

    1) Direction:

      • IN: Input from the point of view of this board.
      • OUT: Output from the point of view of this board.


    Recommended Power up Sequencing

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    idComments

    List baseboard design hints for final baseboard development.

    The power up sequencing highly depends on the use case. In general, it should be possible to enable/disable the processing system (PS) / programmable logic (PL) independently. Furthermore, within the processing logic it should be possible to enable/disable only low-power domain and/or low-power and full-power domain. Additionally, usage of GTR for PS side and GTH for PL side should be possible. Because of this flexibility the needed parts of the following table needs to be selected individually. For detailed information take a look into schematics.

    Scroll Title
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    SequenceNet nameRecommended Voltage RangePull-up/downDescriptionNotes
    0---Configuration signal setup.See Configuration and System Control Signals.
    1 1)PSBATT1.2 V ... 1.5 V-Battery connection.Battery Power Domain usage. When not used, tie to GND.
    13.3VIN3.3 V (± 5 %)-Management power supply.Management module power supply. 0.5 A recommended.
    GTH / GTR Transceiver clocking (Only necessary in cases where the PLL clock is used for GTH / GTH.):
    1 1)GT_DCDC3.3 V (± 3 %) 2)
    GTH transceiver power supply.Main module power supply for GTH / GTY transceiver. 5
    VCCO_66JM1.A32 / JM1.A33INVREF_66JM1.A41IN3.3VINJM1.A54 / JM1.A55 / JM1.B55 / JM1.B56IN

    PL_1V8

    JM1.C32 / JM1.C33 / JM1.D33 / JM1.D34OUTPL_DCINJM1.C57 / JM1.C58 / JM1.C59 / JM1.C60 / JM1.D57 / JM1.D58 / JM1.D59 / JM1.D60 / INLP_DCDCJM2.A50 / JM2.A51 / JM2.A52 / JM2.B50 / JM2.B51 / JM2.B52 / JM2.C50 / JM2.C51 / JM2.C52 / JM2.D50 / JM2.D51 / JM2.D52INDCDCINJM2.A57 / JM2.A58 / JM2.A59 / JM2.A60 / JM2.B57 / JM2.B58 / JM2.B59 / JM2.B60 / JM2.C57 / JM2.C58 / JM2.C59 / JM2.C60 / JM2.D57 / JM2.D58 / JM2.D59 / JM2.D60 / INPS_BATTJM2.D37INDDR_1V2JM2.D47OUTPS_1V8JM3.A56 / JM3.B56 / JM3.C56 / JM3.D56OUTGT_DCDCJM3.A59 / JM3.A60 / JM3.B59 / JM3.B60 / JM3.C59 / JM3.C60 / JM3.D59 / JM3.D60 /INVCCO_25JM3.C7 / JM3.C8 / JM3.D8 / JM3.D9INVCCO_26JM3.C19 / JM3.C20 / JM3.D20 / JM3.D21INVCCO_64JM4.B21 / JM4.B39INVREF_64JM4.B30INVCCO_65JM4.C21 / JM4.C39INVREF_65JM4.C30IN

    1) Direction:

      • IN: Input from the point of view of this board.
      • OUT: Output from the point of view of this board.

    Recommended Power up Sequencing

    Page properties
    hiddentrue
    idComments

    List baseboard design hints for final baseboard development.

    The power up sequencing highly depends on the use case. In general, it should be possible to enable/disable the processing system (PS) / programmable logic (PL) independently. Furthermore, within the processing logic it should be possible to enable/disable only low-power domain and/or low-power and full-power domain. Additionally, usage of GTR for PS side and GTH/GTY for PL side should be possible. Because of this flexibility the needed parts of the following table needs to be selected individually. For detailed information take a look into schematics.

    Scroll Title
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    Main module power supply for programmable logic. 12 2.2PLPU 4 3.3 VProgrammable logic 2.3PL4Programmable logic GT 5 3GTH / GTY transceiver GTH / GTY transceiver. 3 3PGGT_R4GTH / GTY transceiver
    SequenceNet nameRecommended Voltage RangePull-up/downDescriptionNotes
    0---Configuration signal setup.See Configuration and System Control Signals.
    1 1)PSBATT1.2 V ... 1.5 V-Battery connection.Battery Power Domain usage. When not used, tie to GND.
    1 2)3.3VIN3.3 V (± 5 %)-Management power supply.Management module power supply. 0.5 A recommended. Consider note 2) for modules with VCU and/or low-power SoC.
    2Processing System (PS):Procedure for PS starting.2.1Low-power domain:Bring-up for low-power domain PS.
    2.1.1LP_DCDC3.3 V (± 5 %) 3)-Low-power domain power supply.Main module power supply for low-power domain. 5.5 A recommended. Power consumption depends mainly on design and cooling solution.
    2.1.2EN_LPD-PU 4), 3.3 VLow-power domain power enable.
    2.1.3LP_GOOD-PU 4), 3.3 VLow-power domain power good status.Module power-on sequencing for low-power domain finished.
    2.2Full-power domain:Bring-up for full-power domain PS.Full-power PS domain needs powered low-power PS domain.
    2.2.1DCDCIN3.3 V (± 5 %) 3)Full-power domainand GTR transceiver power supply.Main module power supply for full-power domain. 7 A recommended. Power consumption depends mainly on design and cooling solution.2.2.2EN_FPD3.3 V-Full-power domain power enable.
    2.2.3PG_FPD-PU 4), 3.3 VFull-power domain power good status.Module power-on sequencing for full-power domain finished.
    2.2.4EN_DDR3.3 V-DDR memory power enable.2.2.5PG_DDRPU 4), 3.3 VDDR memory power good status.Module power-on sequencing for DDR memory finished.

    2.3

    GTR TransceiverProcedure for GTR transceiver starting.PS transceiver usage needs powered PS (low- and full-power domain).
    2.3.1EN_PSGT3.3 V-GTR transceiver power enable.
    2.3.2PG_PSGT-PU 4), 3.3 VGTR transceiver power good status.Module power-on sequencing for GTR transceiver finished.
    2Programmable Logic (PL)Procedure for PL starting.PS and PL can be started independently.
    2.1PL_DCIN3.3 V (± 5 %) 3) 5)-Programmable logic power supply. A recommended. Power consumption depends mainly on design and cooling solution.
    1 1)EN_PLL_PWR-PD 3), GNDPLL power enable.
    1 1)PG_PLL_1V8-PU 3), 3.3 VPLL power good status.Module power-on sequencing for programmable logic finished. Periphery and variable bank voltages can be enabled on carrier.
    2.4VCCO_25 / VCCO_26 / VCCO_64 / VCCO_65 / VCCO_66 6)-Module bank voltages.Enable bank voltages after PG_PL deassertion.
    2.5PG_VCU-PU 4), 3.3 VVCU power good status.

    2Processing System (PS):Procedure for PS starting.
    2.1Low-power domain:Bring-up for low-power domain PS.
    2.1.1LP
    3GTH / GTY TransceiverProcedure for GTH / GTY transceiver starting.PL transceiver usage needs powered PL and low-power PS domain.
    3.1_DCDC3.3 V (± 3 %) 2)-Low-power domain power supply.Main module power supply for low-power domain. 5.5 A recommended. Power consumption depends mainly on design and cooling solution.
    32.1.2EN_GT_RLPD-PU 3), 33.3 V-GTH / GTY transceiver Low-power domain power enable.
    2.1.3LP_GOOD-PU 3), 3.3 VLow-power domain power good status.

    1) (optional)

    2) On TE0813 REV01 boards it is necessary for modules with VCU and/or low-power speedgrade to either connect signal EN_PL to voltage 3.3VIN or to enable EN_PL together with 3.3VIN. This should be changed in a newer revision.

    3) Dependent on the assembly option a higher input voltage may be possible. 

    4) (on module)

    5) This value depends highly on DCDC U4. Higher values may be possible with different DCDCs. For more information consult schematic and according datasheets.

    6) See DS925 for additional information.

    Board to Board Connectors

    Page properties
    hiddentrue
    idComments
  • This section is optional and only for modules.
  • Module power-on sequencing for low-power domain finished.
    2.2Full-power domain:Bring-up for full-power domain PS.Full-power PS domain needs powered low-power PS domain.
    2.2.1DCDCIN3.3 V (± 5 %) 2)
    Full-power domainand GTR transceiver power supply.Main module power supply for full-power domain. 7 A recommended. Power consumption depends mainly on design and cooling solution.
    2.2.2EN_FPD3.3 V-Full-power domain power enable.
    2.2.3PG_FPD-PU 3), 3.3 VFull-power domain power good status.Module power-on sequencing for full-power domain finished.
    2.2.4EN_DDR3.3 V-DDR memory power enable.
    2.2.5PG_DDR
    PU 3), 3.3 VDDR memory power good status.Module power-on sequencing for DDR memory finished.

    2.3

    GTR TransceiverProcedure for GTR transceiver starting.PS transceiver usage needs powered PS (low- and full-power domain).
    2.3.1EN_PSGT3.3 V-GTR transceiver power enable.
    2.3.2PG_PSGT-PU 3), 3.3 VGTR transceiver power good status.Module power-on sequencing for GTR transceiver finished.
    2Programmable Logic (PL)Procedure for PL starting.PS and PL can be started independently.
    2.1PL_DCIN3.3 V (± 5 %) 2) 4)-Programmable logic power supply.Main module power supply for programmable logic. 12 A recommended. Power consumption depends mainly on design and cooling solution.
    2.2EN_PL-PU 3), 3.3 VProgrammable logic power enable.
    2.3PG_PL-PU 3), 3.3 VProgrammable logic power good status.Module power-on sequencing for programmable logic finished. Periphery and variable bank voltages can be enabled on carrier.
    2.4VCCO_47 / VCCO_48 / VCCO_64 / VCCO_65 / VCCO_66 5)-Module bank voltages.Enable bank voltages after PG_PL deassertion.
    2.5PG_VCU-PU 3), 3.3 VVCU power good status.
    3GTH / GTY TransceiverProcedure for GTH / GTY transceiver starting.PL transceiver usage needs powered PL and low-power PS domain.
    3.1GT_DCDC3.3 V (± 3 %) 2)-GTH transceiver power supply.Main module power supply for GTH transceiver. 5 A recommended. Power consumption depends mainly on design and cooling solution.
    3.2EN_GT_R3.3 V-GTH / GTY transceiver power enable.
    3.3PG_GT_R-PU 3), 3.3 VGTH / GTY transceiver power good status.

    1) (optional)

    2) Dependent on the assembly option a higher input voltage may be possible. 

    3) (on module)

    4

    use "include page" macro and link to the general B2B connector page of the module series,

    For example: 6 x 6 SoM LSHM B2B Connectors
    Include PagePD:6 x 6 SoM LSHM B2B ConnectorsPD:6 x 6 SoM LSHM B2B Connectors Include PagePD:5.2 x 7.6 UltraSoM+ ADF6 and ADM6 B2B ConnectorsPD:5.2 x 7.6 UltraSoM+ ADF6 and ADM6 B2B Connectors

    Technical Specifications

    Page properties
    hiddentrue
    idComments

    List of all Powerrails which are accessible by the customer

    • Main Power Rails and Variable Bank Power add boarder one time maximum Rating (Board will damaged)

    Absolute Maximum Ratings *)

    1) This value depends highly on DCDC U4. Higher values are may be possible with different DCDCs. For more information consult schematic and according datasheets.

    Scroll Title
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    Power Rail Name/ Schematic NameDescriptionMinMaxUnit
    LP_DCDCMicromodule Power-0.3006.0V
    DCDCINMicromodule Power-0.3007.0V
    GT_DCDCMicromodule Power-0.3006.0V
    PL_DCIN 1)Micromodule Power-0.300

    4.0

    V
    3.3VINMicromodule Power-0.3003.600V
    PS_BATTRTC / BBRAM-0.5002.000V
    VCCO_25HD IO Bank power supply-0.5002.000V
    VCCO_26HD IO Bank power supply-0.5002.000V
    VCCO_64HP IO Bank power supply-0.5003.400V

    VCCO_65

    HP IO Bank power supply-0.5003.400V
    VCCO_66HP IO Bank power supply-0.5003.400V
    VREF_64Bank input reference voltage-0.5002.000V
    VREF_65Bank input reference voltage-0.5002.000V
    VREF_66Bank input reference voltage-0.5002.000V

    *) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
       or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

    Recommended Operating Conditions

    This TRM is generic for all variants. Temperature range can be different depending on assembly version.  Voltage range is mostly the same during variants (exceptions are possible, depending on custom request)

    Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

    • Variants of modules are described here: Article Number Information
    • Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C
    • Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
    • Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C
    • The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.

    5) See DS925 for additional information.

    Board to Board Connectors

    Page properties
    hiddentrue
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    • This section is optional and only for modules.
    • use "include page" macro and link to the general B2B connector page of the module series,

      For example: 6 x 6 SoM LSHM B2B Connectors

      Include Page
      6 x 6 SoM LSHM B2B Connectors
      6 x 6 SoM LSHM B2B Connectors

    Include Page
    5.2 x 7.6 UltraSoM+ ADF6 and ADM6 B2B Connectors
    5.2 x 7.6 UltraSoM+ ADF6 and ADM6 B2B Connectors

    Technical Specifications

    Page properties
    hiddentrue
    idComments

    List of all Powerrails which are accessible by the customer

    • Main Power Rails and Variable Bank Power add boarder one time maximum Rating (Board will damaged)

    Absolute Maximum Ratings *)

    Reference Document
    Scroll Title
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    Scroll Title
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    Power Rail Name/ Schematic NameDescription
    Parameter
    MinMax
    Units
    Unit
    LP_DCDC
    1)3.1353.465
    Micromodule Power-0.3006.0V
    DCDCIN
    1)3.135
    Micromodule Power-0.3007.0
    3.465
    V
    GT_DCDC
    1)3.135
    Micromodule Power-0.3006.0
    3.465
    V
    PL_DCIN 1)
    2)3.135
    Micromodule Power-0.300

    7.0

    3.465

    V
    3.3VINMicromodule Power
    3
    -0.
    135
    3003.
    465
    600V
    PS_BATT1.21.5VSee FPGA datasheet.VCCO_251.1643.399VSee FPGA datasheet.VCCO_261.1643.399VSee FPGA datasheet.VCCO_640.971.854VSee FPGA datasheet.

    VCCO_65

    0.971.854VSee FPGA datasheet.VCCO_660.971.854VSee FPGA datasheet.VREF_640.61.2VSee FPGA datasheet.VREF_650.61.2VSee FPGA datasheet.VREF_660.61.2VSee FPGA datasheet.

    1) Dependent on the assembly option a higher input voltage may be possible. 

    PLL_3V3PLL power supply-0.5003.8V
    PS_BATTRTC / BBRAM-0.5002.000V
    VCCO_47HD IO Bank power supply-0.5003.400V
    VCCO_48HD IO Bank power supply-0.5003.400V
    VCCO_64HP IO Bank power supply-0.5002.000V

    VCCO_65

    HP IO Bank power supply-0.5002.000V
    VCCO_66HP IO Bank power supply-0.5002.000V
    VREF_64Bank input reference voltage-0.5002.000V
    VREF_65Bank input reference voltage-0.5002.000V
    VREF_66Bank input reference voltage-0.5002.000V

    1) For REV01 use max. 4 V instead which 2) This value depends highly on DCDC U4. Higher values may are possible with different DCDCs. For more information consult schematic and according datasheets.

    Physical Dimensions

    • Module size: 76 mm × 52 mm.  Please download the assembly diagram for exact numbers.

    • Mating height with standard connectors: 5 mm.

    PCB thickness: 1.74 mm (± 10 %).

    *) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
       or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

    Recommended Operating Conditions

    This TRM is generic for all variants. Temperature range can be different depending on assembly version.  Voltage range is mostly the same during variants (exceptions are possible, depending on custom request)

    Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

    • Variants of modules are described here: Article Number Information
    • Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C
    • Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
    • Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C
    • The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.


    In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

    For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

    https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

    Scroll Title
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    Note

    For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

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    title-alignmentcenter
    titlePhysical DimensionRecommended operating conditions.

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    Image Removed

    Currently Offered Variants 

    Page properties
    hiddentrue
    idComments

    Set correct link to the shop page overview table of the product on English and German.

    Example for TE0706:

        ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0813

        DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0813

    Scroll Title
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    title-alignmentcenter
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    Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueTrenz shop TE0813 overview pageEnglish pageGerman page

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    ParameterMinMaxUnitsReference Document
    LP_DCDC 1)3.2013.399V
    DCDCIN 1)3.1353.465V
    GT_DCDC 1)3.2013.399V
    PL_DCIN 1) 2)3.135

    3.465

    V
    3.3VIN3.1353.465V
    PLL_3V33.1353.465V
    PS_BATT1.21.5VSee FPGA datasheet.
    VCCO_471.1643.399VSee FPGA datasheet.
    VCCO_481.1643.399VSee FPGA datasheet.
    VCCO_640.971.854VSee FPGA datasheet.

    VCCO_65

    0.971.854VSee FPGA datasheet.
    VCCO_660.971.854VSee FPGA datasheet.
    VREF_640.61.2VSee FPGA datasheet.
    VREF_650.61.2VSee FPGA datasheet.
    VREF_660.61.2VSee FPGA datasheet.

    1) Dependent on the assembly option a higher input voltage may be possible. 

    2) This value depends highly on REV01 DCDC U4. Higher values may possible with different DCDCs or different revision. For more information consult schematic and according datasheets.


    Physical Dimensions

    • Module size: 76 mm × 52 mm.  Please download the assembly diagram for exact numbers.

    • Mating height with standard connectors: 5 mm.

    PCB thickness: 1.74 mm (± 10 %).

    Page properties
    hiddentrue
    idComments

    In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

    For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

    https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

    Note

    For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .



    Scroll Title
    anchorFigure_TS_PD

    Revision History

    Hardware Revision History

    Set correct links to download  Carrier, e.g. TE0706 REV02:

      TE0706-02  ->   https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

    Note:

  • Date format:  YYYY-MM-DD
  • Example: 

    Page properties
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    DateRevisionChangesDocumentation Link
    2020-11-25REV02
    • Resistors R14 and R15 was replaced by 953R (was 5K1)
    • Resistor R5 was replaced by 5K1, R8 by 953R (was 9K09 and 1K69 respectively)
    REV02
    Scroll Title
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    Image Added


    Currently Offered Variants 

    Page properties
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    Set correct link to the shop page overview table of the product on English and German.

    Example for TE0706:

        ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0813

        DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0813


    Scroll Title
    anchorTable_VCP_SO
    title-alignmentcenter
    titleTrenz Electronic Shop Overview

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
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    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Trenz shop TE0817 overview page
    English pageGerman page


    Revision History

    Hardware Revision History

    Page properties
    hiddentrue
    idComments

    Set correct links to download  Carrier, e.g. TE0706 REV02:

      TE0706-02  ->   https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

    Note:

    • Date format:  YYYY-MM-DD
    • Example: 

      DateRevisionChangesDocumentation Link
      2020-11-25REV02
      • Resistors R14 and R15 was replaced by 953R (was 5K1)
      • Resistor R5 was replaced by 5K1, R8 by 953R (was 9K09 and 1K69 respectively)
      REV02



    Scroll Title
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    titleBoard hardware revision number.


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    DateRevisionChangesDocumentation Link
    DateRevisionChangesDocumentation Link
    2024-04REV02
    1. Changed DCDC (U13) from EN6347QI to MPM3860GQW-Z and apdated according circuit.

    2. Connected DDR4-TEN signals together for U2, U3, U9, and U12 and pulled them low via 499 Ohm resistor R127. Added testpoint TP3 for signal DDR4-TEN.

    3. Changed voltage rail from 1.35 V to 1.45 V via adaption voltage divider resistor R30 and changed voltage rail name PL_GT_1V35 to PL_GT_1V45.

    4. Changed voltage rail from 1.05 V to 1.15 V via adaption voltage divider resistors R33 and R35 and changed voltage rail name PL_GT_1V05 to PL_GT_1V15.

    5. Added diode D2 between U41 pin 3 net MR and voltage rail 3.3VIN.

    6. Added capacitors C202 ... C205 for VTT voltage rail VTT.

    7. Added resistors R124 (default: not fitted) and R125 to supply U4 VCC either from PL_DCIN or from 3.3VIN.

    8. Changed resistor R76 from 4.22 kOhm to 9.09 kOhm to set current limit to nearly 14.3 A for U4.

    9. Changed inductor (L9) from XGL4030-301MEC to XGL5030-351MEC.

    10. Added remote sense option (default: not fitted):

      1. R126 for U30.

      2. R128 for U29.

      3. R129 for U31.

    11. Added decoupling capacitors:

      1. C208 for U4.

      2. C211, C212, and C213 for U6.

      3. C216 for U10.

      4. C214 for U26.

      5. C215 for U27.

      6. C210 for U34.

      7. C196 for U39.

      8. C197 for U40.

      9. C198 for U42.

      10. C199 for U41.

      11. C200 for U44.

      12. C201, C206, and C207 for U1.

    12. Added pull-up resistors for HOLD (R130) and WP (R131) signals for Flash U7.

    13. Added pull-up resistors for HOLD (R132) and WP (R133) signals for Flash U17.

    14. Changed capacitor (C132) from 1 nF, X7R to 1.2 nF, NP0.

    15. Changed 10 nF capacitor (C112) from 16 V, 0402 to 10 V, 0201.

    16. Changed 100 nF capacitors (C37, C95, C96, C130, and C131) from 6.3 V, X5R, 0201 to 50 V, X7R, 0402.

    17. Changed capacitor (C76, C77, C134, C195) from 1 µF, 16 V to 2.2 µF, 10 V.

    18. Changed capacitor (C129, C140, C141, C142, C143, C144, C145, C146, C147, C148, C153) from 10 µF, 16 V to 22 µF, 10 V.

    19. Changed 22 uF capacitor (C70, C73, C74, C75) from 0805 to 0603.

    20. Changed 22 uF capacitor ( C78, C80, C81, C82, C83, C84, C85, C86, C87, C110, C152, C154, C178) from 6.3 V to 10 V.

    21. Changed 100 Ohm resistors (R7, R10) from 0201, 0.05 W to 0402, 0.063 W.

    22. Changed resistor R77 from 12 kOhm to 10 kOhm.

    23. Changed resistors R41 and R58 from 2 kOhm to 2.49 kOhm.

    24. Added testpoints TP4, TP10, TP11, TP13, TP14, TP19, TP21, TP22, TP33 ... TP72.

    25. Added UKCA logo.

    26. Updated from library.

    27. Changed signal trace length.

    28. Updated documentation.

    REV02
    -REV01First Production ReleaseREV01


    Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

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    • Updated to board REV02.

    2023-03-02

    v.17

    • Corrected max possible DDR4 assembly option

    2023-01-16

    v.14

    ED

    • Fixed issue in absolute maximum ratings
    2022-11-08v.13ED
    • Initial Document

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