Page History

Overview

Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/TE0600

Trenz Electronic GigaBee XC6SLX series are industrial-grade FPGA micromodules integrating a leading-edge Xilinx Spartan-6 LX FPGA, Gigabit Ethernet transceiver (physical layer), two independent banks of 16-bit-wide 128/512 MBytes DDR3 SDRAM, 16 MBytes SPI Flash memory for configuration and operation, and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via robust board-to-board (B2B) connectors.

...

All this on a tiny footprint, smaller than half a credit card, at the most competitive price.

Block diagram

Image RemovedImage Added

Block diagram of the GigaBee XC6SLX board

Main components

Pictures were photographed from revision 3 and serve for informational purposes only.

Top side:

• Xilinx Spartan-6 LX FPGA
• clock generator
• 10/100/1000 Mbps Ethernet PHY
• protected 1-Wire EEPROM
• DDR3-SDRAM
• DC-DC converters

...

• Industrial-grade Xilinx Spartan-6 LX FPGA micromodule (LX45 / LX100 / LX150)

• 10/100/1000 tri-speed Gigabit Ethernet transceiver (PHY)

• 2 x 16-bit-wide 1 Gb (128 MB) or 4 Gb (512 MB) DDR3 SDRAM

• 128 Mb (16 MB) SPI Flash memory (for configuration and operation) accessible through:

• 1 kb protected 1-Wire EEPROM with SHA-1 Engine

• JTAG port (SPI indirect)

• FPGA configuration through:

  • B2B connector

  • JTAG port

  • SPI Flash memory

• Plug-on module with 2 × 100-pin high-speed hermaphroditic strips

• Up to 52 differential, up to 109 single-ended (+ 1 dual-purpose) FPGA I/O pins available on B2B strips

• 46.0 A 0 A x 1.2 V 2 V power rail

• 3.0 A x 1.5 A x 1.5 V 5 V power rail

• 2x 1A x 2.5V power rail

• 125 MHz reference clock signal

• Single-ended custom oscillator (option)

• eFUSE bit-stream encryption (LX100 or larger)

• 1 user LED

• Evenly-spread supply pins for good signal integrity

...

Power Consumption

Power consumption of GigaBee XC6SLX modules highly depend on the FPGA design implemented. Some typical power consumptions are provided below for the following reference systems:

• Boards – GigaBee XC6SLX 45/100/150

• Base board – TE0603-02

• Power supply – 5 V from 5 V for baseboard

• Connected Gigabit Ethernet cable

...

Board power supply diagram

Image RemovedImage Added

Power Supply Sources

...

FPGA VCCIO power options are shown below. Default values for configurable voltages are shown in braces.

Bank 0 power supply VCCIO 0 VCCIO0 can be configured by user to 3.3 V3 V, 2.5 V 5 V or 1.5 V5 V, see Chapter VCCIO0 Power Rail. Bank Banks 1 and 3 VCCIO supply voltage is configured to 1.5 V 5 V to communicate with DDR3 SDRAM memory chip.

...

...

Power Supervision

...

Board-to-board Connectors

EPROM

GigaBee XC6SLX board contains a Maxim DS2502-E48 node address chip with factory-programmed valid MAC-48 address and 768 bits of OTP-EPROM memory for user data.

...

For more information see Winbond W25Q128FV W25Q128JVEIQ (W25Q128BV till REV 02or W25Q128FV in old revisions) product overview.

Flash can be programmed in several ways:

...

The module also provides the footprint for custom 3.3 V additional 3.3 V single-ended oscillator (U12) which can be installed as an option used as a system and user clock for the FPGA (FPGA input pin Y13).

User LED

...

Unused IOB Pins option selection. 

In the standard assembly, the /WDO (watchdog output) line is left unconnected1 and the only possibility to reset the module is by driving the /MR (master reset) line active (low) through pin 18 of connector J2.

...

B2B signals count

Pin Labeling

...

Most pins of B2B connectors J1 and J2 are general-purpose, user-defined I/O pins (GPIOs). There are, however, up to 8 different functional types of pins on the TE0600, as outlined in Table below. In pin-out tables Table 11 and Table 12, the individual pins are colour-coded according to pin type as in Table below. 

TE0600 pin types

...

External Bank 2 differential clock connection

TE0600 -02 module have optional connection to FPGA bank 2 differential clock input pins. To provide connection from B2B_B2_L41_P signal to Y13 FPGA pin, zero-resistor R69 should be soldered. To provide connection B2B_B2_L41_N signal to AB13 FPGA pin, zero-resistor R81 should be soldered. Note that in this case optional user oscillator U13 can't be used.

...

J2 Pin-out

J2 Pin-out

Signal Integrity Considerations

...

Traces of differential signals pairs are NOT routed with equal length, although difference in signal lines length is negligible for actual signal frequencies. For applications where traces length has to be matched or timing differences have to be compensated, Tables below abowe list the trace length of I/O signal lines measured from FPGA balls to B2B connector pins.

...

Board revisions pin coding

Board revisions pin coding

Main Main differences between 01 and 02 revisions:

...

• Optimized placement and routing for DC/DC converters
• Added thermal vias to mounting holes
• Added Testpoints
• Changed Board revision identification to REV03
• Changed U9 from SIT1602AI-83-33E-25.0000 to SiT8008AI-73-XXS-25.000000E
• Added Track-it™ Traceability Pad
• Change SPI Flash from W25Q128BVEIG to W25Q128FVEIG
• DDR3 changed from IM4G16D3EABG-125I to IM4G16D3FABG-125I for the 4 GBit variants
• U13 (DS2432P+) is no longer populated by default

...

Main differences between 03 and 04 revisions:

• Optimized placement and routing
• More powerful regulators
• Removed stucked vias
• Added Testpoints
• Changed Board revision identification to REV04
• U12 was fitted for all module assembly variants as default

Module assembly variants coded by 4 zero ohm resistors, connected to FPGA AV[3:0] pins. All these pins should be configured to have internal PULLUP.

Assembly variants pin coding

...

GigaBee XC6SLX has 4 mounting holes, one in each corner. The module can be fixed by screwing M3 screws (ISO 262) onto a carrier board through those mounting holes. 

Operating Temperature Ranges

...

Disclaimer