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id | Comments |
Important General Note:
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Export PDF to download, if vivado revision is changed!
Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
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Figure template (note: inner scroll ignore/only only with drawIO object):
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Create DrawIO object here: Attention if you copy from other page, use |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Table template:
- Layout macro can be use for landscape of large tables
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Table of contents
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Overview
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Zynq PS Design with DDR Less FSBL Example.
Refer to http://trenz.org/te0722-info for the current online version of this manual and other available documentation.
Key Features
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Excerpt |
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Revision History
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anchor | Table_DRH |
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title | Design Revision History |
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- TE Script update
- rework of the FSBLs
- DDR LESS, Device ID, Sensor+LED access
- VIO for RGB access
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- initial release
Release Notes and Know Issues
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anchor | Table_KI |
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title | Known Issues |
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Requirements
Software
- list of software which was used to generate the design
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anchor | Table_SW |
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title | Software |
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- list of software which was used to generate the design
Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
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Design supports following carriers:
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anchor | Table_HWC |
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title | Hardware Carrier |
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Additional HW Requirements:
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anchor | Table_AHW |
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title | Additional Hardware |
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for JTAG, UART
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For general structure and of the reference design, see Project Delivery
Design Sources
- content of the zip file
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File
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File-Extension
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Description
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Debian SD-Image
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*.img
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Debian Image for SD-Card
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MCS-File
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*.mcs
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Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
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MMI-File
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*.mmi
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File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
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SREC-File
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*.srec
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Converted Software Application for MicroBlaze Processor Systems
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anchor | Table_PF |
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title | Prebuilt files (only on ZIP with prebult content) |
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File
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File-Extension
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Description
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Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
Design Flow
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Notes :
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
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- (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
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- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
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(alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
Note: See SDK Projects
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TE0722 is without DDR, so special FSBL (sources on reference designs) is needed, see also: DDR less ZYNQ Design |
Launch
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Note:
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Basic Information, see TE0722 Getting Started
Programming
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
QSPI
Optional for Boot.bin on QSPI Flash and image.ub on SD.
- Connect JTAG and power on carrier with module
- Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
- Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp fsbl_app
Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
SD
Xilinx Zynq devices in CLG225 package do not support SD Card boot directly from ROM bootloader. Use QSPI for primary boot and SD for secondary boot only. See also Xilinx AR#66846
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section 68616275
- Connect UART USB (most cases same as JTAG)
- Power On PCB
Note: 1. Zynq Boot ROM loads FSBL from QSPI into OCM, 2. FSBL loads bitfile from qsi, 3. FSBL starts application (included into the FSBL Code)
Baremetal App
Note: UART over J2 is used, this is only available, if PL part is configured with correct UART connection.
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- Speed: 115200
- COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
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Vivado HW Manager
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Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)
- Control:
- Enable/Disable RGB LED Counter (default on)
- Enable/Disable different colors (default all off)
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System Design - Vivado
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Block Design
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Note:
optional for Zynq / ZynqMP only
- add basic PS configuration
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anchor | Table_PSI |
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title | PS Interfaces |
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Constrains
Basic module constrains
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# Common BITGEN related settings for TE0722
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] |
Design specific constrain
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set_property PACKAGE_PIN K15 [get_ports UART_0_txd]
set_property PACKAGE_PIN L13 [get_ports UART_0_rxd]
set_property IOSTANDARD LVCMOS33 [get_ports UART_0_*] |
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#RGB LED
#R
set_property PACKAGE_PIN J15 [get_ports {RGB_LED[0]}]
#G
set_property PACKAGE_PIN L14 [get_ports {RGB_LED[1]}]
#B
set_property PACKAGE_PIN K12 [get_ports {RGB_LED[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RGB_LED[*]}] |
Software Design - SDK/HSI
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For SDK project creation, follow instructions from:
Application
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FPGA Example
scu
MCS Firmware to configure SI5338 and Reset System.
srec_spi_bootloader
TE modified 2018.3 SREC
Bootloader to load app or second bootloader from flash into DDR
Descriptions:
- Modified Files: blconfig.h, bootloader.c
- Changes:
- Add some console outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash
xilisf_v5_11
TE modified 2018.3 xilisf_v5_11
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Zynq Example:
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- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY
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ZynqMP Example:
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- Display FSBL Banner and Device Name
Module Specific:
- Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO
zynqmp_fsbl_flash
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zynqmp_pmufw
Xilinx default PMU firmware.
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General Example:
hello_te0820
Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
Source location: \sw_lib\sw_apps
zynq_fsbl
TE modified 2018.3 FSBL
General:
- Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device ID
- Disable Memory initialisation on main.c
Module Specific:
- Add Files: all TE Files start with te_*
- Example app LED and sensor access
zynq_fsbl_flash
TE modified 2018.3 FSBL
General:
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Authors
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