Page History
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Template Revision 1.4.1 (modified)
Basic Notes
- export PDF to download, if vivado revision is changed!
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Revision History
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Date | Vivado | Project Built | Authors | Description |
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2018-0108-3127 | 2017.1 | TE0706_zsys_SDSoC_EDDP_FOC-vivado_2017.1-build_05_20180827095117.zip | UTIA | initial release |
Release Notes and Know Issues
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For general structure and of the reference design, see Project Delivery - AMD devices
Design Sources
Type | Location | Notes |
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Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib | Vivado Project will be generated by TE Scripts |
SDK/HSI | <design name>/sw_lib | Additional Software Template for SDK/HSI and apps_list.csv with settings for HSI |
PetaLinux | <design name>/os/petalinux | PetaLinux template with current configuration |
SDSoC | <design name>/../SDSoC_PFM | SDSoC Platform will be generated by TE Scripts or as separate download |
Additional Sources
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Reference Design is available on:
Hardware Setup
TE0706_zsys_SDSoC_EDDP_FOC 2017.1 Platform with TEC0053-04 - EDPS Power Stage
3-phase brush-less DC motor control with field oriented control (FOC) algorithm implemented in SDSoC 2017.1 on TE0720 module and TE0706-02 carrier board. The TEC0053-04 - EDPS Power Stage controls the BLDC motor with mounted encoder.
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- SDSoC Environment - User Guide (UG1027)
- SDSoC SDSoC Environment User Guide - An Instruction to SDSoC Environment (UG1028)
- SDSoC SDSoC Environment User Guide - Platforms and Libraries (UG1146)
- EDDP Resources - Sources and documentation of the original EDDP Development kit
Appx. A: Change History and Legal Notices
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v.7 | UTIA |
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2018-08-15 | v.1 |
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Overview
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